AU692670B2

AU692670B2 - Dram emulator

Info

Publication number: AU692670B2
Application number: AU46144/96A
Authority: AU
Inventors: Robert Linley Muir
Original assignee: Aristocrat Leisure Industries Pty Ltd
Current assignee: Aristocrat Technologies Australia Pty Ltd
Priority date: 1995-02-10
Filing date: 1996-02-08
Publication date: 1998-06-11
Anticipated expiration: 2016-02-08
Also published as: AU4614496A

Description

DRAM EMULATOR Introduction

The present invention relates generally to slot machines and in particular the invention provides an improved memory system for use within a slot machine.

Regulatory authorities charged with the responsibility of ensuring that gaming machines are operated fairly and are, as far as possible, immune to fraudulent operation have become increasingly stringent in recent years in order to stamp out undesirable practices. In the process, some of these authorities have introduced rules for the design of gaming machines which attempt to prevent the machine from being operated in any manner other than that in which it was intended to operate. One such rule which some authorities have imposed is that programmes controlling the operation of a slot machine cannot run in RAM. This presents a particular problem where the designer of a gaming machine such as a video slot machine wishes to use dynamic RAM to provide the speed required for video manipulation in this type of machine, it is also a problem when the processor selected to control a slot machine is of a type which is designed only to operate with dynamic RAM.. Summary of the Invention

According to a first aspect the present invention consists in a dynamic RAM emulator comprising a block of addressable memory and address control means arranged to address a selected word within the block, the address means including row and column latches for demultiplexing and latching a multiplexed address asserted on an address bus of a processor or a decoded memory selection signal derived from the multiplexed address, a data output arranged to be connected to a data bus of the processor and control logic to control latching of the address or memory selection signal, and enabling of the data output, said control logic also being arranged to override a data bus output enable of the processor and to enable or disable outputs of other memory devices connected to the data bus in accordance with the address latched in the address latch.

According to a second aspect, the present invention consists in a slot machine comprising game playing means and control means wherein the control means includes memory means incorporating the dynamic RAM emulator as hereinbefore described. Brief Description of the Drawings

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

Figure 1 schematically illustrates the electrical configuration of a sl machine using an embodiment of the present invention;

Figure 2 is a block diagram of a first embodiment of a dynamic RA emulator made in accordance with the present invention; and

Figure 3 is a block schematic of a second embodiment of a dynamic RAM emulator made in accordance with the present invention. Detailed Description of the Embodiments

Embodiments of the invention will be described with reference to a gaming machine, the electrical configuration of which is illustrated in Figur 1. This machine makes use of an Application Specific Integrated Circuit (ASIC) containing a RISC processor which interconnects as shown in Figure 1.

A large majority of the functions of the gaming machine control system are built into the ASIC integrated circuit which provides:

A 32 bits RISC processor

Dynamic RAM Controller - VGA resolution video controller along with 12 bit video DAC'S

Stereo eight voices sound generation

System glue logic, eg. Chip Enable lines and Wait State generation

Interrupt controller

Clock dividers The processor connects to three system buses:

A high speed (16 MHZ), 32 bit bus

A low speed, 8 bit. I/O bus

The Interrupt Bus These buses are isolated by data and address latches. The high speed 32 bit bus is used to interface with the CPU memory, of which three types are used:

EPROM

DRAM

DRAM EMULATOR 21 The ASIC processor is designed to run very quickly from Dynamic Memory using the "page mode" of the DRAM. The Device can interface to a maximum of 4 Mbytes of DRAM.

The DRAM contains the screen data with the result that part of the bandwidth of the system is lost while transferring video data to the DAC's.

Certain regulatory authorities currently do not approve the concept of having code running in DRAM. In order to assure top performance for a VGA system the architecture includes electronics that simulate the DRAM using very fast bipolar PROMS. The DRAM emulator 21 is read only and can provide from 256 to 1024 32 bit words.

Another reason to use the DRAM Emulator 21 is that the interrupt system in the ASIC processor is implemented in a way that requires at least one instruction per interrupt in DRAM. This causes problems with those authorities that do not allow machines having code running in DRAM. Gaming jurisdictional bodies may require that no CPU code be executed from RAM. However, microprocessors are often designed so that an interrupt causes execution to commence in the RAM space. In particular the ASIC processor is designed to use dynamic RAM and the interrupt vector is intended to be located in the DRAM space. The instruction executed is usually a jump back to a location in EPROM. but even this may not be allowed by the authorities. The DRAM emulator 21 is designed to map high speed PROM into the address space occupied by the interrupt vector table to ensure acceptable performance of machines running animation on high resolution screens. The system has 1 Mbyte of dynamic RAM as standard, with provision for an optional extra bank of 1 Mbyte.

The system implements the emulation of normal DRAM with high speed (25 nsec) bipolar PROM. The circuit is loaded only in those markets that do not allow to run code from DRAM. The DRAM Emulator 21 can provide from 256 to 1024 32 bit words of PROM.

It has been estimated that with the usage of the DRAM emulator 21, the performance will be increased by 30% over an EPROM equivalent.

A CGA system should run from normal EPROM with 12 MHZ clock with excellent animation. Referring to Figure 2, during the DRAM Cycle the multiplexed address is latched by the DRAM emulator 21 in transparent latches 22.23 and compared in control logic 24 to the selected address, which for the interrupt vectors is page zero (IK words). When page zero is addressed th PROM is enabled (O/E) and the respective DRAM output enable (DRAM O or DRAM OE1) is inhibited. This latched address also supplies a demultiplexed address to the PROMs.

The EMUL-FITTED signal enables or disables the DRAM emulator. When disabled, the entire memory space is connected to DRAM, whereas when enabled the DRAM emulator PROM is mapped to page 0.

The ASIC processor has 4 CAS outputs. CAS[3:0]. which are used t control the individual bytes making up each 32 bit word. Only one of thes

CAS lines is required to latch the address, as on an instruction fetch all 4 lines are asserted.

Referring to Figure 3 a second embodiment is illustrated which provides only the minimum requirement to implement the invention wher only vectors are stored in the emulator memory. In this embodiment only fixed jump relative instruction is stored in the Emulator memory providing jump to another vector table in the machine's EPROM address space. Thus all instructions are identical and only 1 word of storage is needed for all locations. This is implemented as simple logic buffers 26 with hard wired inputs 25.

Latched addresses as such are not required except for the control logic 27 which decides whether or not to enable the DRAM Emulator. Onl the decoded results of the row and column addresses indicating an address within the DRAM emulator address range need be latched, but not the actu addresses themselves.

In an extended version of the embodiment of Figure 3 an extra inpu is provided to the control logic which disables the on board DRAM emulato and instead causes the control logic to select an external emulator memory, typically located on a memory expansion board and which can be compose of bipolar DRAMs.

The signals in the circuit of Figure 3 have the following descriptions :-

RA[9:0]: DRAM multiplexed address inputs.

IENABLE: selects emulator enabled or disabled (production build option) XENABLE: selects external DRAM emulator enabled or disabled. From memory expansion board.

ROWOK, COLOK: Internal latched row/col address ok for DRAM emulator.

PROMOE: Enable for emulator logic buffers. PROMOEZ: Enable for external emulator memory. DRAM OE 0/1 )

DRAM control lines.

DRAM WE 0/1 D[31:0]: CPU data bus.

It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Claims

CLAIMS:

1. A dynamic RAM emulator including a block of addressable memor and address control means arranged to address a selected word within the block, the address means including row and column latches for demultiplexing and latching a multiplexed address asserted on an address bus of a processor or a decoded memory selection signal derived from the multiplexed address, a data output arranged to be connected to a data bus the processor and control logic to control latching of the address or memor selection signal, and to enable the data output, said logic also being arrang to override a data bus output enable of the processor and to enable or disab outputs of other memory devices connected to the data bus in accordance with the address latched in the address latch.

2. The dynamic RAM emulator of claim 1 wherein the block of addressable memory is implemented as a PROM.

3. The dynamic RAM emulator of claim 1 wherein the block of addressable memory is implemented as one or more logic buffer arrays, eac array being one data word wide and each array having a hard coded input.

4. The dynamic RAM emulator of claim 3 wherein each logic buffer array input is provided by a switch.

5. The dynamic RAM emulator of claim 3 wherein the inputs of each logic buffer array are hard wired with logic levels representing an input code.

6. The dynamic RAM emulator as claimed in any one of claims 3, 4 or wherein a single logic buffer array is coded as a jump relative instruction and the address decoding is arranged such that the single logic buffer array occupies a plurality of addresses.

7. The dynamic RAM emulator as claimed in any one of claims 1 to 6 wherein a plurality of low order address lines are demultiplexed to address discreet words in the address space of the block of addressable memory an the remaining address lines are demultiplexed and decoded to provide an enable signal for the dynamic RAM emulator.

8. The dynamic RAM emulator as claimed in any one of claims 3 to 6 wherein the address lines are demultiplexed and decoded to provide an enable signal for each array of logic buffers.

9. The dynamic RAM emulator as claimed in claim 8 wherein several addresses in the address space of the block of addressable memory are decoded to select a single array of logic buffers.

10. A slot machine having game playing means and control means wherein the control means includes memory means incorporating a dynamic RAM emulator including a block of addressable memory and address control means arranged to address a selected word within the block, the address means including row and column latches for demultiplexing and latching a multiplexed address asserted on an address but of a processor or a decoded memory selection signal derived from the multiplexed address, a data output arranged to be connected to a data bus of the processor and control logic to control latching of the address or memory selection signal, and to enable the data output, said logic also being arranged to override a data bus output enable of the processor and to enable or disable outputs of other memory devices connected to the data bus in accordance with the address latched in the address latch.

11. The slot machine of claim 10 wherein the block of addressable memory is implemented as a PROM.

12. The slot machine of claim 10 wherein the block of addressable memory is implemented as one or more logic buffer arrays, each array being one data word wide and each array having a hard coded input.

13. The slot machine of claim 12 wherein each logic buffer array input is provided by a switch.

14. The slot machine of claim 12 wherein the inputs of each logic buffer array are hard wired with logic levels representing an input code.

15. The slot machine as claimed in any one of claims 12, 13 or 14 wherein a single logic buffer array is coded as a jump relative instruction and the address decoding is arranged such that the single logic buffer array occupies a plurality of address.

16. The slot machine as claimed in any one of claims 10 to 15 wherein a plurality of low order address lines are demultiplexed to address discreet words in the address space of the block of addressable memory and the remaining address lines are demultiplexed and decoded to provide an enable signal for the dynamic RAM emulator.

17. The slot machine as claimed in any one of claims 12 to 15 wherein the address lines are demultiplexed and decoded to provide an enable sign for each array of logic buffers.

18. The slot machine as claimed in claim 17 wherein several addresse in the address space of the block of addressable memory are decoded to select a single array of logic buffers.