JPS6299983A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the influence of the fluctuation of a supply voltage to reading out operations so as to shorten a readout access time, by suppressing the fluctuation of the bias voltage of an amplifier circuit constituting a sense amplifier by using a capacitor and resistance. CONSTITUTION:The storing state of a selected storage cell (m) is inputted to a differential amplifier 1 through a data line D, row selecting switch M, and common data line Dc and the differential output of the amplifier 1 is inputted to a sense amplifier 2. Emitters of the bipolar transistors Q3 and Q4 of the sense amplifier 2 are connected with a negative-side power source Vee through constant-current circuits 21 and 22 and a base bias voltage Vb which is applied across the commonly connected bases of the transistors Q3 and Q4 is produced by a resistance R3 and constant-current circuit 23. Fluctuation of the voltage across the common bases is suppressed and averaged by the charging and discharging of a capacitor C1 connected between the common bases and negative-side power source Vee and the capacitor C1 and resistance R3 surely suppress the fluctuation of the base bias voltage Vb with a time constant of a fixed magnitude.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor memory device technology and a particularly effective technology applicable to RAM (Random Access Memory), such as B+ -CMO8 type O8 type. logic circuit) 1f! : S-RAM used (Statenk type RA
M) It relates to effective technology that can be used for.

[Background technology]

For example, "Nikkei Electronics August 12, 1985 issue (No. 37 May 187-20)" published by Nikkei McGraw-Hill.
8 shows a 5-RAM using a so-called Bi-CMO8 type O8 circuit in which a bipolar element and an MO8 element are combined in a logic circuit. This Bi-0 MO8 type 5-RAM is attracting attention as it combines the advantages of low power consumption of MO8 elements and high drive performance of bipolar elements.

FIG. 4 shows a part of the structure of the Bi-CMO8 type S RAM.

The 5-RAM shown in the figure selects a memory cell m by a word line W and a data line, and determines the memory state of the selected memory cell m. It is designed to be read by sense amplifier 2.

The word line W is connected to a row decoder (not shown). One end of the data line has a load MOS transistor M3. It is pulled up to the power supply vec side through M4y, and the other end is connected to the common data line Da through column selection switches M1 and M2. Word line W and data aD are selected by row selection signal bird and Y selection signal Yn, respectively. Both selection signals Xm and Yn are generated by decoding address data applied from the outside.

The storage state of the selected storage cell m is determined by the data line 9 column selection switches Ml, M2 . First, the signal is input to the differential amplifier 1 via the common data line DC. The differential amplifier l has the emitters of a pair of bipolar transistors Ql and Q2 connected in common, and this common emitter is connected to a negative power supply Vee via a constant 1X current circuit 11.

The base of Q2 is a differential input. Then, mutually complementary differential outputs are taken out from the collectors of the pair of transistors Ql and Q2, and are input to the sense amplifier 2 at the next stage.

Sense amplifier 2 consists of a pair of bipolar tube transistors Q
3. This is a type of differential amplifier configured using Q4Y.

Each transistor Q3. Each Q4 constitutes a common base type amplifier circuit. The differential output from the differential amplifier 1 is input to the emitter sides of transistors Q3 and Q4. On the other hand, the outputs Sl and S2 of the sense amplifier 2 are taken out in the form of differential outputs from the collector sides of the respective transistors Q3 and Q4. The differential outputs Sl and S2 of this sense amplifier 2 are:
Although not shown, the signal is output to the outside via a buffer circuit.

Here, a pair of bias transistors Q3. in the sense amplifier 2. Q4 is each 1, and its collector is connected to the positive power supply V CC via load resistors R1 and R2. Clamp diodes DI and D2 are connected in parallel to the load resistors R1 and R2, respectively. In addition, each bipolar transistor Q3. The emitters of Q4 are each
It is connected to the negative power supply VeeK via constant current circuits 21 and 22. Both transistors Q3. The bases of Q4 are commonly connected to each other, and a constant base bias voltage vb is applied to this common base. In this case, in the circuit shown in FIG. 4, the base bias voltage Vb is created by the diode D3 and the constant current circuit 23. By applying a constant forward direction to the diode D3 in the constant current circuit 23, a constant forward magnetic pressure is generated at both ends of the diode Dl. This J-direction voltage serves as the base bias voltage vb of the transistor Q3. It is designed to be given on the common base of Q4.

By the way, the inventors of the present invention have found that this type of semiconductor memory device has the following problems.

That is, the operating power supply VCC of the sense amplifier 2.

Vee is used together with other circuits in the semiconductor integrated circuit device, such as peripheral circuits such as peripheral decoders and buffer circuits.
It is distributed and supplied from a common power supply bus. For this reason,
For example, when address data is switched, the operating state of peripheral circuits changes significantly, and the power supply current flowing within the semiconductor integrated circuit device changes instantaneously. This instantaneous fluctuation in the power supply current corresponds to the instantaneous fluctuation in the power supply voltage (
or vibration). When the voltages of the power supplies Vec and Vee vary instantaneously, the influence of this variation appears as a variation in the base bias voltage vb of the sense amplifier 2. This variation in the base bias voltage vb is caused by the sense amplifier 2
This becomes a kind of noise that disturbs the normal operation of the sense amplifier 2, and this causes an abnormality to appear in the differential outputs Sl and 32 of the sense amplifier 2.

FIG. 5 shows the differential outputs S 1 , S 2 of the 1 sense amplifier 2 when the IL source voltage (Vcc) changes instantaneously.
The abnormal state that appears in -fl! shows. In the same figure (・te,
Point A indicates the position where the differential outputs Sl and S2 of the sense amplifier 2 are inverted and switched due to address data switching. This switching of the differential outputs 81 and 82 at point A is normal and occurs depending on the storage state of the selected storage cell. However, at the subsequent point B, the differential output Sl of the sense amplifier 2.

The level difference of S2 is partially reduced. Differential output 31. at this point B. The decrease in the level difference of S2 is not due to the storage state of the selected memory cell (but is due to an abnormal operation caused by voltage fluctuations of the power supply VCC. In this way, the level difference of the differential output Sl, 82 decreases. This means that the S/N ratio of the differential outputs SL and S2 decreases, which delays the timing of determining successive data and prevents shortening of read access time. It's a good idea not to take too much time (
Become. Furthermore, there is an increased risk that the read content will be reversed due to the slightest trigger.

As described above, in the semiconductor memory device partially shown in FIG. 4, instantaneous fluctuations in the power supply voltage lengthen successive access times, and errors tend to occur in read operations. The present inventors have clarified that there is a point.

[Purpose of the invention]

The purpose of the present invention is to reduce the influence of fluctuations in power supply voltage on successive operations (thus making it possible to shorten successive access time, and to ensure read operations with a high S/N ratio and no fear of errors). It is an object of the present invention to provide a semiconductor memory device technology that is capable of performing the following steps.

The above and other objects and novel features of the present invention will become apparent from the description of Specification 1 and the accompanying drawings.

[Summary of the invention]

A brief description of typical inventions disclosed in this application is as follows.

In other words, the bias voltage of the amplifier circuit that makes up the sense amplifier? What is the variation of the bias voltage given by the resistor and constant current circuit? It is designed to be suppressed by charging and discharging the capacitor, and by using a resistor to generate bias voltage, it is possible to effectively suppress fluctuations in bias voltage even with a relatively small capacitor. This makes it possible to reduce the influence of power supply voltage fluctuations on read operations, shorten read access time, and ensure successive operations with a high S/N ratio without the risk of noise. It is intended to achieve the purpose of making it possible to obtain.

〔Example〕

Hereinafter, typical embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor memory device to which the present invention is applied.

The semiconductor memory device partially shown in the figure is a Bi-0MO8 type 5-RAM, and its basic configuration is almost the same as that shown in FIG.

That is, in the semiconductor memory device shown in FIG. 1, first, a memory cell mY is selected using a word aW and a data line, and the memory state t of the selected memory cell m is read out by the sense amplifier 2.

The word line W is connected to a row decoder (not shown). One end of the data line has a load MOS transistor M3. M4? : Pulled up to the power supply VCC side via
Other end side or column selection switch M1. It is connected to the common data line Dc via M2'. Word line W and data line are selected by row selection signal Xm and Y selection signal Yn, respectively. The internal selection signals Xrn and Yn are generated by decoding address data applied from the outside.

The storage state of the selected storage cell m is determined by the data line D1 column selection switches Ml, M2 . The differential amplifier 1 is first inputted to the differential amplifier 1 through the common data line Dc. (
- is connected to the negative side power supply Vee, and its pair of transistors Ql.

The base of Q2 is a differential input. Then, mutually complementary differential outputs are taken out from the collectors of the pair of transistors Ql and Q2, which are sent to the sense amplifier 2 in the next stage.
is input.

Sense amplifier 2 includes a pair of bipolar transistors Q
3. It is a kind of differential amplifier constructed using QtY. Each transistor Q3. Each Q4 constitutes a common base type amplifier circuit. The differential output from the differential amplifier 1 is input to the emitter sides of transistors Q3 and Q4. On the other hand, the outputs 81 and 32 of the sense amplifier 2 are taken out in the form of differential outputs from the collector sides of the respective transistors Q3 and Q4. Differential output 81 of this sense amplifier 2. Although not shown, S2 is outputted to the outside via a buffer circuit.

A pair of bipolar fist transistors Q in sense amplifier 2
3. Q4 each has its collector connected to the load resistance Jul,
The positive side power supply VCCK is connected via R2. Clamp diodes DI and load resistors R1 and R2 are respectively provided.
D2 are connected in parallel. Also, the emitters of each bipolar transistor Q3゜Q4 are connected to constant current circuits 21゜22? : 1 minus 1! lj power supply Vee. The bases of both transistors Q3tQ4 are commonly connected to each other, and a constant base bias voltage vb is applied to this common base.

Furthermore, fixed? The Itft circuit 21.22123 is composed of a bipolar transistor whose base is supplied with a constant control voltage Vcs.

In the circuit of the embodiment shown in FIG. 1, the base bias voltage vb is created not by the diode and the constant current circuit, but by the resistor R3 and the constant current circuit 23. By causing a constant current to flow through the resistor R3 in the constant current circuit 23, a constant voltage drop is divided across the resistor R3. This drop α pressure serves as the base bias voltage vb of the transistor Q3. It is designed to be given on the common base of Q4. In this case, its resistance R
The value of 3 is preset so that the product of the current flowing by the constant current circuit 23 and the resistance value is equivalent to the forward voltage of the diode.

Furthermore, the base bias voltage vb is set to resistor R3? A capacitor C1 is connected between the common base to which the base bias voltage vb is applied and the negative power supply Vee. This capacitor C1 is always charged and discharged to the potential at the common base.

As mentioned above, bipolar transistor Q3 . Capacitor C on the common base of Q4
By connecting IY, voltage fluctuations, sometimes instantaneous voltage fluctuations, at their common base are removed by capacitor C1.
The charging and discharging of 1 is suppressed by operation and becomes averaged. What should be noted in this case is that the base bias voltage Vb is applied using a resistor rt3'& instead of a diode. As a result, the resistor R3 is always interposed in series between the capacitor C1 and the power supply vCC, and as a result, the capacitor C1 and the resistor R3 are always connected to the base bias voltage with a time constant of a constant magnitude. It becomes possible to reliably suppress fluctuations in vb.

Incidentally, as in the circuit shown in FIG.
If you make it with
and are directly connected by the forward direction of the diode υ3. As a result, the base bias voltage v
It becomes difficult to sufficiently suppress b, and even if it were possible, a capacitor with a large capacity that cannot be formed within a semiconductor integrated circuit device would be required.

On the other hand, in the circuit of the embodiment shown in Figure J1, as mentioned above, the resistor R3 is always interposed between the capacitor C1 and the power supply Vcc, so that the capacitance of the capacitor C1 is a small value of, for example, about 19F. Even in this case, a time constant large enough to suppress fluctuations in the base bias pressure vb can be obtained. As a result, it is possible to reduce the influence of power supply voltage fluctuations on the read operation, accelerate the timing of determining successive data, and shorten the Z output access time.
A read operation with a high ratio and no possibility of error can be reliably obtained.

FIG. 2 shows an example of the state of the differential output 31.82 of the sense amplifier 2 when the voltage of the power supply Vcc changes instantaneously due to switching of address data in the semiconductor memory device partially shown in FIG. shows. In the figure, A is the differential output of the sense amplifier 2, Sl, by switching the address data.

S2 is reversed to indicate the switching point. This change in the human score is caused by the storage state of the selected storage cell. After this, the differential output Sl.

S2 maintains the level difference above a certain level regardless of the voltage fluctuation of the power supply Vcc. In other words, the differential outputs 81 and 32 from the sense amplifier 1 become stable immediately after the address data is switched.

:xS Figure 3 shows an overview of the overall configuration of 5-RAM to which the present invention is applied.

The 5-RAM shown in the figure includes a memory matrix 100 formed by arranging a large number of memory cells in a matrix of rows and columns, and a memory cell in this memory matrix that is used as address data Ai.
Row decoder 110 and column decoder 1 to select based on n
20, read/write control and sense amplifier 130, input data control unit 1 that controls input data Din, etc. based on '+filJ control data WE, C8
40. and a sense amplifier/output buffer 150 for outputting read data Dout'.

〔effect〕

ill The bias voltage of the amplifier circuit that makes up the sense amplifier output is provided by a resistor and a constant current circuit, and by suppressing the fluctuation of the bias voltage by charging and discharging the capacitor, the bias voltage can be adjusted even with a capacitor of relatively small capacity. Fluctuations can now be effectively suppressed, thereby reducing the influence of power supply voltage fluctuations on read operations, and making it possible to accelerate the timing of determining the sense amplifier output after address data has been switched. This has the effect of shortening access time.

(21) Also, by reducing the influence of fluctuations in the 1 Jt volatile voltage on the successive readout operation, it is possible to reliably obtain a readout operation with a high S/N ratio and no risk of error.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

Although the invention made by the present inventor is applied to the technology of Bi-CMO8 type 5-RAM, which is the background field of application, it is not limited thereto, and for example, pure MO8 type. The present invention can also be applied to storage device technologies other than 5-RAM or random access memory.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a main part of a semiconductor memory device according to the present invention, FIG. 2 is a waveform chart showing an operating state of the semiconductor memory device shown in FIG. 1, and FIG. 5-A block diagram showing an overview of the applied RAM; FIG. 4 is a partial circuit diagram of a semiconductor memory device considered before this invention; FIG. 5 is an operation of the semiconductor memory device shown in FIG. 4. It is a waveform chart showing the state. m...Storage cell, D...Data line, Dc...Common data line, l...Differential amplifier, 2...Sense amplifier, Sl. S2...Sense amplifier output, Q3. Q4... Bipolar transistor that constitutes the sense amplifier, Vb.
... Bipolar ψ transistor Q3. Q4 common base bias 'tortoise pressure, vcc, Vce...power supply, R3...
・Resistance, C1... Capacitor.

Claims (1)

[Claims] 1. A semiconductor memory device in which a sense amplifier reads out the memory state of a memory cell arbitrarily selected from among a large number of memory cells, wherein the sense amplifier is a common-base type transistor amplifier circuit. In order to provide a base bias voltage to this common base type transistor amplifier circuit, a resistor and a constant current circuit are connected to its base.
Furthermore, the semiconductor memory device 2 is characterized in that its base is connected to a power supply via a capacitor, and the sense amplifier constitutes a differential amplifier circuit by a pair of bipolar transistors whose bases are commonly connected. A semiconductor memory device according to claim 1, characterized in that: