JPS629911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a display device using a raster scan method,
In particular, the present invention relates to a display device in which pattern data can be easily rewritten.

Simple raster scan display devices display predetermined characters or special patterns in one specified color in each character corner, and cannot display multiple colors in the same character corner. On the other hand, there is an example of displaying in multiple colors by multiplexing the pixel memories that generate the display pattern of one character segment, reading them out at the same time, and displaying them in an overlapping manner. (Special request 1977
(No. 138080, Multi-Color Pixel Display Device) In this example, the corresponding code must be written as an address for each pattern of each pixel memory to be superimposed. Therefore, if the pattern to be written is a multicolor pixel pattern, the pattern must be separated into primary colors and written on each sheet, which is not an easy task. Furthermore, when you want to add a pattern with the same code to a pattern that has already been written, it is not allowed to leave the previous part; instead, save the pattern in advance in the program, and use the saved pattern data. Logically process the newly added pattern data,
There was a drawback that the pattern to be written had to be recreated and written.

An object of the present invention is to provide a display device in which pattern data can be easily rewritten.

First, the present invention will be summarized based on some embodiments.

First, by simultaneously erasing only the patterns corresponding to one piece of display state information (designation of color, blink, etc.) in multiple pixel memories that are displayed in an overlapping manner, it is possible to easily erase part of the patterns within the pixels. I did it like that.

The second method is to add new patterns to multiple pixel memories that are displayed in an overlapping manner without erasing the patterns that have already been written.
Additional back writing to patterns within pixels can be easily performed.

Third, by adding a new pattern to multiple pixel memories that are superimposed and displaying them, without erasing the old previous pattern, except for the parts that overlap with the already written pattern and the new pattern, the pixel Additional front writing to inner patterns can now be done easily.

A more specific description of each of the above points is as follows.

By reading out multiple pixel memories at the same time during display scanning and superimposing each one as a unit of display status information such as color or blinking, multicolor and blinking lighting can be achieved within one character corner. There are display devices that are capable of displaying dots and non-blinking lit dots. With this plurality of pixel memories, it is difficult to write or erase data to or from a group of pixel memories that are simultaneously read out. Although it is not impossible, the process of creating and writing the pattern data is complicated and difficult to use, and many advanced functions are lost due to this. Therefore, it is designed to make it easier to partially write and partially rewrite this pattern data.In response to external writing to a group of multiple pixel memories that are simultaneously read out and displayed, the pixel memory is read out, The data is logically processed together with new data to be written and control information such as erasure, back/front writing, etc., and then written into the pixel memory.

One specific example of implementing the apparatus of the present invention will be described in detail below with reference to the drawings.

The position where the circuit constituting the device of the present invention is attached will be explained with reference to FIG. In synchronization with the raster scan of the display device, the horizontal direction X coordinate (horizontal direction count signal) and the vertical direction Y coordinate (vertical direction count signal) are given to the X/Y converter 131, and the one-dimensional memory address is address register 1
32, and then its output is given to the refresh memory 130 as an address. In the refresh memory 130, information on the displayed screen is stored in one-to-one correspondence with the position on the screen. In the example of this display device, the data stored in the refresh memory 130 is
It is assumed that a display pattern is stored as a code for each character corner, such as alphanumeric characters to be displayed.

Data read out from the refresh memory 130 in synchronization with the raster scan is set in the data register 133.

Here, an example of data set in the data register 133 is shown in FIG. In the example in Figure 2,
An example of 16 bits per word is shown, where the code content is given in the lower 8 bits, the upper 4 bits are control information, followed by blink (BL) designation bits, followed by blue (B) and green. (G:
Three color designating bits, Green) and Red (R), are provided. The character code displayed at the corner of one character segment is represented by the lower 8 bits, whereas the upper 8 bits indicate the display status information within the corner of one character segment. That is, what color should one character of the corner be displayed in, whether it should be blinked, etc. FIG. 3 shows another structure of display state information. If we explain the bit positions by numbers assigned from the upper digits on the left, bit 2 HL is half-brightness display;
Bits 3 and 4 designate different blink cycles, and bits 5, . . . , and 7 designate three primary colors as in FIG.

An example of one character segment angle displayed by one piece of data in FIG. 2 is shown in FIG. In FIG. 4, each character segment consists of 7 bits horizontally and 8 bits vertically, for a total of 56 dots. The code of the alphabet "A" is set in the lower 8 bits shown in FIG. 2, and display status information such as color specification is specified.
As shown in FIG. 5, the letter "A" is displayed.

The output line of the data register 133 in FIG. 1 includes a standard character pattern generation circuit 135, an extended pattern generation circuit 136, and
Pattern generation circuit 101 used in the device of the present invention
- added to 103. Standard character generation circuit 135
Then, the lower 8 bits in Figure 2 are the signal line 150.
, characters as shown in FIG. 5 are displayed, and the extended pattern generating circuit 136 generates and displays graphic pixels as shown in FIG. 6, for example. The outputs of the pattern generation circuits 135 and 136 are connected to parallel/serial conversion circuits 137 and 137A.
It becomes a serial pulse signal train and is ANDed.
Corresponding pattern data is added to the gates 138, 139, 112, . . . , 114, and whether or not to display them is controlled. these gates 13
8, 139, 112, 113, and 114 are each controlled by the output line of the decoder 134. In this example, the input to the decoder 134 is a part of the output line of the data register 133, and is the control data of the upper 4 bits in FIG. The output of the selected generating circuit will be displayed by the output line of this decoder. A plurality of pattern generation circuits 101, .
The gates 112, .

The outputs of AND gates 138 and 139 are input to R gate 140. Even if there are a plurality of pattern generation circuits for expansion, only a portion from generation circuit 136 to gate 139 is added, and all are input to this R gate 140. R gate 14
The output of 0 is for separating the color into the three primary colors.
It is input to AND gate 141. AND gate 1
41 is the separation into three primary color signal lines, and the color information R, G, B of the data register 133, that is, the second
Since the color information in the figure is 3 bits, it is composed of 3 pieces and each is input. AND gate 14
1 output is R gate 142, 143, 144
The signals are inputted into the three primary colors of red, green, and blue, respectively, and become luminance signals of the three primary colors.

The outputs of the AND gates 112, 114 are applied to the R gates 142-144, respectively. In this example, each of the pattern generation circuits 101 to 103 has three colors of red, green, and blue.
In this case, by reading out the three generating circuits 101 to 103 at the same time, each of the three primary colors and their mixture 4 are generated.
A total of seven colors can be displayed within one character corner. These pattern generation circuits 101, -, 10
In addition to 3, for example, there are two types of blink (BL) bits as shown in Figure 2 or as shown in Figure 3.
1 and BL2), or a pattern generation circuit corresponding to the specification of half brightness (HL), etc. may be further provided.

In FIG. 1, the rewriting circuit 1 of the part according to the present invention
00 is a circuit for controlling the rewriting of pixel memory data for the pattern generation circuits (pixel memories in a narrow sense) 101, 103 that are to be simultaneously read out and displayed in an overlapping manner during these displays. . This pattern generation circuit 101, ~,
103 is an input/output data line 12 from the circuit 100
3, to, 128 are simultaneously rewritten. Input data to be rewritten is given through a data line 122, and the display state such as the color to be rewritten is set in a register 111 and input to the circuit 100. And at the same time register 1
A control command for the circuit 100 set to 10 is also input to the circuit 100.

The control commands set in the register 110 are as follows: (1) The input data (pattern information on the data line 122) is transmitted to the pattern generation circuits 101, 1,
This mode writes uniquely to each pixel memory in 03, and the contents of the previous pixel memory do not remain.

(2) A mode in which only the lighting of the dot pattern that matches the display state specified by the register 111 is erased from each pixel memory.

(3) Backward writing method, that is, when writing input data (information given by data line 122), all unlit dots are written without changing the lighting dot pattern already written in each pixel memory. A mode in which only partial writing is performed.

(4) Front-write method, that is, a mode in which writing is performed so that data in each pixel memory remains in the portions of the input data (information given through the data line 122) other than the lit dots.

Make four specifications.

The meanings of these modes will be explained in more detail with reference to FIGS. 4 to 8.

In the above mode (1), a new pattern is written regardless of what was previously written in the pixel memory, and if the pattern "A" in Figure 5 is written, then any pattern in Figure 6 is written. , and replace it with the written pattern itself. This mode also uses a fourth input pattern.
As shown in the figure, if there is no pattern, it can be said to be completely erased.

Mode (2) above means erasing one part, and the pixel memories in the pattern generation circuits 101 to 103 have a pattern as shown in FIG. 7b, for example, and the display pattern 300 is blue and the display pattern 301 is green. If blue is set in the register 111 in FIG. 1 and erased in this mode, b in FIG. 7 becomes b in FIG. 6.

In the above mode (3), the writing is done backwards, as shown by a, b, and c in FIG. First, in the pixel memories of the pattern generation circuits 101 to 103, the data a shown in FIG.
In the place where the blue pattern 300 was written, write the pattern corresponding to b in FIG. 6, as shown in FIG.
The pattern shown in FIG. 6b is written as shown in FIG. 8b. That is, the pattern 301 has dots 31
It overlaps with pattern 300 at point 0, and the old pattern data is valid at this point. continue,
If the pattern in FIG. 6c is written in FIG. 8b in this mode, it becomes FIG. 8c, and the pattern 302
is not written with dots 312 and 311,
Old data patterns become valid.

The mode (4) is a front-write method, as shown by a, b, and c in FIG. First, in the pixel memory of the pattern generation circuits 101 to 103, the data shown in FIG.
The pattern shown in FIG. 6b is written in the place where the blue pattern 300 was written. the result,
The contents of the pixel memory are as shown in FIG.
This is the data. Furthermore, if the pattern shown in FIG. 6c is written in the same manner, the result will be as shown in FIG. 7c. To write pattern 302, dots 312 and 311 that overlap with the old data pattern are
is rewritten with data of a new pattern 302.

These above modes (1), (2), (3), and (4) are specified as follows.
given by setting to register 110 in FIG.
The correspondence of output information on the output line is as follows: Mode (1)...B ₁ = 0, B ₂ = 0 Mode (2)...B _{1 = 0, B 2 =} 1 Mode (3)... ...B ₁ =1, B ₂ =0 Mode (4)...B ₁ =1, B ₂ =1. This is the same as the input of B ₁ and B ₂ in FIG.

Details of the circuit 100 of FIG. 1 are shown in FIG.
~Block 600 shown in Block (i, j),
~, 603, etc., is block 50 in FIG.
Further details are shown in 0.

That is, the circuit of the basic circuit block 500 in FIG. 9 is composed of each block (l, m) arranged in a matrix in FIG. 10, where l=1, 2, . . .
..., i, m = 1, 2, ......, j. Each of them is also one of the blocks 600-603.

Furthermore, the pattern generation circuits 101, . . . , of FIG.
Each one of 103 is the same, and the details are shown in FIG.

Below, Figure 1 and its details are shown in Figures 9, 10, and 1.
The circuit will be explained using Figure 1.

FIG. 9 shows that the basic circuit block 500 is the same.
They are arranged horizontally as 501, 502, and 503.
This number is 1, ~, j, and the number of j is
This corresponds to the number of pattern generation circuits 101 to 103 in FIG. 1, and the j-th pattern generation circuit inputs and outputs data from the j-th pattern generation circuit. Each input/output corresponds to signal lines 123 to 128 in FIG.
In FIG. 10, signal lines O _j and I _j represented by signal lines 620 and 621 correspond, respectively.

In FIG. 10, the input/output data line O _j 62
0, and I _j 621 is l= of Block (l, j)
Each output line O _lj of 1, ~, i is a bundle of l=1, ~, i, and each input line I _lj is l=1, ~, i
It consists of a bundle of.

Therefore, the bundle of signal lines extending in the vertical direction in FIG. 10 corresponds to each constituent dot within one character corner. The input/output data lines bundled vertically are
This becomes an input/output data line from that one pattern generation circuit.

The line O _l (l=1, . . . i) represented by the data line O _l 620 in FIG. , 127, and I _l (l=1, ......, represented by the data line I ₁ 621)
i) is a readout signal from the pixel memory in the pattern generation circuit, and each signal line 124,
It corresponds to 126,128.

The data line 122 of FIG. 1 for externally writing to the pixel memory is the data line 624 of FIG. 10, which is a bundle of D _n (m=1, . . . , j) signal lines. Similarly, display state information written from outside to the pixel memory is set in the register 111 in FIG. 1, and its output is sent to the signal line 62 in FIG.
It is 5. The signal line 625 is connected to Cl (l=1, ~,
i) is a bundle of signal lines.

The control line indicating the mode set in the register 110 in FIG. 1 is the _B1 signal line 53 in FIG.
0, _B2 signal line 531, which enters the decoder 505 that decodes the _B1 , _B2 signals, and becomes signal lines 532, . . . , 535 indicating each mode. Signal line 53
2, ~, 535 are the aforementioned modes (1), (2), and
This becomes a signal line representing (3) and (4). The details of this circuit 505 part are shown in FIG.
AND gate 519 and inverter 520
It is made up of. In FIG. 10, the signal line 532,
. . , 535 are wired to all of the blocks (l, m), and the connections are the same as those of the basic block 500 in FIG. This wiring is omitted in FIG. 10 for clarity.

_Each signal line ₆₁₇ constituting the data line 624 in FIG. ~, j) are input to each basic block Block (l, m) as a signal line, and the details of the connection are the same as the connection of the D _j signal line 537 and the _j signal line via the inverter 524 in FIG. be.

The output of the display state information set in the register 111 in FIG. 1 is the C signal line 625 in FIG. 10, which is configured as a bundle of C _l (l=1, . . . i) signal lines. The C _l signal line becomes the C _l input line of the corresponding Block (l, m).

The entire circuit shown in FIG. 9 is as shown in blocks 500 to 503, in one row in the horizontal direction of FIG. 10, that is, Block (l, m).
This is a circuit portion in which m is fixed to an appropriate value and l is included from 1 to i. In FIG. 9, the matrix parameters (l, m) are expressed as (i, j) for convenience of illustration.

Any one of the basic circuit blocks Block (l, m)
As an explanation of the block 500 in FIG.
This will be explained by. All other blocks can be considered in the same way.

Also, the line Block (m) in Figure 10 (however,
An arbitrary line Block (j) of the blocks m=1, . . . j) will be represented by the circuit 504 in FIG. Therefore, the signal line 60 in FIG.
I _lj (l=1,......,i) of 4 is shown in Fig. 9.
Q _lj (l=1, . . . i) of the signal line 606 in FIG. 10, which is an input to the NOR gate 521, is an input to the NAND gate 523 in FIG. Output line 53
The three wires 9, . . . , 541 are the signal lines 62 in FIG.
Corresponds to 3.

Figure 9 shows the basic circuit block Block (l, j).
This is an arrangement of l=1, ~, i. Input line I _ln from the pattern generation circuit (l and m are fixed values)
is represented by the I _1j signal line 542, and the output line O _ln (l, m are fixed values) to the pattern generation circuit is represented by the O _1j signal line 543. Here, the I _1j signal line 542 becomes data read from the pixel memory of one dot within one character segment corner of one pattern generation circuit (that is, corresponding to one display state information). The same goes for the O _1j signal line 543, which becomes write data. This signal is the output of NAND gate 510, and the outputs of NAND gates 511 to 516 are input to this NAND gate 510. In addition, i=1, 2, 3...
. . . indicates the bit arrangement position of the display state (color, blink, etc.), and j=1, 2, 3, . . . indicates the bit position of the word.

In the rewriting mode (1) described above, only the NAND gate 516 is opened by the signal line 532. Therefore, the gate 516 receives a signal on the signal line 537 indicating one bit of input data from the outside, and a signal on the signal line 537 indicating one bit of input data from the outside.
The C _l signal line of the display state information corresponding to Block (l, m), that is, here, the signal C ₁ of the C ₁ signal line 536
is subjected to AND processing by an AND gate 518, and is input to a NAND gate 516 via a signal line 545, and is written into the pixel memory.

In mode (2) partial erasure, the NAND gate 515
is used by the signal on signal line 533. Other input lines of this gate 515 are the state of the dots read out from the pattern generation circuit and the output line 541 of the NAND gate 523. The signal line 541 is
This is a signal line indicating a mismatch between external input data _Dj , specified display state information _C1 , and old data as a pattern memory. AND output 545 of one C ₁ signal line 536 signal of certain display state information and one D _j signal line 537 signal of external input data, and one dot signal line 5 of input data.
After passing through the coincidence detection gate 517 with the signal of Q
The match result for this one bit is sent to the _1j signal line 544. The output of the signal line 541 is obtained by performing NAND processing on this Q _1j signal line group (m= ₁ , . In other words, the gate 515 erases only those that match, but those that do not match are written as they were before.
Partial deletion is possible.

In mode (3), the signal line 534 allows NAND
Gates 513 and 514 are used. line
The input to the NR gate 521 of Block (j) 504 is the input read data from each pixel memory, and the signal line 539
The signal becomes "0", the gate 513 is stopped, and the pattern table line 545 from the outside is prohibited.
The signal line 539 is inverted by the inverter 522, and the signal line 540 is input to the gate 514. When this is "1", the old data in the pixel memory is written again, and in the opposite case, it is prohibited and the external As pattern data is written, "backward writing" is possible.

In mode (4), the signal line 535 allows NAND
Gates 511 and 512 are used. gate 51
The signal line 545 is input to the gate 1, and if there is input data, it will be written as is.On the other hand, the gate 512 will receive the data read from the pattern generation circuit and the externally written dot signal. Signal line 53 for indicating that something is prohibited
8 signals are input. When external data is received on the signal line 538 (when a lighting instruction is received on the D _j signal line 537), old data must be erased regardless of whether the display status information matches or does not match. Signal line 538 as gate signal
is used. In this way, "front writing" is possible in which data written from outside is written on top of old data.

FIG. 11 shows the pattern generation circuit 10 of FIG.
1, ~, 103, showing details of each one, 1
All blocks 01 to 103 are the same circuit. The output code line 150 of the data register 133 of the refresh memory 130 and the pixel memory 7
A signal line 120 that sends a code specified from the outside to rewrite to 00 is connected to the data selector 7.
01 is selected and becomes the address of the memory 700. The memory 700 is a pixel memory that stores dots at the corner of one character as pattern data, and can have as many patterns as the code is given. The data read from the memory 700 is output to the parallel/serial conversion circuit shown in FIG. 1, and the data line 704 becomes the I _i input line.
It is sent out as follows. The I _i input lines are signal lines 124, 126, and 128 in FIG. memory 70
The data written to 0 is written to the circuit 100 in FIG.
The 123rd, 125th, and 127th signal lines are
It is input in the same way as the signal line 703 in the figure, is set to the register 702, and written to the memory 700. The signal line 121 is a timing signal such as set timing, and in this example, the a, b, c lines 70
There are three lines, 5, to ,707.

The timing of memory write/read in FIG. 11 is shown in a time chart in FIG. 12 and will be explained.

During the period from 820 to 821 of the waveform 805, the signal is changed from "1" to "0" at the time when the memory reading for display on the display tube ends, that is, during the horizontal retrace time and vertical retrace time. , signal line 70
5, and the address is transferred from the line 150 from the refresh memory to the address line 12 for rewriting.
Switch to 0. The signal line 706 is connected to the first
As shown in the waveform 806 in FIG. 2, the reading of the memory 700 is performed in a time zone beyond the time point 820, and at the time point 822 when it ends, the signal is set to 0, and at the time point 823, it is set to "1". By this,
The information in register 702 is set into memory 700 at point 823. The data read from point 820 is sent to signal line 704 in waveform 81.
Data is output between 0 points 824 and 825, and is logically processed by the circuit shown in FIG.
At the same time, the rewritten data input from the outside is sent to the data line 122 in a section 826 according to the data waveform 811.
and 827, and are simultaneously logically processed by the circuit of FIG. The data logically processed by the circuit in FIG. 10 returns to the data line 703, and the waveform 80
7 is set in the register 702 by the set signal line 707. This set output is established from point 829 onwards by waveform 812. The output data of this register 702 is the waveform 806 of the write control signal line 706 of the memory 700.
It is set in memory 700 at the rising point 823 of . The address of the memory 700 is changed from point 820 to point 825 to point 8 during memory read and write times for rewriting.
21 and 823 must be issued. It is sufficient that data established around point 830 of waveform 813 and established up to points 821 and 823 is output as an address.

According to this embodiment, even if a superimposed pixel memory that enables multicolor display within one character block corner is used, all related configurations can be rewritten with one rewriting operation for the superimposed memory group. The pixel memory is rewritten in a format that suits the purpose, making it easy to create image data for the display device, and having the effect of easily displaying complex pictures at high speed.

According to this embodiment, data displayed as overlapping pixels within one character corner can be erased in units of one property (for example, one color, one blink cycle dot, etc.), and the screen It has the effect of dynamically changing and displaying some of the intersecting pictures inside.

According to this embodiment, it is possible to easily add to the pixel pattern from the outside without checking the content of the already written pixel pattern or performing logical processing. There is an effect.

A modification of the present invention is the R gate 1 shown in FIG.
In addition to the 7-color display of the 3 primary colors and their combinations according to 42, -, 144, it is possible to further provide an intermediate color in addition to the 3 primary colors and increase the number of these 3 luminance signal lines,
When using a display with an expanded function such as converting the full luminance signal to N/FF at the blink timing for blinking, the number of pattern generating circuits is not limited to the three of pattern generating circuits 101 to 103, and the number of pattern generating circuits can be increased. In this case, the number is Block
The value on the l side expressed by (l, m) simply increases from l=3, and this can be considered as an extension of this example, and the same effect can be obtained.

The circuit of the basic circuit block 500 explained in FIG. 9 of the present invention has meaning in the processing itself within the block, and the combinations of gates such as AND, R, NAND, and NR are not limited to this example. Furthermore, it is also the same that the entire interior is a read-only memory that combines only the relationship between input lines and output lines.

Furthermore, although the rewrite control information is set in four modes, it can be similarly applied to modes other than the four modes.

According to the present invention, pattern data can be rewritten extremely easily.

[Brief explanation of the drawing]

1 is a block diagram of a display device showing where the device according to the invention is located; FIG. 2 is a diagram showing an example of data information read from the refresh memory and controlling the pattern generator; FIG. 3 is a diagram showing another example of the display status information in the upper digit part of FIG. Figure 6 is a diagram showing an example of displaying the alphabetic letter "A" within the corner of one character segment. Figures a, b, and c are diagrams explaining the details of the front writing mode, Figures 8 a, b, and c are diagrams explaining the details of the back writing mode, and Figure 9 is a diagram explaining the details of the display dot mode. FIG. 10 is an example circuit diagram illustrating the detailed logic for implementing the apparatus of the present invention, which shows processing of data from a pattern generation circuit provided for each display state information. FIG. 11 is a circuit diagram for explaining an example of the pattern generation circuit, and FIG.
FIG. 2 is a time chart showing the timing pulses of FIG. 11 and explaining the operation. 100...Rewriting circuit, 101-103...
Pattern generation circuit for pixel (pattern) memory, 1
30... Refresh memory, 131... Data register, 135... Standard character pattern generation circuit.

Claims (1)

[Scope of Claims] 1. A refresh memory, a pattern generator that generates a pixel pattern according to a code read from the refresh memory, and a plurality of pattern memories provided in parallel with the pattern generator. , Rewrite, which takes in rewrite control information, display status information, and rewrite data, and writes external data as is; partial erase, which erases the data when the display status information matches the pattern data in the pattern memory; and partial erase, which erases the data when the display status information matches the pattern data in the pattern memory. A rewrite circuit that updates the contents of the plurality of pattern memories by distinguishing between an endorsement that changes only pixels that are not filled with rewrite data to rewrite data and a front write that uses the original pattern data in areas where there is no rewrite data and rewrites only the areas that have rewrite data. and a display device that displays pixel patterns from the pattern generator and the plurality of pattern memories.