JPS6297420A - Input circuit - Google Patents
Input circuitInfo
- Publication number
- JPS6297420A JPS6297420A JP60238101A JP23810185A JPS6297420A JP S6297420 A JPS6297420 A JP S6297420A JP 60238101 A JP60238101 A JP 60238101A JP 23810185 A JP23810185 A JP 23810185A JP S6297420 A JPS6297420 A JP S6297420A
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- level
- input circuit
- waveform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業−１−の利用分野〕
この発明は信号源から伝送ケーブルを通して伝送される
デジタル信号を受信側で取込む入力回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry-1-] The present invention relates to an input circuit that receives, on a receiving side, a digital signal transmitted from a signal source through a transmission cable.
第５図（」、従来の、この種の入力回路の代表的なもの
を示す回路図であって、１はデジタル信号例えばデジタ
ル映像信号を伝送する伝送ケーブル、２．３は受信装置
例えばディスプレイモニタＡの入力端イ、４は終端抵抗
、５は増幅器（ＴＴＬｌ路）、６はアースである。FIG. 5 is a circuit diagram showing a typical conventional input circuit of this type, in which 1 is a transmission cable for transmitting a digital signal, such as a digital video signal, and 2.3 is a receiving device, such as a display monitor. Input terminal A of A, 4 is a termination resistor, 5 is an amplifier (TTL1 path), and 6 is a ground.
この構成においては、図示しない送信側信号源から伝送
ケーブル１を１ｍして伝送され、入力端子２．３に入力
されたデジタル映像信号により終端抵抗４の両端に電圧
降下を発生する。終端抵抗４の片側はアース電位にある
ので、該アース電位から見た入力端子２の電位が増幅器
５の入力電位となる。In this configuration, a voltage drop is generated across the terminating resistor 4 by a digital video signal transmitted from a transmission side signal source (not shown) through the transmission cable 1 for 1 m and inputted to the input terminal 2.3. Since one side of the terminating resistor 4 is at ground potential, the potential of the input terminal 2 viewed from the ground potential becomes the input potential of the amplifier 5.
送信側から送ν）出されるデジタル映像信号の波形が第
６図＋ａｌに示すような波形である場合、終端抵抗４の
両端に現れる入力波形が同じ波形であることが理想的で
あるが、実際には、伝送う一−プル１の品質や長さ等に
より、例えば、第６図（ｈｌに示すような歪波形となる
ので、増幅器５の出力はそのスレッショルドレベルを０
とすると同図（Ｃ））に示すように、上記第６図ｔａ＋
の原信号と異なるデー−７、−テイ比のデジタル映像信
号となり）、デイスプし・イモニタ１゛の画像が、原信
号が持つ画像情報に対して不正確になるという問題があ
った。If the waveform of the digital video signal sent from the transmitting side is as shown in Figure 6+al, ideally the input waveforms appearing at both ends of the terminating resistor 4 should be the same waveform, but in reality In this case, depending on the quality and length of the transmission pull 1, for example, a distorted waveform as shown in FIG.
Then, as shown in the same figure (C)), the above figure 6 ta+
(This results in a digital video signal with a data ratio different from that of the original signal.) This causes a problem in that the image on the display monitor 1 becomes inaccurate with respect to the image information contained in the original signal.
この発明は１−記した問題を解消するためになされたも
ので、原信号のデユーティ比を忠実に再現することが可
能で、従来に比し、送受信側間での情報伝達の確度を高
めることができる入力回路を得ることを目的とする。This invention was made to solve the problem described in 1. It is possible to faithfully reproduce the duty ratio of the original signal, and it improves the accuracy of information transmission between the transmitting and receiving sides compared to the conventional method. The purpose is to obtain an input circuit that can perform
〔問題を解決するための手段〕
この発明は−１−記ｌ」的を達成するため、入力信号の
直流レベルをシフトする回路を設けたものである。[Means for Solving the Problem] In order to achieve the object described in item 1-1, the present invention is provided with a circuit that shifts the DC level of an input signal.
この発明では、入力信号の直流レベルが調節されるので
、ｉｔ！ｉｔ節の度合を適切にすることにより、増幅器
のスレッショルドｌノヘルを相対的に変化させることが
できるため、原信号のデユーティ比をほぼ忠実に再現す
ることが可能となる。In this invention, since the DC level of the input signal is adjusted, it! By optimizing the degree of the it clause, the threshold value of the amplifier can be relatively changed, making it possible to almost faithfully reproduce the duty ratio of the original signal.
第１図はこの発明の一実施例を示したものであり、終端
抵抗４とアース６との間に直流電圧源７を挿入している
点において、第５図の従来の場合と相違する。FIG. 1 shows an embodiment of the present invention, which differs from the conventional case shown in FIG. 5 in that a DC voltage source 7 is inserted between a terminating resistor 4 and a ground 6.
この構成においては、終端抵抗４の片側は直流電圧源７
が与える直流レベルにあるので、今、該直流レベルをｅ
とすると、増幅器５の入力波形は第４図（ｂｌに〉１（
すように直流レベルがｅだげシフトされた波形となる。In this configuration, one side of the terminating resistor 4 is connected to the DC voltage source 7.
Since the DC level is at the DC level given by
Then, the input waveform of the amplifier 5 is as shown in FIG.
The waveform is such that the DC level is shifted by e.
従って、増幅器５の出力は同図（Ｃ）に示すようになり
、原信号に近いデユーティ比を持つ信号となる。Therefore, the output of the amplifier 5 becomes as shown in FIG. 5C, which is a signal having a duty ratio close to that of the original signal.
従って、本実施例によれば、原信号が持つ情報を正確に
画像表示することができ、また、画像の質を調整するこ
ともできる。Therefore, according to this embodiment, the information contained in the original signal can be accurately displayed as an image, and the quality of the image can also be adjusted.
上記実施例では、入力波形の直流レベルをシフトするた
めの回路として直流電圧源７を用いているが、第２図に
示すように、終端抵抗４とアース６との間に抵抗８を挿
入し該抵抗８に定電流源９から電流を流すことようにし
ても良く、また、第３図に示すように、増幅器５のアー
ス端子ＧＮＤをダイオード１０を介して接地することに
より等測的に電圧を発生させるようにしても良く、同様
の効果を得ることができる。In the above embodiment, the DC voltage source 7 is used as a circuit for shifting the DC level of the input waveform, but as shown in FIG. 2, a resistor 8 is inserted between the terminating resistor 4 and the ground 6. A current may be caused to flow through the resistor 8 from a constant current source 9, and as shown in FIG. It is also possible to generate the same effect, and the same effect can be obtained.
この発明は以１−説明した１ｆｆｌＦ）、入力波形に歪
が生じていても、原信号のデユーティ比を忠実に１）現
することができるので、原信号が持つ情報を正確に受信
することができる。This invention can faithfully represent the duty ratio of the original signal even if the input waveform is distorted, so that the information contained in the original signal can be accurately received. can.
第１図〜第３図はこの発明の実施例を示す回路図、第４
図は−１−記実施例の効果を説明するための波形図、第
５図は従来の入力回路を示す回路図、第６図は−１−記
従来例における各部波形図である。
図において、１ 伝送う゛−プル、２．３−入力端子、
４−終端抵抗、５−増幅器、７ 直流電圧源、８−抵抗
、９一定電流源、１０ ダイオード。
なお、図中、同一符号は同一・または相当部分を示す。Figures 1 to 3 are circuit diagrams showing embodiments of the present invention;
5 is a circuit diagram showing a conventional input circuit, and FIG. 6 is a waveform diagram of various parts in the conventional example described in -1-. In the figure, 1 transmission loop, 2.3 input terminal,
4 - terminating resistor, 5 - amplifier, 7 - DC voltage source, 8 - resistor, 9 constant current source, 10 diode. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (4)
信装置の正負入力端子、該両入力端子間にある終端抵抗
を通して信号が導かれる増幅器を有する入力回路におい
て、直流レベルシフト回路を有することを特徴とする入
力回路。(1) An input circuit having positive and negative input terminals of a receiving device that receives digital signals through a transmission cable, and an amplifier through which the signal is guided through a terminating resistor located between the two input terminals, is characterized by having a DC level shift circuit. input circuit.
挿入された直流電圧源であることを特徴とする特許請求
の範囲第１項記載の入力回路。(2) The input circuit according to claim 1, wherein the DC level shift circuit is a DC voltage source inserted between a terminating resistor and ground.
挿入された抵抗と、両者の接続点に接続された定電流源
であることを特徴とする特許請求の範囲第１項記載の入
力回路。(3) The input circuit according to claim 1, wherein the DC level shift circuit is a resistor inserted between a terminating resistor and ground, and a constant current source connected to a connection point between the two. .
アースとの間に挿入されたダイオードであることを特徴
とする特許請求の範囲第１項 記載の入力回路。(4) The input circuit according to claim 1, wherein the DC level shift circuit is a diode inserted between the earth terminal of the amplifier and the earth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60238101A JPS6297420A (en) | 1985-10-22 | 1985-10-22 | Input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60238101A JPS6297420A (en) | 1985-10-22 | 1985-10-22 | Input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6297420A true JPS6297420A (en) | 1987-05-06 |
Family
ID=17025187
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60238101A Pending JPS6297420A (en) | 1985-10-22 | 1985-10-22 | Input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6297420A (en) |
-
1985
- 1985-10-22 JP JP60238101A patent/JPS6297420A/en active Pending
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