JPS629682Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Background of the Invention This invention relates generally to solenoid control systems and to tip detection devices used therein. More specifically, the invention provides that the solenoid energization period is dependent on the amount of work imposed on it such that the solenoid is always turned off or the current is reduced as soon as the solenoid armature or plunger is positioned. Regarding solenoid control systems that are functions.

The prior art is replete with examples of electromechanical systems and solenoid control systems using electric solenoids. Many printer systems use solenoid-actuated print hammers, record card feeders use solenoid-actuated grippers, and card or check sorters use solenoid-actuated pocket gates. Many prior art solenoid control systems deenergized the solenoid in one or more of the following ways. Most prior art systems operate to turn off the solenoid at a fixed amount of time after the solenoid is first turned on. Other types of systems use mechanical feedback, such as a relatively mildly responsive mechanical switch that senses when a solenoid is positioned and operates to de-energize the coil. Still other systems use photographic optics or the like to detect the current position of a solenoid plunger so that its coil is deenergized when the plunger reaches a predetermined physical position. Some prior art systems use comparison means to determine when a predetermined threshold level of current is reached after the solenoid is positioned to de-energize the solenoid coil.

All of the prior art systems described above suffer from one or more of the following disadvantages. None of these systems turn off the solenoid at the substantially precise time that the solenoid is positioned, resulting in wasted energy as the solenoid continues to be driven after the plunger or armature has positioned. This greatly increases the power requirements of the system and creates a possible occurrence of overheating that can damage the solenoid coil or associated circuitry. Furthermore, the heat generated after the plunger is positioned reduces the effectiveness of the solenoid, in addition to wasting energy and possibly harming the coil or by increasing its resistance. Yet another disadvantage of many of the prior art systems is that the precise position of the solenoid plunger varies with respect to turn-off time, thereby making it difficult to control the damping of the solenoid to achieve repeatable damping characteristics. This results in the fact that it is extremely difficult. The problem of energy waste is particularly important when power requirements are critical.

SUMMARY OF THE INVENTION The purpose of the invention is to provide a solenoid control system for minimizing power consumption and minimizing heat generated within the solenoid.

Yet another object of the invention is to provide a solenoid control system in which the solenoid activation period is a function of the amount of work imposed on it.

Still other objects of this invention are that the solenoid is designed to reduce the power requirements of the plunger, to reduce the power requirements of the system, to reduce the heat generated and damage resulting therefrom, and to allow for controlled damping. The present invention provides a solenoid control system that is deenergized in the energized position.

Yet another object of this invention is to provide a solenoid control system with improved repeatable damping characteristics and better dropout characteristics in faster times.

Yet another object of this invention is to provide a solenoid control for use in battery-actuated solenoid-based systems that provides maximum permanence of battery energy by assuring the earliest possible turn-off time of the solenoid after the desired work has been accomplished. The goal is to provide a system.

Yet another object of the invention is to provide a tip detection circuit that detects sudden changes or fluctuations in current flowing through a solenoid coil resulting from sudden changes in reluctance.

Yet another object of the invention is to provide a tip detection device that monitors a current flowing through a resistor connected in series with a solenoid coil to generate a tip indicating pulse at that point in the current waveform at which a solenoid plunger or armature is positioned. It is to be.

Yet another object of this invention is to provide a solenoid control system using a tip sensing device to detect the point at which a solenoid plunger or armature is positioned and to control the turn-off time of the solenoid and within a predetermined time period. In response to a solenoid plunger not being positioned, the solenoid coil is deenergized to prevent damage to the system.

These and other objects of the invention are accomplished in a solenoid control system that normally deenergizes the solenoid coil at that point in time when the solenoid plunger is positioned. The tip detection circuit monitors the current flowing through a sensing resistor that is connected in series with the solenoid coil and senses changes in the current established in the coil as the reluctance of the coil changes. As soon as the solenoid armature or plunger is positioned and the reluctance no longer changes, the tip detection circuit generates a pulse and the solenoid control logic turns off the current to the solenoid coil in response to the tip indication pulse. If the solenoid control logic does not reach the tip indication pulse within a predetermined time period, the solenoid control logic deenergizes the solenoid coil to prevent damage to the system.

DETAILED DESCRIPTION OF THE INVENTION A typical solenoid drive circuit and therefore characteristic current waveforms are shown in FIGS. 1 and 2.
In Figure 1, solenoid 11 is +24 volts
It has one end connected to a DC power supply potential and the other end connected to a switching transistor 13 via a series sensing resistor 15. When the external control circuit applies a signal to the base of transistor 13 and causes it to switch to a conductive state, a series current path passes through solenoid 11, series sense resistor 15, and transistor 13 from the +24 volt power supply to ground. Connection point 12 connects current sensing resistor 15 and transistor 13
The connection point is connected to the anode of diode 14, the cathode of diode 14 being coupled to the end of solenoid 11 which is connected to the +24 volt power supply. Connection point 12 is also connected to the collector of a second switching transistor 16 via a holding current establishing resistor 18. Once transistor 13 has been switched to a non-conducting state, the transistor is switched to a conducting state when transistor 13 is so switched and operates to establish a level of holding current. After switching transistor 13 is switched to a non-conducting state, diode 14 is added to form a current loop through the solenoid and sensing resistor. A voltmeter 17 is connected in parallel to the sensing resistor 15 so that the voltage is measured over time.

FIG. 2 represents a current versus time curve, where the current is calculated from the equation I=V/R. Assuming that transistor 13 is switched into conduction at time t ₀ , the current flowing through the coil of solenoid coil 11 is established and can be measured by measuring the voltage across known sensing resistor 15 . With any inductor, the coil of solenoid 11 attempts to counteract changes in the current flowing through it. During a period of time _t1 , the current is sufficient so that the solenoid plunger or armature is introduced into the coil. As the solenoid armature or plunger is introduced into the coil, current continues to be established but the reluctance changes. At some time t ₂ , the reluctance is changing faster than the current is establishing so that the current waveform of FIG. 2 reflects a drop in the level of current flowing through the solenoid coil and sensing resistor 15. ing. At time _t3 , the solenoid armature or plunger is positioned such that the reluctance no longer changes and the current is freely established in the coil again. This point at which the reluctance stops changing appears to be the peak of the current waveform in FIG. 2 and occurs at time _t3 . The current is equal to the time t ₃ and
continues to be established within the coil as shown by the portion of the waveform between t _{and 4} . At time _t4 , a threshold level of current is detected by some means known in the art and switching transistor 13 is switched to a non-conducting state. However, a current loop is established between solenoid coil 11, sensing resistor 15 and diode 14.
The current decays in the coil between times t ₄ and t ₅ .
At time t ₅ , a holding current level established by the conduction state of switching transistor 16 and the magnitude of holding current establishing resistor 18 is reached and this level of holding current is
6 is maintained until it is switched to a non-conducting state.

It can be seen that after time _t3 , current continues to be established in the coil although no useful work is being done as the solenoid plunger or armature is already well positioned. This increased current generates unwanted and unwanted heat that reduces the efficiency of the solenoid or causes damage to the solenoid coil and associated circuitry.

A rapid current fluctuation or "peak" appears at time t ₃ and the peak of this current waveform substantially represents the exact time at which the solenoid plansha or armature is positioned and the reluctance of the system no longer changes. This can be seen from studying the characteristic current waveform shown in FIG. Depending on various parameters of the circuit involved and the amount of work applied to the solenoid plunger or armature, the point in time at which this tip occurs will vary. The purpose of this invention is to fix the turn-off time with respect to this tip representing a plunger or armature positioned to retain energy, reduce power requirements, avoid overheating and extend the life of the system. .

FIG. 3 shows a block diagram of the solenoid control system of this invention. The solenoid 19 is connected to a +24 volt power supply DC potential and is driven by a solenoid drive circuit 21 which is connected to the solenoid 19 via a lead 23. Solenoid drive circuit 21 is controlled by solenoid drive control logic of block 25 which is connected to solenoid drive circuit 21 via lead 27. The solenoid drive control logic circuit of block 25 is connected to lead wire 2.
A solenoid energization signal is received from some external power source via 9, which signal indicates the need to energize solenoid 19. Solenoid drive control logic 25 is responsive to external pulses and solenoid drive circuit 21
energizes the solenoid 19. Solenoid 19
When the solenoid plunger or armature is positioned as indicated by the occurrence of a peak in the current waveform passing through the solenoid coil,
The tip detector of block 31 senses the current flowing through solenoid coil 19 via lead 33 and provides an output pulse across lead 35 to the solenoid drive control logic of block 25. Upon receiving this cusp indicator pulse, the solenoid drive control logic of block 25 turns off the solenoid drive circuit of block 21, deenergizing the solenoid. If this cusp indicator pulse is not received by the solenoid drive control logic of block 25 for a predetermined period of time, the solenoid drive control logic of block 25 turns off the solenoid drive circuit of block 21 to 19 thereby protecting the circuit.

FIG. 4 shows a schematic diagram of the solenoid control system of FIG. 3, in which each numbered block is shown correspondingly numbered to the dotted line block of the circuit of FIG. The solenoid drive circuit of block 21 receives its input from the solenoid drive control logic of block 25 via lead 27. Lead wire 27 is connected to the input of inverter 37, and the output of inverter 37 is connected to connection point 3.
Connected to 9. Connection point 39 is connected to the +5 volt supply through resistor 41 and connected to diode 45.
The anode of the diode 45 is connected to the connection point 39 and the cathode is connected to the connection point 43. Connection point 43 is resistor 4
7 to ground and further connected to the base of transistor 49. transistor 49
The emitter of is connected directly to the base of transistor 51 and to ground through resistor 50.
The collector of transistor 49 is connected to the collector of transistor 51 at node 53. Connection point 5
3 is coupled via lead 23 to the solenoid of block 19, and the emitter of transistor 51 is connected via lead 33 to the input of the tip detection circuit of block 31. The solenoid of block 19 has one end coupled to input lead 23;
It includes a solenoid coil 55 having its other end coupled to a +24 volt power supply potential. Block 19 is further shown to include a diode 57 connected in parallel to a solenoid coil 55 having its anode connected to input lead 23 and its cathode connected to the +24 volt power supply.

The tip detection circuit of block 31 is connected to input terminal 59.
The input is received from the lead wire 33. Input connection point 59 connects to reference connection point 6 via current sensing resistor 63.
1. The reference connection point 61 connects the solenoid coil 55, the lead wire 23, the connection point 53, and the transistors 51 and 4 when the transistor switch consisting of the transistors 49 and 51 is conductive.
9, lead wire 33, connection point 59, current sensing resistor 6
3. +24 via connection point 61 and lead wire 65
It is coupled directly to ground via lead 65 such that a series current path is established from the volt supply to ground. Current sensing resistor 63 is therefore inserted into a series current path which is used to energize the solenoid coil such that the current flowing through resistor 63 represents the current flowing through solenoid coil 55. The peak detection circuit of block 31 further includes a differential voltage comparator 67 having a pair of inputs. A first comparator input is taken from node 69 which is coupled to input node 59 via a first comparator input resistor 71 . First comparator input node 69 is also coupled to reference node 61 via first comparator input capacitor 73 . The combination of first input resistor 71 and first input capacitor 73 is connected in parallel to current sensing resistor 63 and has a first characteristic RC time constant. Comparator 6
The second input to 7 is taken from a second comparator input connection 75, which connection 75 connects the second comparator input resistor 7.
7 to input node 59 and via a second comparator input capacitor 79 to reference node 61
connected to. The second input capacitor provides some noise rejection but can be removed under certain conditions. A second input resistor 77 and a second input capacitor 79 are connected in parallel with the current sensing resistor 63 and have a second characteristic RC time constant that is different from the RC time constant of the first input resistor 71 and first input capacitor 73. First input resistance-capacitor coupling 71, 7
3 forms a ratio with the second input resistor-capacitor coupling 77, 79, such that the current in the solenoid coil 55 and the sensing resistor 63 is
9 and 75 in response to changes in the voltage drop across current sensing resistor 63. Capacitors 73, 79 and/or
Alternatively, the values of resistors 71, 77 can be varied to obtain variable degrees of accuracy over different ranges of operation, as is known in the art.

The negative power input of comparator 67 is connected to reference node 61 via leads 81 and 83, respectively. The positive power input of comparator 67 is connected to lead 8.
7 and through an offset establishing resistor 89 to connection point 85, respectively. Connection point 85 is connected to a +5 volt DC power source. The output of comparator 67 is taken from output node 91. Output connection point 91 is connected to connection point 85 via resistor 93,
Connected via lead 35 to the input of the solenoid drive control logic of block 25 and connected to lead 9.
7 to positive feedback network connection point 95. A positive feedback network is connected between the feedback node 95 and the first comparator input node 69 and consists of a relatively large size feedback resistor 99 and a parallel connection of a feedback capacitor 101. The feedback network provides hysteresis and reduces the susceptibility of the system to noise.

The solenoid drive control logic of block 25 has three inputs and one output. First input 103
receives set and positive reset pulses from an external system indicating the need to energize solenoid 19. This input is connected to input connection point 105, which connects via lead wire 109.
connected to the "J" input of JK flip-flop 107 and connected to inverter 111 and lead wire 113.
to the "K" input of JK flip-flop 107. A second input to the solenoid drive control logic of block 25 is taken from input 115;
This input 115 receives continuous clock pulses from a clock pulse source, such as a 250KC master clock, not shown but well known in the art. These clock pulses are input 11
5 through lead 117 to the clock input of JK flip-flop 107 and through clock input lead 121 to the clock input of second JK flip-flop 119. JK
The “Q” output of flip-flop 107 is connected to connection point 1.
JK flip-flop 119 taken from 23
connected directly to the “J” input of the The ``'' output of JK flip-flop 107 is taken from node 125 and applied directly to the ``K'' input of JK flip-flop 119. Node 123 is also connected to one input of a NAND gate 129 via a lead 127, and node 125 is connected to one input of a second NAND gate 133 via a lead 131. "Q" of JK flip-flop 119
Output is sent to NAND gate 13 via lead wire 135
3 and the output of JK flip-flop 119 is connected to the second input of JK flip-flop 119 via lead 137.
Connected to the second input of NAND gate 129.
The output of NAND gate 129 is connected via lead 141 to the "dominant clear" input of master/slave JK flip-flop 139 and NAND gate 133
The output of is connected via lead 143 to the "dominant clear" input of master/slave JK flip-flop 139. The "J" input of master/slave JK flip-flop 139 is connected directly via lead 145 and the "K" input of master/slave JK flip-flop 139 is connected via lead 147 to the +5 volt power supply.

The third or clock input of master/slave JK flip-flop 139 is taken from the output of the tip detection circuit of block 31 via lead 35 and is
The "" output of the slave JK flip-flop is used as the only output of the solenoid drive control logic of the present invention and is connected via lead 27 to the input of the solenoid drive circuit of block 21.

FIG. 5 shows a timing diagram useful in explaining the operation of the circuit of FIG. The various pulse trains or lines in the timing diagram of FIG. 5 are labeled A through L. Line A shows the pulse train of clock pulses as applied to input 115 of the solenoid control logic of block 25. The pulse on line B represents a forward going "set" pulse which is applied to input 103 from some external source to indicate that solenoid 19 should be energized. Line C is
Line D represents the "Q" output of JK flip-flop 107 and line D represents the "Q" output of JK flip-flop 119. The negative going pulse of line E is
The negative going pulse on line F represents the output of NAND gate 129 and the negative going pulse on line F represents the output of NAND gate 133. The pulses on line G are used in case no tip is detected or for one reason or another.
For two reasons, the tip indication pulse is
5 via the solenoid control logic of block 25.
represents the output of the JK flip-flop 139.

Line H of the timing diagram of FIG. 5 shows the waveform of current flowing through sense resistor 63 when lead 35 is disconnected from the solenoid control logic of block 25.
A tip indicating pulse from the output of comparator 67 is not received within a predetermined time period (the time between the pulses of lines E and F), and solenoid coil 55 is turned off only at the end of that predetermined time period. Forced. The waveform of line I shows that lead wire 35 is connected to block 2.
output connection point 91 of the tip detection device when disconnected from the solenoid control logic of 5 so that the tip indication pulse is not used to de-energize the solenoid.
represents the output that appears in The waveform on line J represents the pulse train seen at the clock input of master/slave JK flip-flop 139 when lead 35 is connected to the third or clock input of the flip-flop and is provided with a peak indication pulse from the output of comparator 67. represent. The second time that the waveform of line J goes negative and then goes sharply positive is for the purpose of showing that it goes negative and then goes sharply positive rather than continuing as a straight positive pulse. This is somewhat exaggerated, but in reality this occurs over a very short period of time and is not normally observed. The pulses on line K are the master/slave JK flip-flop 13 of the solenoid control logic of this invention.
9 represents the signal seen at the ``'' output of 9, in which the cusp indicator pulse is received via lead 35 for a predetermined period of time, and the waveform in line L is a sensing resistor for the case where: 63, in which case the tip indicator pulse is applied via lead 35 to the solenoid control logic of block 25 and turns off the solenoid drive circuit 21 and turns off the solenoid coil 55 of block 19. It is used to negate the

FIG. 6 represents an alternative embodiment of the tip detection device of the present invention. The configuration of the comparator and the ratio establishing inputs are therefore substantially as shown in FIG. 4 and the output is modified to eliminate and replace the feedback network consisting of feedback resistor 99 and feedback capacitor 101. Replace the following circuit with The output of comparator 67 is taken from node 149. It is coupled to node 85 through resistor 93 at node 149 and to ground through capacitor 153. Connection point 149 is also connected to the input of a Schmitt trigger device 155, which may be, for example, an MC1489 package known in the prior art and which provides the necessary noise rejection and hysteresis in place of the feedback network of FIG. It is used to give Schmidt trigger device 15
The output of 5 is connected to inverter 1 via lead wire 159.
57 and the output of the inverter 157 is applied to the block 25 via the lead wire 35 as described above.
to the solenoid control logic.

The operation of the solenoid control system of FIG. 4 will now be described with reference to the timing diagrams A-L of FIG. 5 discussed above.

When an external circuit or system generates a positive going pulse B to indicate the need to energize solenoid coil 55 of block 19, the positive pulse B is applied to input 103 to trigger the negative going pulse of the next master clock pulse A. Used to predominately set JK flip-flop 107 in green. When JK flip-flop 107 is set, its "Q" output C goes high. This high is applied to the “J” input of JK flip-flop 119 and is also applied to NAND gate 12 via lead 127.
9 is given to one input. NAND gate 129
Since the other input of JK flip-flop 119 is connected to the ``'' output of JK flip-flop 119, and this ``'' output still remains high until JK flip-flop 119 is set by the next clock pulse (JK flip-flop 119 ``Q'' ”
(see output D), both inputs of NAND gate 129 momentarily go high, and a low appears at the output of gate 129 for one clock pulse time, as shown in FIG. 5E. This low is transferred via lead 141 to the "dominant set" of master/slave JK flip-flop 139, thereby setting flip-flop 139 to the dominant set. The duration of this "dominant set" pulse is sufficient to ensure that flip-flop 139 is not reset by the pulse on lead 35 that occurs when the coil is energized. When flip-flop 139 is set, its output F goes low. This low pulse is applied to the input of the inverter 37 via the lead wire 27. Inverter 37 inverts this low input to produce a high at its output, which enables the base of transistor 49 to go high, causing transistor 49 to conduct. When transistor 49 conducts, transistor 51 is switched conductive to provide +24 volts DC.
From the power supply, solenoid coil 55, transistor 4
A current path is formed through 9 and 51 and sensing resistor 63 to ground.

Once a current is established in solenoid coil 55, the current H flowing through sense resistor 63 is monitored by the comparator circuit of block 31 as follows.
That is, before solenoid drive circuit 21 is energized to drive solenoid 19, comparator 67 is biased through offset resistor 89 so that its output J is high. When the solenoid 19 is energized and current begins to flow through the sensing resistor 63, the change in the current H flowing through the sensing resistor 63 is:
It is monitored by the ratio of resistor 71 and capacitor 73 to resistor 77 and capacitor 79. resistance 7
The combination of 1 and capacitor 73 has a different RC time constant than the combination of resistor 77 and capacitor 79. Therefore, the input connection point 69 of the comparator 67
Although the potentials of and 75 both follow the voltage drop of the sensing resistor 63 with a time delay, they are not the same due to the difference in time constant. The ratio thus establishes a differential voltage between input nodes 69 and 75 of comparator 67. As a result, the current flows through the sensing resistor 63
As soon as J starts flowing, the output J at node 91 goes low due to the ratio establishing circuitry at the input of comparator 67. The current flowing through the solenoid coil 55 continues to be established until the solenoid plunger is retracted by the solenoid coil. When the plunger is retracted and the air gap is reduced,
The current begins to drop due to the change in reluctance. This is because reluctance changes faster than the rate at which current is established in the coil.
At the moment when the current H flowing through the sensing resistor 63 starts to drop, a change in reluctance is displayed, and the comparator 67
's input ratio circuitry senses the change. In other words, due to the difference in time constant, the input connection points 69 and 75
The potential of is reversed, which causes the output J of comparator 67 to go high. As soon as the solenoid plunger is positioned, the reluctance no longer changes and the current flowing through the sensing resistor 63 begins to be established again and the tip appears as shown in FIG. 5H.
When the sense resistor current begins to increase, the input ratioing network causes the output J of comparator 67 to go low again. In this manner, a cusp indicator pulse as shown in FIG. 5J is generated and applied via lead 35 to the clock input of master/slave JK flip-flop 139. +5 volt power supply lead 14
7 to the "K" input, the signal at the clock input resets the flip-flop 139. With this, JK flip-flop 1
39's "" output K becomes high, and this high "" output is sent to the inverter 3 via the lead wire 27.
7 is inverted and a low signal is provided to the base of transistor 49. As a result, switching transistors 49 and 51 are deenergized, a current path is opened, and solenoid coil 55 is deenergized. As soon as transistors 49 and 51 are turned off, current in sensing resistor 63 ceases to flow. Therefore, the current in the sensing resistor 63 actually becomes as shown in FIG. 5L. When the current of the sensing resistor 63 stops flowing, the ratio of the comparator 67 is established RC.
The network again causes the output J of node 91 to go high.

Therefore, the turn-off time of the solenoid is
It is fixed at a predetermined time after the occurrence of the tip. The onset of the tip means that the solenoid plunger is positioned and the change in reluctance ends, and this will be observed in the current waveform H.

If the tip is not detected by the tip detector 31 (which occurs when a solenoid plunger or armature is plugged in, etc.), then
The solenoid control system of FIG. 4 operates as follows. That is, the trailing edge of the "SET" pulse of FIG. 5B resets the JK flip-flop 107 (FIG. 5C), which in turn causes the JK
Flip-flop 119 is reset (fifth
Figure D). Just before JK flip-flop 119 is reset, both inputs of NAND gate 133 go high, causing a low to appear at the output of NAND gate 133, as shown in FIG. 5F. This row is connected to the main/slave via lead wire 143.
Awarded for "superior clear" of JK flip-flop 139. This pulse resets the JK flip-flop 139 and a high appears at the "" output as shown in FIG. 5G. This high is transferred via lead 27 to inverter 37 of the solenoid drive circuit of block 21, which switches transistors 49 and 51 to a non-conducting state, thereby deenergizing solenoid 19. In this way, the current in coil 55 is prevented from increasing continuously. If the current continues to increase after the plunger is positioned, it wastes energy and generates harmful heat that burns out the coil or damages associated circuitry.

The tip detector of block 31 uses a feedback network consisting of a parallel combination of feedback resistor 99 and feedback capacitor 101. This positive feedback network locks the comparator to its current state, thereby providing a hysteresis effect and reducing the susceptibility of the system to noise. If the system were to oscillate freely or become susceptible to noise, the circuitry would be unusable for the resulting unreliable output. In an alternative embodiment of the tip detector shown in FIG. 6, the feedback capacitor and feedback resistor are eliminated, but the Schmitt trigger device 1
55 is added to provide the necessary hysteresis effect and the necessary noise rejection.

Under normal operation, the circuit of FIG.
3 is operative to initiate energization of solenoid coil 55 in response to the presence of a "SET" pulse at 3. A solenoid coil overcurrent is established and a tip appears in the current waveform at the time the solenoid plunger is positioned. The tip detector of block 31, and more particularly comparator 67,
monitors the current flowing through sense resistor 63 and senses alternating voltages at inputs 69 and 75 as commanded by the RC input ratio establishing circuitry, and thereby the output of the tip detector is connected to the solenoid. A pulse is generated when the plunger is positioned and the tip is raised. This signal causes block 25
The solenoid control logic generates a signal which causes transistors 49 and 51 to switch to a non-conducting state and de-energize the solenoid coil. If the tip is not detected, JK flip-flop 139
When there is no leading indicator pulse arriving on lead 135 to the clock input of the NAND gate 133, but at the end of a predetermined period of time, which is determined by the duration of the set pulse appearing at input 103, NAND gate 133 outputs a negative going pulse. resets the master/slave JK flip-flop, thereby causing transistors 49 and 51 to be switched to a non-conducting state, thereby deenergizing the solenoid coil, thereby minimizing excessive heat generation, and disabling the solenoid coil. and protect related circuits.

Table 1 below shows typical component values used in a typical embodiment of the invention. These values are representative only and in no way constitute a limitation of this invention.

Table 1 Component value or name comparator 67 LM311 Schmitt device 155 MC1489 NAND gate 129 & 133 DTL946 Inverter 37 DTL944 Inverter 111 & 157 DTL936 Coil 55 3.4Ω resistor 41 270Ω resistor 47 1000Ω resistor 50 51Ω resistor 63 0.10Ω resistance 71, 77 & 92 2000Ω resistance 89 10000Ω resistance 99 2×10 ⁶ Ω Capacitor 73 & 153 0.1 μF Capacitor 79 0.012 μF Capacitor 101 0.005 μF Although a specific device has been shown for the purpose of describing Applicant's invention, other variations and modifications in the specific structure shown may be made in the supra. It will be clear that nothing can be done without departing from the spirit and scope of the invention, which is limited only by the claims of the utility model registration.

[Brief explanation of the drawing]

FIG. 1 shows a schematic diagram of a solenoid energizing circuit having a voltmeter connected in parallel with a resistor in series with the solenoid coil. FIG. 2 represents the current versus time curve for a typical solenoid energization and deactivation cycle. FIG. 3 shows a block diagram of the solenoid control system of this invention. Figure 4 shows a schematic diagram of the solenoid control system of this invention.
The details of the tip detection circuit and solenoid control logic of this invention are also shown. FIG. 5 shows a timing diagram referred to in explaining the operation of the circuit of FIG. 4. FIG. 6 shows a circuit diagram of an alternative embodiment of the tip detector of block 31 of FIG. In the figure, 11, 19 are solenoids, 13,
16 is a switching transistor, 15 and 18 are resistors, 21 is a solenoid drive circuit, 25 is a solenoid drive control logic circuit, 31 is a tip detection device, 6
7 is a comparator, 71 and 77 are input resistors, 73 and 79
is the input capacitor, 107 and 119 are the JK flip-flops, 139 is the main/slave flip-flop,
49 and 51 indicate switching transistors.

Claims (1)

[Claims for Utility Model Registration] (1) A solenoid control system that energizes a solenoid in response to a signal representing an external need and deenergizes the solenoid when the solenoid armature reaches a predetermined position. means for establishing a current path from a power source through the solenoid to ground, the current path establishing means including bistable switching means for opening and closing the current path, and further comprising: detection means for detecting when the solenoid armature reaches the predetermined position in response to an overflow current and generating a control signal in response, the detection means having first and second inputs; a differential voltage comparator coupled in parallel to the current sensing resistor and having a comparison output;
a first resistor-capacitor means having an RC time constant of; and a second resistor-capacitor means coupled in parallel to the current sensing resistor and having a second RC time constant different from the first RC time constant. means for coupling said first and second resistor-capacitor means to first and second inputs of said comparator, respectively, to establish a differential voltage ratio between said inputs; and an output of said comparator. a control means connected to the circuit for eliminating noise and preventing oscillations, wherein the current flowing through the current sensing resistor undergoes a characteristic variation when the solenoid armature reaches the predetermined position; the comparator thus detects the characteristic current fluctuation and outputs the control signal in response;
further comprising logic control means for triggering said bistable switching means into a first state in response to said signal representative of an external need and triggering said bistable switching means into a second state in response to said control signal; A solenoid control system comprising: in the first state the current path is closed to energize the solenoid and in the second state the current path is open to fire the solenoid. (2) The solenoid control system according to claim 1, wherein the current path establishing means includes a current sensing resistor, and the bistable switching means includes a transistor switch. (3) said logic control means includes flip-flop means, said flip-flop means generating a first switch trigger signal for triggering said transistor switch to said first state in response to said signal representative of an external need; A second switch trigger signal is applied to an input of the transistor switch and for triggering the transistor switch to the second state in response to the control signal. A solenoid control system according to scope 2. (4) The control means includes first logic circuit means for forcing the flip-flop means to generate the first switch trigger signal in response to the signal representing an external need; and first logic circuit means responsive to the control signal. means for resetting said flip-flop means to generate said second switch trigger signal; and means for generating said control signal within a predetermined period of time in response to a failure of said detection means to reset said flip-flop means. and second logic circuit means for clearing the transistor switch and applying the second switch trigger signal to the transistor switch.