JPS629624A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS629624A
JPS629624A JP14832885A JP14832885A JPS629624A JP S629624 A JPS629624 A JP S629624A JP 14832885 A JP14832885 A JP 14832885A JP 14832885 A JP14832885 A JP 14832885A JP S629624 A JPS629624 A JP S629624A
Authority
JP
Japan
Prior art keywords
film
photoresist
semiconductor substrate
thermal oxide
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14832885A
Other languages
Japanese (ja)
Other versions
JPH0695499B2 (en
Inventor
Shuzo Ito
伊藤 修三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP60148328A priority Critical patent/JPH0695499B2/en
Publication of JPS629624A publication Critical patent/JPS629624A/en
Publication of JPH0695499B2 publication Critical patent/JPH0695499B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To unnecessitate the process in which the back side of a semiconductor substrate is coated with a photoresist film as well as to prevent the flaws and contamination generated by the coating of photoresist by a method wherein the thermally oxided film on the back side of the semiconductor substrate is coated with a protective film which can be removed by the same etching process. CONSTITUTION:A semiconductor substrate 11 is oxidized by heat, and thermally oxided films 14 and 15 are grown on the main surface 12 and the back side 13 of the substrate 11. Subsequently, a silicon dioxide film (protective film) 16 of approximately 8,000Angstrom in thickness is coated on a thermally oxided film 15 by performing a CVD method, and then a photoresist film 17 is made to spray-coat the thermally oxided film 14. Said photoresist film 17 is formed by patterning, and an etching is performed on the thermally oxided film 14 using the pattern-formed photoresist film 17 as a mask. Generally, as the etching speed of the silicon dioxide film 16 is approximately double the etching speed of the thermally oxided films 14 and 15, the thermally oxided film 15 of approximately 4,000Angstrom is left on the back side 13 even when the thermally oxided film 14 is entirely removed by etching. A thermally oxided film 15 is formed by patterning, and a thyristor, for example, can also be formed by introducing impurities using said film 15 as a mask.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は半導体装置の製造方法に係わり、特に、半導体
基板の主面に不純物を導入する際、該主面の裏面を不純
物から保護する為の保護膜の形成方法に関する。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a semiconductor device, and particularly to a method for protecting the back surface of the main surface of a semiconductor substrate from impurities when introducing impurities into the main surface of the semiconductor substrate. The present invention relates to a method for forming a protective film.

〈従来の技術〉 第2図は従来の半導体装置の製造方法を示す工程図であ
り、まず、単結晶シリコンの基板1を熱酸化して、基板
1の主面2とその裏面3とに二酸化シリコン膜4,5を
成長させる(第2図(a))。 続いて、二酸化シリコ
ン膜4上にホトレジスト膜6を塗布し、(第2図(b)
)、この後、リソグラフィ工程によりホトレジスト膜6
をパターン形成する(第2図(C))。この後、基板1
は裏返され、二酸化シリコン膜5上にホトレジスト膜7
が全面に塗布された後、ベーキングを経て硬化させられ
る(第2図(d))。こうして裏面3の保護がなされる
と、すでにパターン形成されているホトレジスト膜6を
マスクとして、二酸化シリコン膜4をエツチングしく第
2図(e))、ホトレジスト膜6が除去された後、拡散
工程により露出された主面2からP型の不純物、例えば
ボロンを導入する(第2図(f))。こうして、拡散領
域8が形成されると、二酸化シリコン膜4の膜厚が増加
させられ、拡散領域8も二酸化シリコンで被われる(第
2図(g))、この後、ホトレジスト膜7が二酸化シリ
コン膜5と共に除去され、二酸化シリコン膜4と露出さ
れた裏面3とにN型の不純物、例えばリンが導入され、
パッシベーションがなされると共に、裏面3はオーミッ
クコンタクトに備え、不純物濃度が高められる。
<Conventional Technology> FIG. 2 is a process diagram showing a conventional method for manufacturing a semiconductor device. First, a single crystal silicon substrate 1 is thermally oxidized to form carbon dioxide on the main surface 2 and the back surface 3 of the substrate 1. Silicon films 4 and 5 are grown (FIG. 2(a)). Subsequently, a photoresist film 6 is applied on the silicon dioxide film 4 (FIG. 2(b)).
), after this, the photoresist film 6 is formed by a lithography process.
A pattern is formed (FIG. 2(C)). After this, board 1
is turned over and a photoresist film 7 is placed on the silicon dioxide film 5.
After being applied to the entire surface, it is cured through baking (Fig. 2(d)). After the back surface 3 is protected in this way, the silicon dioxide film 4 is etched using the patterned photoresist film 6 as a mask (FIG. 2(e)). After the photoresist film 6 is removed, a diffusion process is performed to remove the silicon dioxide film 4. A P-type impurity, such as boron, is introduced from the exposed main surface 2 (FIG. 2(f)). When the diffusion region 8 is formed in this way, the thickness of the silicon dioxide film 4 is increased and the diffusion region 8 is also covered with silicon dioxide (FIG. 2(g)). The silicon dioxide film 4 is removed together with the film 5, and an N-type impurity, for example, phosphorus, is introduced into the silicon dioxide film 4 and the exposed back surface 3.
In addition to passivation, the back surface 3 has an increased impurity concentration in preparation for ohmic contact.

〈発明の解決しようとする問題点〉 しかしながら、従来の製造方法は、二酸化シリコン膜4
をエツチングする前に、二酸化シリコン膜5をホトレジ
スト膜7で被わなければ二酸化シリコン膜4をエツチン
グする間に二酸化シリコン膜5もエツチングされてしま
い、裏面3が露出して、拡散領域8の形成工程中に裏面
3にもP型の不純物が導入され、オーミックコンタクト
が形成できなくなる恐れがあることから、ホトレジスト
膜7の塗布工程が必ず必要であり、そのため、基板1を
裏返して二酸化シリコン膜5上にホトレジスト膜7を塗
布する間に、傷や汚が付着しやすく。
<Problems to be solved by the invention> However, in the conventional manufacturing method, the silicon dioxide film 4
If the silicon dioxide film 5 is not covered with a photoresist film 7 before etching, the silicon dioxide film 5 will also be etched while the silicon dioxide film 4 is being etched, exposing the back surface 3 and forming the diffusion region 8. Since P-type impurities may be introduced into the back surface 3 during the process, making it impossible to form an ohmic contact, the process of coating the photoresist film 7 is absolutely necessary. Therefore, the substrate 1 is turned over and the silicon dioxide film 5 While applying the photoresist film 7 thereon, scratches and dirt are likely to adhere thereto.

これらが原因となって、半導体装置の歩留りの低下、更
には、信頼性の低下が生じるという問題点があった。
Due to these factors, there has been a problem in that the yield of semiconductor devices is lowered, and further, the reliability is lowered.

また、両面にホトレジスト膜を塗布すると、基板1をシ
リコンゴムベルト上に載せて搬送し、スプレーによるホ
トレジストの塗布をしようとすると、ホトレジストがベ
ルトに付着するので、かかる連続的塗布方法による大量
処理ができないという問題点があった。
Furthermore, if a photoresist film is coated on both sides, if the substrate 1 is placed on a silicone rubber belt and conveyed and the photoresist is applied by spraying, the photoresist will adhere to the belt, making it impossible to perform mass processing using such a continuous coating method. There was a problem.

〈問題点を解決するための手段〉 本発明は上記問題点に鑑み、半導体基板の主面と該主面
の裏面とに熱酸化膜を成長させた後、前記半導体基板の
裏面に形成された熱酸化膜上に該熱酸化膜と共に同一エ
ツチング工程で除去可能な保護膜を被着し、半導体基板
の主面上の熱酸化膜をエツチングする際、裏面上に熱酸
化膜を残し、露出した半導体基板の主面から第1導電型
の不純物を導入するとき、裏面を熱酸化膜の残りで保護
し、裏面に第2導電型の不純物を導入する工程に備える
ようにしたことを要旨とする。
<Means for Solving the Problems> In view of the above-mentioned problems, the present invention provides a method for growing a thermal oxide film on the main surface of a semiconductor substrate and the back surface of the main surface, and then forming a thermal oxide film on the back surface of the semiconductor substrate. A protective film that can be removed in the same etching process as the thermal oxide film is deposited on the thermal oxide film, and when the thermal oxide film on the main surface of the semiconductor substrate is etched, the thermal oxide film is left on the back surface and the exposed parts are removed. When introducing impurities of a first conductivity type from the main surface of a semiconductor substrate, the back surface is protected with the remainder of a thermal oxide film in preparation for the step of introducing impurities of a second conductivity type into the back surface. .

〈実施例〉 第1図(a)乃至(g)は、本発明の一実施例を表わす
工程図であり、まず、半導体基板11は熱酸化されて、
その主面12と該主面12の裏面13とには厚さ約1.
6μmの熱酸化膜14,15が成長する(第1図(a)
)、  続いて、熱酸化膜15上には、CVD法により
、二酸化シリコン膜16が約8000人の厚さに被着さ
れ(第1図(b))、その後、熱酸化膜14上にホトレ
ジスト膜17がスプレー塗布される(第1図(C))、
 このホトレジスト9117は、リソグラフィ工程によ
りパターン形成され(第1図(d))、熱酸化膜14は
パターン形成されたホトレジスト膜17をマスクとして
、ふっ酸によりエツチングされる。 一般に、二酸化シ
リコン膜16のエツチング速度は熱酸化膜14.15の
エツチング速度の約2倍なので、熱酸化膜14が全てエ
ツチング除去されても、裏面13には、約4000人の
熱酸化膜15が残っている。 その結果、半導体基板1
の主面12が一部露出され(第1図(e))、ホトレジ
スト膜17の除去後、P型の不純物5例えばボロンが導
入されて拡散領域18が形成される(第1図(f)’)
、  この後、拡散領域18を二酸化シリコン膜で被い
、裏面13を露出させ。
<Example> FIGS. 1(a) to (g) are process diagrams showing an example of the present invention. First, a semiconductor substrate 11 is thermally oxidized,
The main surface 12 and the back surface 13 of the main surface 12 have a thickness of about 1.5 mm.
Thermal oxide films 14 and 15 of 6 μm are grown (Fig. 1(a)).
), Next, a silicon dioxide film 16 is deposited on the thermal oxide film 15 to a thickness of approximately 8,000 mm by the CVD method (FIG. 1(b)), and then a photoresist is deposited on the thermal oxide film 14. A membrane 17 is spray applied (FIG. 1(C));
This photoresist 9117 is patterned by a lithography process (FIG. 1(d)), and the thermal oxide film 14 is etched with hydrofluoric acid using the patterned photoresist film 17 as a mask. Generally, the etching speed of the silicon dioxide film 16 is about twice that of the thermal oxide film 14.15, so even if the thermal oxide film 14 is completely etched away, about 4000 thermal oxide films 15. remains. As a result, the semiconductor substrate 1
A part of the main surface 12 is exposed (FIG. 1(e)), and after removing the photoresist film 17, a P-type impurity 5 such as boron is introduced to form a diffusion region 18 (FIG. 1(f)). ')
After that, the diffusion region 18 is covered with a silicon dioxide film, and the back surface 13 is exposed.

N型の不純物、例えばリンを導入する(第1図(g))
、  その結果、パッシベーションがなされると共に、
裏面13の不純物濃度が増加し、オーミックコンタクト
に適した裏面13が得られる。
Introducing an N-type impurity, for example, phosphorus (Figure 1 (g))
, As a result, passivation is achieved and
The impurity concentration of the back surface 13 increases, and a back surface 13 suitable for ohmic contact is obtained.

なお、一実施例では、保護膜としてCVD法による二酸
化シリコン膜を使用したが、保護膜は、熱酸化膜と同一
のエツチング工程で除去できればよく、イオンミリング
によるエツチングを使用すれば保護膜の材質は広く選定
することができる。
In one embodiment, a silicon dioxide film formed by CVD was used as the protective film, but the protective film only needs to be removed in the same etching process as the thermal oxide film, and if etching by ion milling is used, the material of the protective film can be removed. can be selected from a wide range.

また、裏面13上の熱酸化膜15を全面的に除去する必
要はなく、これをパターン形成し、パターン形成された
熱酸化[15をマスクとして不純物の導入をし、例えば
サイリスタを形成することもできる。
Furthermore, it is not necessary to completely remove the thermal oxide film 15 on the back surface 13; it is also possible to pattern it and introduce impurities using the patterned thermal oxide film 15 as a mask to form, for example, a thyristor. can.

〈効果〉 以上、説明してきたように、本発明によれば、裏面上の
熱酸化膜を同一エツチング工程で除去可能な保護膜で被
ったので、裏面をホトレジスト膜で被う工程が不要にな
り、ホトレジストの塗布に伴う、傷や汚を防止すること
ができ、歩留りと信頼性の向上を図れるという効果が得
られる。
<Effects> As explained above, according to the present invention, the thermal oxide film on the back side is covered with a protective film that can be removed in the same etching process, so the process of covering the back side with a photoresist film is no longer necessary. , it is possible to prevent scratches and stains associated with the application of photoresist, and the effect of improving yield and reliability can be obtained.

さらに、ホトレジストは主面上の熱酸化膜にのみ塗布さ
れるので、半導体基板をコンベアで搬送しつつホトレジ
ストをスプレー塗布することができ、ホトレジストの塗
布工程の処理量を増加できるという効果も得られる。
Furthermore, since the photoresist is applied only to the thermal oxide film on the main surface, the photoresist can be spray applied while the semiconductor substrate is being transported by a conveyor, which also has the effect of increasing the throughput of the photoresist application process. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)乃至(g)は本発明の一実施例を表わす工
程図、第2図(a)乃至(h)は従来例を表わす工程図
である。 11・・・・・・・半導体基板 12・・・・・・・主面 13・・・・・・・裏面 14.15・・・・熱酸化膜 16・・・・・・・保護膜 特許出願人      ローム株式会社代理人   弁
理士  桑 井 清 −第1図 第1図 (f) 第1図 第2図 (e ) (↑ ) 第2図 ζg)′ 第2図
FIGS. 1(a) to (g) are process diagrams representing one embodiment of the present invention, and FIGS. 2(a) to (h) are process diagrams representing a conventional example. 11...Semiconductor substrate 12...Main surface 13...Back surface 14.15...Thermal oxide film 16...Protective film patent Applicant ROHM Co., Ltd. Agent Patent Attorney Kiyoshi Kuwai - Figure 1 Figure 1 (f) Figure 1 Figure 2 (e) (↑) Figure 2 ζg)' Figure 2

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の主面と該主面の裏面とに熱酸化膜を成長さ
せる工程と、前記半導体基板の裏面に成長した熱酸化膜
上に該熱酸化膜と共に同一エッチング工程で除去可能な
保護膜を被着する工程と、前記半導体基板の主面上に成
長した熱酸化膜を選択的に除去して半導体基板の主面の
一部を露出させると共に裏面に熱酸化膜を残す工程と、
露出した半導体基板の主面から第1導電型の不純物を導
入する工程と、裏面の熱酸化膜の少なくとも一部を除去
する工程と、露出した裏面から第2導電型の不純物を導
入する工程とから成る半導体装置の製造方法。
A step of growing a thermal oxide film on a main surface of a semiconductor substrate and a back surface of the main surface, and a protective film that can be removed together with the thermal oxide film in the same etching step on the thermal oxide film grown on the back surface of the semiconductor substrate. a step of selectively removing the thermal oxide film grown on the main surface of the semiconductor substrate to expose a part of the main surface of the semiconductor substrate and leaving a thermal oxide film on the back surface;
A step of introducing an impurity of a first conductivity type from the exposed main surface of the semiconductor substrate, a step of removing at least a part of the thermal oxide film on the back surface, and a step of introducing an impurity of a second conductivity type from the exposed back surface. A method for manufacturing a semiconductor device comprising:
JP60148328A 1985-07-08 1985-07-08 Method for manufacturing semiconductor device Expired - Fee Related JPH0695499B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60148328A JPH0695499B2 (en) 1985-07-08 1985-07-08 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60148328A JPH0695499B2 (en) 1985-07-08 1985-07-08 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS629624A true JPS629624A (en) 1987-01-17
JPH0695499B2 JPH0695499B2 (en) 1994-11-24

Family

ID=15450318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60148328A Expired - Fee Related JPH0695499B2 (en) 1985-07-08 1985-07-08 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0695499B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038754A (en) * 2021-10-25 2022-02-11 上海华力集成电路制造有限公司 Method for improving FinFET crystal back process
CN114038754B (en) * 2021-10-25 2024-04-30 上海华力集成电路制造有限公司 Method for improving FinFET crystal back process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114169A (en) * 1974-02-15 1975-09-06
JPS566469A (en) * 1979-06-28 1981-01-23 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50114169A (en) * 1974-02-15 1975-09-06
JPS566469A (en) * 1979-06-28 1981-01-23 Toshiba Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114038754A (en) * 2021-10-25 2022-02-11 上海华力集成电路制造有限公司 Method for improving FinFET crystal back process
CN114038754B (en) * 2021-10-25 2024-04-30 上海华力集成电路制造有限公司 Method for improving FinFET crystal back process

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JPH0695499B2 (en) 1994-11-24

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