JPS6295840A - Transistor device - Google Patents

Transistor device

Info

Publication number
JPS6295840A
JPS6295840A JP60238117A JP23811785A JPS6295840A JP S6295840 A JPS6295840 A JP S6295840A JP 60238117 A JP60238117 A JP 60238117A JP 23811785 A JP23811785 A JP 23811785A JP S6295840 A JPS6295840 A JP S6295840A
Authority
JP
Japan
Prior art keywords
transistor
chip
conductor
substrate
rectangular conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60238117A
Other languages
Japanese (ja)
Inventor
Minoru Kadota
門田　実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60238117A priority Critical patent/JPS6295840A/en
Publication of JPS6295840A publication Critical patent/JPS6295840A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the loss in a high-frequency signal and to make the electrical characteristics of a transistor chip fulfill sufficiently by a method wherein a rectangular conductor is provided in the substrate and the outer leads and the transistor chip are mutually connected through the conductor. CONSTITUTION:A rectangular hole is bored in that part of a substrate 3 whereon a transistor chip 5 is placed. A rectangular conductor 15 is inserted in this hole. A semiconductor capacitor 14 is provided on the upper surface of the conductor 15. Outer leads 1 and 2 and the chip 5 are mutually connected through the conductor 15. Therefore, the inductance component between the chip 5 and an electrode becomes smaller. By this way, the loss in a high-frequency signal is reduced and the electrical characteristics of the chip 5 can be sufficiently delivered.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はトランジスタ装置、特に高周波高出力トラン
ジスタの改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in transistor devices, particularly high-frequency, high-output transistors.

〔従来の技術〕[Conventional technology]

第５図は従来のトランジスタ装置を示す外装内の組立上
面図、第６図はその断面図であり２図において、　（１
）　、　（２１は外部リード、（３）はこの外部リード
に接する金属膜電極を有した基板、（４）はこの基板に
密着固定された放熱フィン、（５）は基板上に設けられ
たトランジスタチップ２（６）は同じく半導体コンデン
サ、　（７）　、　（８１、＋９）　、α１はリード線
、αυは電極用金属板である。Fig. 5 is an assembled top view of the inside of the exterior showing a conventional transistor device, and Fig. 6 is its cross-sectional view. In Fig. 2, (1
), (21 is an external lead, (3) is a substrate with a metal film electrode in contact with this external lead, (4) is a heat dissipation fin closely fixed to this substrate, and (5) is a transistor provided on the substrate. Chip 2 (6) is also a semiconductor capacitor, (7), (81, +9), α1 is a lead wire, and αυ is a metal plate for electrode.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のトランジスタ装置は上記のように構成されるので
、トランジスタチップ（５）からエミッタリード線（７
）、電極用金属板αυを介して基板（３）に至るまでの
エミッタリードインダクタンス成分が、高周波電流の流
れる篭極用金属板住υにより犬きくな夛、トランジスタ
の電気的性能に悪影響を及ぼしていた。また電極用金属
板住υの存在によシ、出力側の高インピーダンス化をは
かるだめの出力整合回路を内蔵することができない、と
いう問題点かあった。Since the conventional transistor device is configured as described above, the emitter lead wire (7) is connected from the transistor chip (5).
), the emitter lead inductance component from the electrode metal plate αυ to the substrate (3) is distorted by the high-frequency current flowing through the cage electrode metal plate αυ, which adversely affects the electrical performance of the transistor. was. Furthermore, due to the presence of the metal plate for the electrodes, there was a problem in that it was not possible to incorporate an output matching circuit to increase the impedance on the output side.

この発明は、上記のような問題点を解消するためになさ
れたもので、トランジスタチップの電気的性能を十分に
発揮させるために、エミッタリードインダクタンス成分
を小さくシ、また出力整合回路の内蔵を容易にすること
を目的とする。This invention was made to solve the above-mentioned problems, and in order to fully demonstrate the electrical performance of the transistor chip, it reduces the emitter lead inductance component and makes it easy to incorporate an output matching circuit. The purpose is to

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るトランジスタ装置は、トランジスタチッ
プが載置される基板の一部に角形の穴をあけ、この穴の
中に角形導体を入れ、この角形導体の上面に半導体コン
デンサを設けるものとした。In the transistor device according to the present invention, a square hole is formed in a part of the substrate on which the transistor chip is mounted, a square conductor is placed in the hole, and a semiconductor capacitor is provided on the upper surface of the square conductor.

〔作用〕[Effect]

この発明によれば、基板内に角形導体を設けることによ
り、エミッタリードから比較的小さいインダクタンス成
分を介して電極に接続できる。このためトランジスタチ
ップと電極間のインダクタンス成分を小さくできるとと
もに、角形導体の上面に半導体コンデンサを載せること
による出力整合回路の内蔵が可能となり、トランジスタ
の電気的性能を大巾に向上させることになる。According to this invention, by providing a rectangular conductor within the substrate, the emitter lead can be connected to the electrode via a relatively small inductance component. This makes it possible to reduce the inductance component between the transistor chip and the electrodes, and also to embed an output matching circuit by mounting a semiconductor capacitor on the top surface of the rectangular conductor, greatly improving the electrical performance of the transistor.

〔発明の実施例〕[Embodiments of the invention]

第１図はこの発明の一実施例に係るトランジスタ装置を
示す外装内の組立上面図、第２図はその断面図であり、
（１）〜α〔は上記従来装置と同一または相当するもの
でるる。（ｌ！９は基板（３）に設けられた角形の穴の
中に挿入された角形導体でアシ、第３図にその斜視図を
示す。この角形導体α９は、その下面が放熱フィン（４
）に半田付けされるとともに。FIG. 1 is an assembled top view of the interior of a transistor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view thereof.
(1) to [alpha] are the same as or equivalent to the above-mentioned conventional device. (l!9 is a rectangular conductor inserted into a rectangular hole provided in the board (3), a perspective view of which is shown in Fig. 3.The lower surface of this rectangular conductor α9 has a radiation fin
) as well as being soldered.

その上面に半導体コンデンサＩが半田付けされる。A semiconductor capacitor I is soldered to its upper surface.

この半導体コンデンサＩはリード線（７）、αり、α３
により、外部リード＋１）とトランジスタチップ（５）
との間に挿入されることになる。第４図は上記したこの
発明に係るトランジスタ装置の等価回路図である。This semiconductor capacitor I has a lead wire (7), α ri, α3
Therefore, external lead +1) and transistor chip (5)
It will be inserted between. FIG. 4 is an equivalent circuit diagram of the transistor device according to the invention described above.

上記のように構成されたトランジスタ装置においては、
トランジスタチップ（５）からのリード線（７）とエミ
ッタ電極間に角形導体α９を設けたから、従来装置のよ
うに電極用金属板を介さず、直接エミッタ電極につなが
る構造となシ、エミッタリードインダクタンス成分が小
さくなる。まだ、角形導体（至）の上面に半導体コンデ
ンサＩを設は出力整合回路を構成できるので、出力側の
高インピーダンス化をはかることができ、外部回路の設
計、構成が容易となり、高周波高出力トランジスタの電
気的性能を大巾に向上させることになる。In the transistor device configured as above,
Since the rectangular conductor α9 is provided between the lead wire (7) from the transistor chip (5) and the emitter electrode, the structure is connected directly to the emitter electrode without going through the metal plate for the electrode as in conventional devices, and the emitter lead inductance components become smaller. However, it is possible to configure an output matching circuit by installing a semiconductor capacitor I on the top surface of a rectangular conductor, making it possible to achieve high impedance on the output side, making it easy to design and configure external circuits, and making it possible to create high-frequency, high-output transistors. This will greatly improve the electrical performance of the device.

なお、上記実施例ではエミッタ電極部の一部の個所に適
用する場合について述べたが、他のトランジスタ電極部
等のインダクンスを小さくするための個所にも同様に適
用できるものである。In the above embodiment, the case where the present invention is applied to a part of the emitter electrode section has been described, but it can be similarly applied to other sections such as the transistor electrode section where inductance is to be reduced.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおシ、トランジスタ外装内の
インダクタンス成分を小さくシ、出力整合回路の内蔵を
可能としたから、高周波信号における損失が少なく、外
部回路の設計、構成が容易となシ、トランジスタの電気
的特性を十分に発揮させることができる。As explained above, this invention reduces the inductance component inside the transistor exterior and makes it possible to incorporate an output matching circuit, which reduces loss in high-frequency signals and facilitates the design and configuration of external circuits. It is possible to fully exhibit the electrical characteristics of.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例に係るトランジスタ装置を
示す外装内の組立上面図、第２図はその断面図、第３図
はこの発明に用いられる角形導体の一例を示す斜視図、
第４図は上記第１図装置の等価回路図、第５図は従来の
トランジスタ装置を示す外装内の組立上面図、第６図は
その断面図である。 図において、　（１１、（２１は外部リード、（３）は
基板。 （４）は放熱フィン、（５）はトランジスタチップ、（
７）。 （ｓ＋　、　（９）　、　Ｑｌ　、　＠７Ｊ　、　（１
３はリード線、α４は半導体コンデンサ、αυは角形導
体でるる。 なお、各図中、同一符号は同一または相当部分を示す。FIG. 1 is an assembled top view of the inside of the exterior showing a transistor device according to an embodiment of the present invention, FIG. 2 is a sectional view thereof, and FIG. 3 is a perspective view showing an example of a rectangular conductor used in the present invention.
FIG. 4 is an equivalent circuit diagram of the device shown in FIG. 1, FIG. 5 is an assembled top view of the conventional transistor device inside the exterior, and FIG. 6 is a sectional view thereof. In the figure, (11, (21 is an external lead, (3) is a board, (4) is a heat dissipation fin, (5) is a transistor chip, (
7). (s+, (9), Ql, @7J, (1
3 is a lead wire, α4 is a semiconductor capacitor, and αυ is a rectangular conductor. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] （１）放熱フィンに密着固定された金属膜電極を有した
基板、この基板上に設けられた外部リード及びトランジ
スタチップ、上記基板に設けられた角形の穴、この穴に
挿入され下面が上記放熱フィンに固定された角形導体を
備え、この角形導体を介して上記外部リードとトランジ
スタチップを接続したことを特徴とするトランジスタ装
置。(1) A substrate with a metal film electrode closely fixed to a heat dissipation fin, an external lead and a transistor chip provided on this substrate, a square hole provided in the above substrate, and the bottom surface inserted into this hole serves as the heat dissipation. 1. A transistor device comprising a rectangular conductor fixed to a fin, the external lead and the transistor chip being connected via the rectangular conductor. （２）角形導体が上面に半導体コンデンサを有し、この
半導体コンデンサを介して外部リードとトランジスタチ
ップを接続したことを特徴とする特許請求の範囲第１項
記載のトランジスタ装置。(2) The transistor device according to claim 1, wherein the rectangular conductor has a semiconductor capacitor on its upper surface, and the external lead and the transistor chip are connected via the semiconductor capacitor.
JP60238117A 1985-10-22 1985-10-22 Transistor device Pending JPS6295840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60238117A JPS6295840A (en) 1985-10-22 1985-10-22 Transistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60238117A JPS6295840A (en) 1985-10-22 1985-10-22 Transistor device

Publications (1)

Publication Number Publication Date
JPS6295840A true JPS6295840A (en) 1987-05-02

Family

ID=17025430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60238117A Pending JPS6295840A (en) 1985-10-22 1985-10-22 Transistor device

Country Status (1)

Country Link
JP (1) JPS6295840A (en)

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