JPS6295092A - Chroma signal processing circuit for vtr - Google Patents

Abstract

PURPOSE:To easily make an IC on an IC substrate of one chip, delete an installation of its terminal pin and external part and to make the device compact by digitally processing a chroma signal. CONSTITUTION:A chroma signal Sc applied from a video signal system of a TV is applied to an ACC detector 6 through an ACC circuit 4. To the ACC detector 6, a color burst signal sampled from a digital chroma signal by a burst gate circuit 8 and an analog chroma signal of an output side of the ACC circuit 4 are applied. The ACC detector 6 detects a leading value level of the color burst signal. The output level of the ACC circuit 4 is controlled so as make the level of the analog chroma signal fixed and the analog chroma signal of the fixed level is obtained. The level controlled analog chroma signal is applied to an A/D 10 and converted into a digital chroma signal. To the A/D 10, a sampling signal of a phase synchronizing with a color subcarrier is applied from a voltage control oscillator 12 and the digital chroma signal of the phase synchronizing with the color subcarrier is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chroma signal processing circuit for a VTR (video tape recorder), and particularly to frequency conversion by digital processing of a chroma signal.

[Conventional technology]

Conventionally, in a chroma signal processing circuit using analog signal processing, an oscillation frequency from an oscillation circuit synchronized with a burst signal and a horizontal synchronization signal is added to a sub-converter by an APC (automatic phase control) circuit and an AFC (automatic frequency control) circuit. This local frequency signal and the chroma signal are added to the main converter to process the chroma signal.

[Problem that the invention seeks to solve]

In such conventional analog chroma signal processing circuits, the analog processing circuit section and the digital processing circuit section are mixed, and when configured with IC, the analog processing circuit section and the digital processing circuit section are placed on separate semiconductor substrates. However, the number of terminal pins increases, the configuration becomes complicated, and there is a limit to the reduction of external components, which increases the manufacturing cost of the entire chroma signal processing process.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a chroma signal processing circuit for a VTR that digitizes the frequency conversion of a chroma signal and facilitates integration into an IC.

[Means for solving problems]

As shown in FIGS. 1 and 2, the chroma signal processing circuit of the VTR of the present invention processes an analog chroma signal by sampling it using a sampling signal whose phase is synchronized with the color subcarrier and converts it into a digital chroma signal. Demodulates a digital color difference signal from the digital chroma signal obtained by the digital converter 10 and this analog-to-digital converter, and converts the sampling frequency of this digital color difference signal to another sampling frequency whose phase is synchronized with the color subcarrier. After that, a frequency conversion circuit 20 demodulates the original digital chroma signal.
and a digital chroma signal that converts the digital chroma signal obtained by this frequency conversion circuit into an analog chroma signal.
It is composed of an analog converter 32.

[For production]

The chroma signal processing circuit of the VTR of the present invention digitizes an analog chroma signal, demodulates a digital color difference signal from the digital chroma signal, and converts the sampling frequency of this digital color difference signal to another sampling frequency whose phase is synchronized with the color subcarrier. The frequency conversion of the color difference signal is realized by digital processing by demodulating the original digital chroma signal and converting this digital chroma signal into an analog chroma signal.

In the chroma signal processing circuit of the VTR of the present invention, the frequency conversion circuit is provided with a storage means for storing the digital color difference signal, and when storing the digital color difference signal stored in the storage means, the frequency conversion circuit converts the digital color difference signal stored in the storage means into a low frequency conversion color subsystem. By reading out a sampling signal whose phase is synchronized with the carrier, frequency conversion of the color difference signal during recording can be performed by digital processing.

Further, in the chroma signal processing circuit of the VTR of the present invention, the frequency conversion circuit is provided with a storage means for storing the digital low-pass converted color difference signal, and when playing back, the frequency conversion circuit is configured to read the digital low-pass converted color difference signal stored in the storage means. By reading out a sampling signal whose phase is synchronized with the color subcarrier, frequency conversion of the color difference signal during reproduction can be performed by digital processing.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

1 and 2 show an embodiment of a chroma signal processing circuit for a VTR according to the present invention. FIG. 1 shows the configuration during recording, and FIG. 2 shows the configuration during playback, which are the same during recording and playback. The same reference numerals are given to the circuit parts having the configuration.

In FIG. 1, a chroma signal Sc given from a TV video signal system (not shown) is filtered through a bandpass filter (BPF).
) 2, it is added to an ACC (automatic chroma control) circuit 4 for automatically adjusting the signal level, and the AC
The chroma signal Sc passed through the C circuit 4 is applied to an ACC detector 6.

The ACC detector 6 is supplied with the color hearth H word extracted from the digital chroma signal by the burst gate circuit 8, as well as the analog chroma signal on the output side of the ACC circuit 4, and the ACC detector 6 is connected to the color hearth H word extracted from the digital chroma signal.
・Detect the starting value level of the signal, and use the detected output to keep the analog chroma signal level constant
The output level of the CC circuit 4 is controlled, and an analog chroma signal of a constant level is obtained.

The analog chroma signal whose level has been controlled by the ACC circuit 4 is applied to an analog/digital converter (A/D) 10 and converted into a digital chroma signal. A/D 1
0, a sampling signal whose phase is synchronized with the color subcarrier is added from the voltage controlled oscillator 12, and by this sampling signal, the analog chroma signal is sampled and digitized, and a digital signal whose phase is synchronized with the color subcarrier is added. Chroma signal is obtained.

Here, the voltage controlled oscillator 12 constitutes a phase-locked loop (PLL) together with the frequency divider 14 and the phase comparator 16.18, and generates a sampling signal (3.58Mtlz) of a specific frequency whose phase is synchronized with the color subcarrier. ) oscillates. That is, the oscillation output of the voltage controlled oscillator 12 is divided by the frequency divider 14 to the same frequency as the horizontal synchronization frequency f8, and then added to the phase comparator 16 to calculate the phase difference with the horizontal synchronization signal (f). At the same time as being detected, the oscillation output of the voltage controlled oscillator 12 is applied to a phase comparator 18, and the phase difference with the color burst signal obtained by the burst gate circuit 8 is detected. These detected phase differences are applied to the voltage controlled oscillator 12 as a control voltage for controlling the oscillation frequency, and the oscillation frequency f is set. is adjusted according to the sum of both phase differences, and as a result, voltage controlled oscillator 1
The sampling signal applied to the A/D I O by the oscillation output of No. 2 is synchronized in phase with the horizontal synchronization signal and the color burst signal.

The digital chroma signal obtained by the A/D 10 is then applied to the demodulation circuit 22 of the frequency conversion circuit 20.
The digital color difference signals of R-Y and B-Y are demodulated. In this case, a sampling signal whose phase is synchronized with the color subcarrier is applied to the demodulation circuit 22 from the voltage controlled oscillator 12 similarly to A/DIO, and the demodulation circuit 22 generates a digital signal whose phase is synchronized with the color subcarrier. The color difference signal is demodulated.

This digital color difference signal is applied to the modulation circuit 24, which modulates another sampling signal (clock) synchronized with the low frequency conversion color subcarrier, thereby outputting it from the modulation circuit 24 as a frequency-converted digital chroma signal. be done. modulation.

The circuit 24 receives a sampling signal (160fH) synchronized with the low frequency conversion color subcarrier from the rotary circuit 26.
is added, and the digital chroma signal is frequency-converted by this low-pass conversion color subcarrier.

In this case, the oscillation frequency is set by the crystal oscillation circuit 28, and a timing signal whose phase is synchronized with the low frequency conversion color subcarrier by the phase locked loop (PLL) 30 is added to the low frequency circuit 26 as a sampling signal. ing.

The digital chroma signal obtained by the frequency conversion circuit 20 is then converted to a digital-to-analog converter (D/A converter).
) 32 and is converted into an analog chroma signal in response to a timing signal applied from the rotary circuit 26.

This analog chroma signal passes through a bandpass filter 34, is applied to a recording magnetic head 36 via a signal processing circuit (not shown), is converted into magnetism, and is magnetically recorded on a magnetic tape (not shown) as a recording medium. be done.

Next, as shown in FIG. 2, in the chroma signal processing circuit during reproduction, the image recorded on the magnetic tape as a recording medium is reproduced by the reproduction magnetic head 38, and the chroma signal detected by this reproduction is The signal is passed through bandpass filter 3
9, the signal is applied to an ACC circuit 4 for automatically adjusting the signal level.

The chroma signal whose level has been adjusted by the ACC circuit 4 is added to the A/DIO and converted into a digital signal. In this case, a sampling signal (160f,) whose phase is synchronized with the low frequency conversion color subcarrier is applied from the voltage controlled oscillator 12 to the A/D 10, and the tear-1-log chroma signal is sampled by this sampling signal. and converted into a digital chroma signal.

Here, as in the embodiment shown in FIG. A sampling signal (3.58 MHz) of a specific frequency whose phase is synchronized with the color subcarrier is oscillated. That is, the oscillation output of the voltage controlled oscillator 12 is divided by the frequency divider 14 to the same frequency as the horizontal synchronization frequency f, and then added to the phase comparator 16 to generate the horizontal synchronization signal (fH).
The phase difference between voltage controlled oscillator B 1 and
The oscillation output of No. 2 is applied to the phase comparator 18, and the phase difference with the color nost signal obtained by the burst gate circuit 8 is detected. is applied as a control voltage to control its oscillation frequency r. is adjusted according to the added value of the phase difference, and as a result, the sampling signal applied to the A/DIO by the oscillation output G of the voltage controlled oscillator 12 is synchronized in phase with the horizontal synchronization signal and the color burst signal. ing.

The digital chroma signal obtained by the A/D 10 is then applied to the demodulation circuit 42 of the frequency conversion circuit 40.
The digital low-pass conversion color difference signals of R-Y and B-Y are demodulated, and in this case, the demodulation circuit 42 receives a sampling signal whose phase is synchronized with the low-pass conversion color subcarrier, similar to A/DIO, using a voltage controlled oscillator. 12, and the digital low-pass conversion color difference signal whose phase is synchronized with the low-pass conversion color subcarrier is demodulated by the demodulating circuit 42.

This digital low-pass conversion color difference signal is applied to the modulation circuit 44, which modulates another sampling signal (clock) synchronized with the low-pass conversion color subcarrier, thereby converting the frequency-converted digital chroma signal to the modulation circuit 44. 44. A sampling signal (160f, . . . ) synchronized with the color subcarrier is applied to the modulation circuit 44 from the crystal oscillation circuit 2B, and the digital chroma signal is frequency-converted.

The digital chroma signal obtained by this frequency conversion circuit 40 is added to the D/A 32, and is sent to the crystal oscillation circuit 2.
It is converted into an analog chroma signal in response to a timing signal applied from 8.

This analog chroma signal is applied to the ACC detector 6 along with a color burst signal processed from the digital chroma signal from the A/DIO by the burst gate circuit 8. The ACC detector 6 detects the head value level of the color burst signal, and this detection output is applied to the ACC circuit 4, and the output level of the ACC circuit 4 is adjusted so that the level of the analog chroma signal is constant based on the detection output. is controlled.

Then, the output of the D/A 32 is applied to a high frequency amplification section (RF) of a TV receiver (not shown) through a bandpass filter 45, and the TV receiver obtains an image corresponding to the chroma signal reproduced by the magnetic head 38. It will be done.

Note that the killer circuit 46 detects whether the mode is monochrome or color mode depending on the presence or absence of a color burst signal from the burst gate circuit 8, and controls the D/A 3 according to the detection output.
Controls the passage of the 2nd chroma signal.

Next, FIGS. 3 and 4 show specific configuration examples of the frequency conversion system in the chroma signal processing circuit of the VTR of the present invention, and FIG. 3 shows the chroma signal processing circuit during recording shown in FIG. 1. The specific structure of the middle frequency political change IQ circuit 20, Part 4
The figure shows a specific example of the structure of the frequency conversion circuit 40 in the chroma signal processing circuit during reproduction shown in FIG.

As shown in FIG. 3, in the frequency conversion circuit 20, the demodulation circuit 22 includes sampling gate 1 circuits 50, 52, .
The modulation circuit 24 is composed of sampling gate circuits 60, 62, an adder 64, and a sampling gate circuit 66. Each sampling gate circuit 50.52.54.56
．． 60, 62, and 66 can be configured with a gate circuit that allows a signal to pass depending on a specific sampling signal, a launch circuit, or a storage means that uses a specific sampling signal as a successive signal.

A/DIQ, each sampling gate circuit 50.
52.54.56.60.62.66 and D/A32
Additionally, a specific sampling signal is applied from a timing generation circuit 68. That is, the timing generation circuit 68 has a signal A in FIG. 5 which is 160 times the horizontal synchronization frequency r□.
Timing signal 160fll, horizontal synchronization frequency f shown in
The timing signal 910 shown in E of FIG. 5 is 910 times H.
f, 4 is added, and the timing generation circuit 68 generates the timing signal 910fH1 shown in FIG. 5, its inverted timing signal 910fH1, the timing signal LP shown in I in FIG. P
2. Timing signal 40 f HR shown in C of FIG.
.

A timing signal 40f ) 18 shown in D in FIG. 5, a timing signal 160fH1 shown in 8 in FIG.
．． 52, an inverted timing signal 910fH, a sampling gate circuit 54, a timing signal LPz, a sampling gate circuit 56, a timing signal LPz, and a sampling gate circuit 60, a timing signal 40fH*.
, the timing signal 40 is sent to the sampling gate circuit 62.
f HB, inverted timing signal 160fH to sampling gate circuit 66, timing signal 160fH to D/A 32
Add f H respectively.

Therefore, according to such a configuration, during recording, after the chroma signal is converted into a digital signal by the A/D 10 according to each timing signal, the sampling gate circuits 50, 52, 54, 56, 60, 62, . The signal is allowed to pass in response to a timing signal added as a sampling signal to the D/A 32, and the digital color difference signal is demodulated, frequency converted, and modulated to obtain a low frequency digital chroma signal, which is sent to the D/A 32. The applied timing signal allows the low frequency digital chroma signal to be converted back into a low frequency analog chroma signal.

In addition, as shown in FIG. 4, the frequency conversion circuit 4 at the time of reproduction
0, the demodulation circuit 42 includes a sampling gate circuit 69.70 and an adder 72, and the demodulation circuit 44 includes a sampling gate circuit 74.76.7.
8.8o, 82.84, adder 86 and sampling gate circuit 88. Each sampling gate circuit 69.70.74.76.78.80.82.8
4. As in the previous embodiment, 88 can be constituted by a gate circuit or latch circuit that allows a signal to pass depending on a specific sampling signal, or a storage means that uses a specific sampling signal as a successive signal.

The A/D 10 and each sampling gate circuit 69.
70.74.76.78.80.82.84.88 and the D/A 32 are supplied with specific sampling signals from a similar timing generation circuit 68. That is,
The timing generation circuit 68 also generates a timing signal 160fH1 shown in A in FIG. 5 which is 160 times the horizontal synchronization frequency f11 and a timing signal 910 shown in E in FIG. 5 which is 910 times the horizontal synchronization frequency r. fH is added, and the timing generation circuit 68 generates the timing signal 160f shown in A in FIG. 5 or its inverted timing signal 160.
fH, timing signals Lp shown in P, , Q, R, , S, T in Fig. 5: + , LP, , LPl, LP6, LP7
, the timing signal (RY) 3 shown in U in FIG.
B-Y)ff, timing signal 910 shown in FIG.
f,, generates an inverted timing signal 910 f H-, a timing signal 160fH to A/DIO, and an inverted timing signal 160 to the sampling gate circuit 69.70.
f,, the timing signal L is applied to the sampling gate circuit 74.
P4, timing signal L to sampling gate circuit 76
P3, timing signal L to sampling gate circuit 78
P b , timing signal LP 't to sampling gate circuit 80 , timing signal LP s to sampling gate circuit 82 , (RY)x, timing signal LP to sampling gate circuit 84, (BY):l,
Inverted timing signal 91 to sampling gate circuit 88
0f, , timing signal 910f to D/A 32
, respectively.

According to such a configuration, during reproduction, after the chroma signal is converted into a digital signal by the A/DIO according to these timing signals, the sampling gate circuit 6
9.70.74.76.78.80.82.84.88
In response to a timing signal added as a sampling signal, the signal is allowed to pass, and the digital color difference signal is demodulated, frequency converted, and modulated to obtain a high frequency digital chroma signal. The high-frequency digital chroma signal is again converted into a high-frequency analog chroma signal by the timing signal.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(a) By digitally processing the chroma signal, it can be easily integrated into an IC on a single-chip IC board, and the terminal pin installation and external parts can be reduced, making it possible to miniaturize the device. can.

(bl Digital processing can reduce the time axis fluctuations of the chroma signal, making it possible to obtain high-quality images not only during normal playback but also during other special playback.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the chroma signal processing circuit of the VTR of the present invention during recording, and FIG.
3 is a block diagram showing an example of the frequency conversion system during recording in the chroma signal processing circuit of the VTR of the present invention, and FIG. FIG. 5 is a block diagram showing an embodiment of the frequency conversion system during reproduction in the chroma signal processing circuit of the VTR of the invention, and FIG. 5 is a timing chart showing its operation timing. IO...Analog-digital converter, 2o, 40.
... Frequency conversion circuit, 22.42 ... Demodulation circuit, 24
．． 44...Modulation circuit, 32...Digital-to-analog converter.

Claims (3)

[Claims] (1) An analog-digital converter that samples an analog chroma signal using a sampling signal whose phase is synchronized with the color subcarrier and converts it into a digital chroma signal, and converts the digital chroma signal obtained by this analog-digital converter into a digital a frequency conversion circuit that demodulates the color difference signal, converts the sampling frequency of the digital color difference signal to another sampling frequency whose phase is synchronized with the color subcarrier, and then demodulates the original digital chroma signal; A chroma signal processing circuit for a VTR, comprising a digital-to-analog converter for converting the obtained digital chroma signal into an analog chroma signal. (2) The frequency conversion circuit is provided with storage means for storing the digital color difference signal, and when storing, converts the digital color difference signal stored in the storage means into a sampling signal whose phase is synchronized with the low frequency conversion color subcarrier. The VTR according to claim 1, characterized in that the VTR is read out by
chroma signal processing circuit. (3) The frequency conversion circuit is provided with a storage means for storing the digital low-pass converted color difference signal, and during playback, the digital low-pass converted color difference signal stored in the storage means is sampled in phase synchronization with the color subcarrier. The VT according to claim 1, characterized in that the VT is read out by a signal.
R's chroma signal processing circuit.