JPS6295093A - Chroma signal processing circuit for vtr - Google Patents

Abstract

PURPOSE:To easily perform a delay processing of a chroma signal without requiring an external circuit such as a glass delay line by adding a digital chroma signal delayed for a specific time of more than its one horizontal synchronizing period to the digital chroma signal. CONSTITUTION:A digital low frequency converting chroma signal obtained in an A/D8 is applied to a demodulating circuit 20 for demodulating a color difference signal and the color difference signals R-Y, B-Y are demodulated from the digital low frequency converting chroma signal. In this case, to the demodulating circuit 20, a timing signal is applied from a voltage control oscillator 10 and a digital demodulating processing is carried out according to the timing signal. These digital color difference signals are applied to a delay adding circuit 22 for performing the prescribed delay processing to the digital low frequency converting chroma signal. This delay adding circuit 22 adds the digital color difference signal delayed by the specific time more than its one horizontal synchronizing period to the digital color difference signal before the analog conversion, thereby the delay processing is applied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a chroma signal processing circuit for a VTR (video tape recorder), and particularly to delay processing for a digital chroma signal during playback.

[Conventional technology]

Conventionally, a chroma signal processing circuit used during reproduction of a VTR uses a comb filter using a glass delay line.

[Problem that the invention seeks to solve]

Comb filters that use glass delay lines have the drawback of requiring a large number of external components, such as peripheral components, and requiring a large installation area.

Also, when playing in a mode other than normal playback,
After head switching, there is a drawback that color shift occurs due to fluctuations in the time axis of the color subcarrier until APC (phase control) follows up.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a chroma signal processing circuit for a VTR that can reduce the number of parts and easily integrate into an IC.

Means for Solving Problem C] As shown in FIG. 1, the chroma signal processing circuit of the VTR of the present invention samples an analog chroma signal using a sampling signal whose phase is synchronized with the low frequency conversion color subcarrier. An analog-to-digital converter 8 converts the digital chroma signal into a digital chroma signal, and converts the digital chroma signal outputted from the analog-to-digital converter into a digital chroma signal that is delayed by a specific period of time or more by one horizontal synchronization period. It is equipped with a delay adding circuit 22 that adds to the digital chroma signal output from the converter.

[For production]

The chroma signal processing circuit of the VTR of this invention is an analog signal processing circuit.
By adding a digital chroma signal that is delayed by a specific period of one horizontal synchronization period or more to the digital chroma signal output by the digital converter, the delay of the glass delay line etc. can be reduced with respect to the digital chroma signal. Performs delay processing equivalent to means.

In the chroma signal processing circuit of the VTR of the present invention, the delay adding circuit includes, for example, storage means for storing one horizontal synchronization period or more of the digital chroma signal and delaying it by a specific time, and a readout signal of the storage means. If it is configured with an addition means for adding the digital chroma signal on the input side of the storage means, it can be easily integrated into an IC with a simple configuration.

Further, in the chroma signal processing circuit of the VTR of the present invention, the storage means may be capable of repeatedly reading the digital chroma signal stored in advance for one horizontal synchronization period or more when switching the reproduction signal in a specific reproduction mode, for example. , for example, in the noiseless search mode during playback, a specific horizontal synchronization period (6 to 8H) after head switching.
The digital chroma signal for one horizontal synchronization period or more stored immediately before the head switching is repeatedly read out, and the video output can be obtained.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of a chroma signal processing circuit for a VTR according to the present invention.

In FIG. 1, an image stored on a magnetic tape as a storage medium is reproduced by a magnetic head 2, and a chroma signal Sc obtained by this reproduction is filtered through a bandpass filter (BPF).
) 4, it is added to an ACC (automatic chroma control) circuit 6 for automatically adjusting the signal level.

The low frequency converted chroma signal whose level has been adjusted by the ACC circuit 6 is sent to an analog/digital converter (A/D) 8.
In addition, the signal is sampled by a sampling signal (160fH, fH: horizontal synchronization frequency) whose phase is synchronized with the low-frequency conversion color subcarrier, and is converted into a digital low-frequency conversion chroma signal.

The voltage controlled oscillator 10 includes a frequency divider 12 and a phase comparator 1.
4.16, it constitutes a phase locked loop (PLL), and obtains an oscillation output whose phase is synchronized with the low-frequency conversion color subcarrier. That is, the voltage controlled oscillator 100
The oscillation output is converted to the horizontal synchronization frequency f by the frequency divider 12. After being divided into the same frequency as , it is added to the phase comparator 14,
The phase difference with the horizontal synchronizing signal (fH) is detected and added to the phase comparator 16, and the burst gate circuit 1
8 detects the phase difference with the color burst signal extracted from the digital low frequency converted chroma signal from the A/D 8. These detected phase differences are applied to the voltage controlled oscillator 10 as a control voltage for controlling the oscillation frequency, and the oscillation frequency is controlled according to the added value of the side phase differences, and the timing signal obtained by the oscillation output is The phase is synchronized with the horizontal synchronization signal and the color burst signal.

In this embodiment, the digital low-frequency converted chroma signal obtained by the A/D 8 is applied to the demodulation circuit 20 for demodulating the color difference signal, and the digital low-frequency converted chroma signal is converted into R-Y, B- The Y digital color difference signal is demodulated. In this case, a timing signal is applied to the demodulation circuit 20 from the voltage controlled oscillator 10, and digital demodulation processing is performed in accordance with the timing signal.

These digital color difference signals are added to a delay adding circuit 22 that performs predetermined delay processing on the digital low-frequency converted chroma signal, and this delay adding circuit 22 adds signals for at least one horizontal synchronization period to the digital color difference signals before analog conversion. Delay processing is performed by adding a digital color difference signal that is delayed by a specific time.

The output of this delay adding circuit 22 is applied to a modulation circuit 24, and the digital color difference signal after delay processing is sent to a crystal oscillation circuit 24.
6, and a digital chroma signal whose frequency is converted by this modulation is obtained.

In this case, the demodulation circuit 20, the delay addition circuit 22, and the modulation circuit 24 are installed as frequency conversion means for the digital low-frequency conversion chroma signal, and are used for preprocessing to convert the frequency of the digital low-frequency conversion chroma signal. After the demodulation circuit 20 demodulates the color difference signal, which is the necessary information, from the digital low-frequency converted chroma signal to be frequency-converted, the delay addition circuit 22 performs the necessary delay processing on the digital low-frequency converted chroma signal, which is an aspect of the digital low-frequency converted chroma signal. Frequency conversion is performed on the digital low-frequency converted chroma signal by applying the frequency conversion to the digital color difference signal and modulating the digital color difference signal in the modulation circuit 24.

The modulated output of the modulation circuit 24 is applied to a digital-to-analog converter (D/A) 28 and converted into an analog signal. In this case, a timing signal is applied to the D/A 28 from the crystal oscillation circuit 26, and the modulated output of the modulation circuit 24 is converted into an analog signal by the timing signal.

In this case, the chroma signal converted into an analog signal by the D/A 28 is converted into an analog signal by the burst gate circuit 18.
It is applied to the ACC detector 30 along with the color burst signal extracted from the digital low-pass converted chroma signal from D8. Therefore, the ACC detector 30 detects the head value level of the color burst signal, and this detection output is applied to the ACC circuit 6.
The output level of circuit 6 is controlled.

Then, the output of the D/A 28 is passed through the bandpass filter (BPF) 3.
2 to the high frequency amplification section (R) of the TV receiver (not shown).
F) and reproduced by the magnetic head 2, an image corresponding to the chroma signal is obtained.

Further, the killer circuit 34 detects whether the mode is monochrome mode or color mode depending on the presence or absence of the color burst signal applied from the burst gate circuit 18, and controls the D/A 28 to cant the chroma signal according to this detection output.

Therefore, in such a ROMA signal processing circuit, A/
A demodulation circuit 2o demodulates a digital color difference signal from the digital low-frequency converted chroma signal digitally converted in D8, and a delay addition circuit 22 adds a digital color difference signal for one horizontal synchronization period or more to this digital color difference signal, and then This added color difference signal causes the crystal oscillation circuit 26 to
modulates the oscillation output from the
This digital chroma signal is converted into an analog signal by the D/A 28. In this case, the delay processing of the digital low-pass converted chroma signal is performed using a digital color difference signal, but the digital color difference signal is obtained by demodulating the digital low-pass converted chroma signal for frequency conversion, and is essentially It is the same as the digital low-frequency conversion chroma signal. Therefore, delay processing of the chroma signal can be performed using a simple circuit configuration using the digital color difference signal demodulated from the digital low-frequency converted chroma signal, and this processing can be realized only with electronic elements on the IC. Therefore, the processing circuit can be easily integrated into an IC.

FIG. 2 shows a specific example of the configuration of the delay adding circuit 22 shown in FIG.

The delay adding circuit 22 of this embodiment stores the digital color difference signal obtained by the demodulation circuit 20 in a storage element 36 installed on the IC as a storage means, and stores it as a digital low-frequency conversion chroma signal for one horizontal synchronization period or more. The digital color difference signal stored in the storage element 36 and read out with a specific delay time from the storage element 36 and the demodulation circuit 20
The adder 38 adds the digital color difference signals given from the adder 38, and the added output is applied to the modulation circuit 24.

Further, FIG. 3 shows another specific example of the configuration of the delay adding circuit 22 shown in FIG. 1.

The delay adding circuit 22 of this embodiment stores a digital color difference signal as a digital low-frequency conversion chroma signal via a switch circuit 40 in addition to a storage element 42 installed on an IC as a storage means for one horizontal synchronization period or more. A digital color difference signal is stored, and the time period until the APC circuit responds to the jitter immediately after the VTR's special playback head scans interlaced tracks is stored for at least one horizontal synchronization period immediately before inter-track interlacing. The digital color difference signal is repeatedly read out from the storage element 42. In this case, the digital color difference signal read out from the storage element 42 is applied to the modulation circuit 24, and
The data is taken into the storage element 42 again via the switch circuit 40, stored therein, and read out.

〔Effect of the invention〕

As explained above, according to the present invention, delay processing of chroma signals can be easily performed without requiring an external circuit such as a glass delay line, the number of external parts can be reduced, and it can be easily integrated into an IC. For example, one chip of IC
You can configure a chroma signal processing system with

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the chroma signal processing circuit of the VTR of the present invention, and FIG. 2 is a block diagram showing a specific example of the configuration of the delay adding circuit installed in the chroma signal processing circuit of the VTR of the present invention. 3 are block diagrams showing other specific examples of the structure of the delay adding circuit installed in the chroma signal processing circuit of the VTR of the present invention. 8...Analog-digital converter, 20...Demodulation circuit, 22...Delay addition circuit, 36.42...Storage element.

Claims (3)

[Claims] (1) An analog-digital converter that samples an analog chroma signal using a sampling signal whose phase is synchronized with the low-pass conversion color subcarrier and converts it into a digital chroma signal, and a digital chroma signal output from this analog-digital converter. a chroma signal of a VTR, characterized in that the chroma signal of the VTR is characterized by comprising a delay adding circuit that adds a digital chroma signal delayed by a specific time period of one horizontal synchronization period or more to the digital chroma signal outputted from the analog-to-digital converter. processing circuit. (2) The delay adding circuit includes a storage means for storing one horizontal synchronization period or more of the digital chroma signal and delaying it by a specific time, and a readout signal of the storage means and a digital chroma signal on the input side of the storage means. 2. The chroma signal processing circuit for a VTR according to claim 1, further comprising an adding means for adding . (3) In a specific reproduction mode, the storage means is capable of repeatedly reading out digital chroma signals stored in advance for one horizontal synchronization period or more when switching reproduction signals. A chroma signal processing circuit for a VTR described in .