JPS58205391A - Processing circuit of chrominance signal - Google Patents

Abstract

PURPOSE:To stabilize the color forming in using an SECAM signal, by providing a gate circuit switching the mode with an external control signal in an IC and stopping the operation of a phase comparator of the APC system only at the SECAM signal. CONSTITUTION:A signal which turns off a gate circuit 31 at the input of the SECAM signal and turns on the gate circuit 31 at a PAL signal is inputted from a control signal input terminal 32. The gate circuit 31 is turned off at the SECAM signal, the operation of the phase comparison circuit 24 is stopped and a phase comparison control output between a carrier chrominance signal switched at each H and an output of a voltage controlled oscillator 26 in free-running is not outputted. In this case, an output of a band pass filter outputted to a converter 5 is controlled with the phase information provided for a reproducing horizontal synchronizing signal inputted from a terminal 15 only. At the input of non-SECAM signal, the gate circuit 31 is turned on and the phase comparison circuit 24 is operative.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal processing circuit for recording and reproducing color signals of SKCAM color TV signals.

The color signal processing in V'I'RK, which is compatible with the conventional SECAM system, is now compatible with the PAL system (also equipped with a circuit that can also support the DVTRKSECAM system,
Many are used as TRs.

The reason for this is that the reception area for the SIICAM television signal is close to the reception area for the PAL television signal, and this is for the convenience of users who watch broadcasts from both systems. Furthermore, it is possible to view and listen to both types of video and audio tapes. In addition, the difference in signal processing between the PAL system and the SkCAM system in the digital signal processing circuit is due to the ease of circuit configuration, as it exists only in a part of the color signal processing system and not in the luminance signal processing system. Do it.

Figure 111 shows a circuit block diagram showing an example of a color signal processing circuit of a VTR that is compatible with the PAL system and the simple SECAM system.
is a reproduced color signal input terminal, 3 is a first switching switch f (hereinafter abbreviated as sw), 4 is an ACC, S is a first frequency conversion circuit (hereinafter abbreviated as a converter), and 6 is a low-pass filter (hereinafter abbreviated as LPH). ), 7 is the first killer amplifier, 8#
'i Recording color No. 11 output Ruko, 9ri first band pass filter (hereinafter referred to as BPP and f), 1101dSECA discrimination circuit, 11 is second SW, 12 is 2HDL filter,
13 is a second killer amplifier, and 14 is a color signal output terminal during reproduction.

Further, 15 is a horizontal synchronizing pulse input trend, 16 is a first phase comparison circuit (hereinafter abbreviated as PD), 17 is a voltage controlled oscillator C (hereinafter abbreviated as vCO), 18 is a first frequency dividing circuit, and 19 is a 2 frequency divider circuit, 20 is a 4-phase logic circuit, 21 is a second
converter, 22 is the second BPF, 25 is the third SW
, 24 is the second PD, 25 is the fourth SW, 26 is the first voltage-controlled crystal oscillator (hereinafter abbreviated as X-taLVco)
, 27 is a second X-tatVcO 128 is a killer detector, 29 is a head pulse input terminal, and 30 is a burst gate pulse input terminal.

When recording a PAL television signal, each SW is in the position shown, and the carrier frequency from input terminal 1 is fBc (;4
．． A color signal of 43 MHz) is input. This is AC
C4 makes the amplitude constant. Part of this signal is the third 5
Through W23, second PD24 and killer detector 28
is input. In the second PD24, the off-center frequency is f
The phase of the output of the first X-tatvCO of sc and the burst signal in the output signal of ACC4 is compared, and the first X-tatvCO2(S is controlled by the output voltage).

In this way, the first X-talVcO26 and the second PD2
Phase Locked Loo
p) to stabilize power 2-/black and white discrimination by the killer detector 28. On the other hand, the output of the VCO 17 is frequency-divided by A in the first frequency divider circuit 18, further divided by Yoshi frequency in the second frequency divider circuit 19, and the horizontal synchronizing pulse (or equivalent horizontal frequency) is separated from the input Eirin signal. pulse) and the first PDld, and is controlled by this output voltage.

In this way, VCO 17, poison frequency division 18, 19. Since PLI consisting of PD1d is configured, VCO17 is 16Q
1lI11# is set so that it oscillates at fH.

As a precaution, the output frequency of the first frequency dividing circuit 18 is 40f.
It becomes l. 90° which is the output of this first frequency dividing circuit 18
A 40fH signal with a phase shift of 94 phases is input to the four-phase logic circuit 20. In the 4-phase logic circuit 20, in the PAL system, in which high-density recording is performed by a two-head helical scan system without a guard band, a track recorded by one head (the recording track at this time is referred to as CH-1) is used. ) always outputs one of the four phases so that the phase is constant, and the track recorded by the other head (the recording track at this time is CH-2) is 1 phase.
Four-phase signals are switched and output every 1H so that there is a delay of 90'' for every H.The output of this 4-phase logic circuit 20 and the second X-tatVc of the center frequency (sc+-4f)
The second converter 21 multiplies the output obtained by making O27 rerun 7 times, and the sum frequency component is sent to the second BPF.
It is taken out at 22.

Therefore, the frequency of the output of BPF22 is (fsc+(4)
0++ ) fB , ) and Cll-2, a carrier signal whose phase is delayed by 90° every 1H is obtained. This carrier signal and the output of the ACC 4 are multiplied by the first converter 5.

Therefore, when the difference frequency component is extracted using LPFd, when the carrier frequency is (40+i)fg and one phase is CH-2, a color signal delayed every 1H by i/(90'' is obtained).

This frequency offset of ÷fII is necessary in order to make the interference caused by the chrominance signal to the luminance signal noticeable. This signal is sent to the recording amplifier from the output terminal 8, mixed with the luminance signal, and recorded.

Note that in black and white mode, the first killer amplifier 7 is controlled by the output of the killer detector 28 so as not to output a signal from the output terminal 8 so as not to record noise.

During reproduction, each SW3, 25.25 is switched to the opposite position tlK from that shown. The carrier frequency is (40+tone)
At fB, when CH-2, the color signal whose phase is delayed by 900 every 1H is inputted more than 2 times, and the ACC is passed through the first SW5.
4 makes the amplitude constant. On the other hand, since the horizontal synchronizing pulse (or equivalent pulse) separated from the reproduced luminance signal is input from the horizontal synchronizing pulse input signal 15, the VCO
17 still oscillates at 160 fE.

In the 4-phase logic circuit 20, the first frequency dividing circuit 18 is used to delay the phase by 90' for each IH during CH-2, as in the case of recording.
The four-phase output is switched and output. This allows C during recording.
This compensates for the slow phase of H-2. On the other hand, the first
talVcO26 free runs and oscillates at f'sc. The output of this lil X-tat V CO26 and the burst signal in the output signal of the first converter 5 are compared in phase, and the second X-t&tV CO27 is controlled using this output voltage. Therefore, the carrier frequency of the reproduced color signal becomes stable fBQ.

In addition, the first converter circuit 5 and BPF 9 correct the phase delay at CH-2 during recording, and the color signal returned to fBQ is judged by the SECAM discrimination circuit 10 whether or not it is a signal of the SECAM system. , the control signal causes the second 5W11
When it is an SgCAM signal, it is returned to f'sc and the nine-color signal is directly output to the killer amplifier 15. Also, SIi
When the signal is other than the tCAM signal, that is, when it is a PAL signal, it is input to the 2HDL filter 12, the signals around 2H are added together, the crosstalk is removed, and the signal is output to the killer amplifier 13.

The killer amplifier 13 outputs no signal to the output terminal 14 in response to a control signal from the killer detector 28 in order to prevent noise from being added to the reproduced video signal during black and white.

In this way, even when receiving SECAM signals, the color tg is set in 5W11.
The signal processing is the same as when receiving a PAL signal, except that the signal is switched so that it does not pass through the 2HDL filter 12. In the PAL signal, as shown in Figure 2, this is quadrature two-phase modulation in which the R-Y component of the carrier color signal is transmitted with phase inversion for each line. This is because there is a correlation between

By utilizing this fin correlation and using a 2HDL filter, crosstalk from adjacent tracks is removed, achieving high vM degree recording and reproduction.

The SECAM Igi issue transmits the B-Y signal at approximately 4.25 MHz.
The R-Y signal is frequency-modulated into a signal of approximately 4.41 MH2 and is inserted alternately every 1H. This is because there is no accurate correlation between the phases of each fin.

As mentioned above, the signal processing method of the carrier color signal is different for PAL signals and SECAM signals, but in a simple SECAM compatible VTR, the same signal processing as for PAL signals is performed even when SECAM signals are received, so when receiving SECAM signals, simple SEC
When recording and reproducing is performed with an AM compatible VTR, the PD 24 operates only during the burst gate pulse period. However, as mentioned above, the frequency of the carrier color signal of the SgCAM signal differs by about 14 DKHz for each H, so the X-ta 4V of the PD 24 during playback.
The control output to cO27 is different every 1H, X-%atV
The oscillation frequency of CO27' is unstable, and this is transmitted to the reproduced carrier color signal via the converter 21 and BPF 22, making the hue of the reproduced image unstable and making the reproduced screen unsightly. One object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a color signal processing circuit that achieves stable coloring when using S1i:CAM system signals in a VTR compatible with the simple SECAM system.

The present invention provides a gate circuit inside the IC that switches the mode using an external control signal, stops the operation of the APC phase comparator only when the SECAM signal is present, and reduces coloring during the SECAM signal. It is something to do.

A block diagram of one embodiment of the present invention is shown in FIG.

In FIG. 3, 31 is a gate circuit, and 32 is a control signal input terminal.

The operations in blocks 11 to 30 are the same as in FIG. 1 both during recording and reproduction. From the control signal input terminal of 52, S
A signal is input that turns off the gate circuit 51 when the ECAM signal is input, and turns on the gate circuit 31 when the PAL signal is input.

81; At the time of CAM signal, the gate circuit is OFF L.

The operation of the PD 24 is stopped, and the phase comparison control output between the transport color tg which switches every H and the free running X-tatV C026 is not output. At this time, the output of the BPF 22 that is output to the controller 7 and the output 5 is controlled only by the phase information of the reproduced horizontal synchronization signal input from the controller 15. Non-SE
At the time of the CAM signal, the gate circuit operates ONI, and the PD24 operates. Just by providing one gate circuit like this,
Stable recording and reproduction can be performed for both PAL and SECAM systems.

FIG. 4 shows an embodiment of the gate circuit of the present invention.

It is a 55/d2 human-powered AND gate. 30 no (-
The stop gate pulse is a signal that is about 5 μsea high before and after the burst signal period of the carrier color signal, and when the control signal from 32 is high, the gate circuit 51 output goes high and operates the PD 24. sgCAM
At the time of signal, the control signal from 32 is Low, and the output of AN-D gate 35 is Low, stopping the operation of PD 24. At the time of non-SICAM signal, the control signal from 32 is Hl.
At gh, the AND gate 33 output is high only during the burst signal period.
lgh and operates the PD24.

FIG. 5 shows a block diagram of another embodiment using the present invention. 1 to 31 are the same blocks as in FIG. 5. In this embodiment, the control signals in FIG. 5 are obtained from the output of the SECAM discrimination circuit. External input terminal is no longer required,
This has the advantage of reducing the number of elements and reducing costs.

FIG. 6 shows a block diagram of another embodiment using the present invention. 52 is an X-ta1 oscillator that oscillates at a frequency of (fB (H++ fH), 55 is an adder, and 34 is a fifth SW.
%35 is a frequency limiting circuit. The others are Figure 5 and Okaji.

The operation at the time of PAL signal in figure M6 will be explained. During recording, the operation is similar to that shown in FIG. When playing, #! 4 S
W is switched, 26 first X-t and alVCO are re-run 7 times, and this is used as a reference signal for #4. Then, the second PD24 compares the phase of the Jin's rsc.

At this time, the carrier frequency of the reproduced color signal input from the input terminal 2 is (40+7)fn, and the second converter 2
1 is the output frequency of the X-tat oscillator 32, which is (f, .++fB). Let the output frequency of the four-phase logic circuit 20 be f in this ζ.

The output frequency of #I2 BPF22 is (f, .+-)rH
Therefore, the carrier frequency of the output signal of the first BPF 9 is (fac +r, -40fH). Since this frequency is button controlled to be f'sc, fso+f, -40fB=f8o, that is, f, -JO1'.

becomes. In other words, the VCO 17 is controlled to be 160 fH. However, in this case, since the burst signal has a frequency spectrum every 7 fH, a deviation within ÷f8 is allowed in order to pull in correctly.

Therefore, the output of VCO17 is +fB from 16of.
Even if the PD24 of jig2 performs control from a state where X4 = = fB or more, the 160fJIVc will not be retracted correctly, so even when there is no control from the second PD24, VC
Output of O17-1) Do 1IFIl@ with the output of the frequency limiting circuit so as not to deviate by more than fB from E160fji.

The circuit format shown in Figure 6 can also be applied to the four color signal processing circuits.
A more stable colored surface can be obtained by stopping the operation of the second PD 24 when receiving the iICAM signal.

The reason for this is that the sensitivity Iie of the 10th X-talVcO is several H
Since the sensitivity of VCO 17 is as high as several hundred H2@A degrees, the output of PD 24 is H
This is because when the SECAM signal changes from time to time, the reproduced carrier color signal frequency becomes unstable and a stable colored screen cannot be obtained.

In addition, assuming that the center oscillation frequency of the VCO 17 in FIGS. 3, 5, and 6 given in the embodiment of the present invention is 160 fH, 9 is 1
It goes without saying that the frequency does not need to be limited to 60 fH, and may be any frequency that has a certain relationship with the horizontal synchronization frequency.

As explained above, by using the present invention in a VTRK compatible with the simple SECAM system, it is possible to enjoy a stable playback screen without uneven hue when reproducing SECAM signals.
This is extremely effective in improving image quality performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional color signal processing circuit. Fig. 2 is a vector diagram showing the components of the PAL signal, Fig. 3 is a block diagram showing an embodiment of the color signal processing (b) path of the present invention, and Fig. 4 is a gate circuit constituting the present invention. FIG. 5 is a block diagram of another embodiment of the present invention, and FIG. 6 is a block diagram of still another embodiment of the present invention. 10...SffCAM discrimination circuit 11...
...SW 31...Gate circuit 32...Control signal input terminal

Claims (1)

[Claims] An oscillator that oscillates with a color subcarrier fsc, a phase comparator that matches the phase of the output of the oscillator and the burst signal, and a first pulse that operates the phase comparator during the burst signal period. In a chrominance signal processing circuit having an input terminal, a control signal is obtained to stop the operation of the phase comparator only when the SECAM signal is received, and a gate is applied to the first pulse.
A color signal processing circuit characterized in that the operation of the phase comparator is stopped only when a CAM signal is received.