JPS6294023A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To test both circuit sections separately by sending a signal between an analog circuit section and a digital circuit section through a latch circuit inserted between both the circuit sections, and acting the latch circuit as a shift register at the test. CONSTITUTION:Latch circuits 5a-5z constituting a shift register are inserted between the analog circuit sections 2a, 2b and the digital circuit section 3, a signal between both the circuit sections is sent through the latch circuits 5a-5z normally, and the latch circuits 5a-5z are connected in cascade at the test and they are acted like the shift register. As a result, a test pattern is inputted directly to the digital circuit section externally and the signal fed to the analog circuit section is extracted directly externally from the digital circuit section.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to semiconductor integrated circuit technology and to technology that is particularly effective when applied to the configuration of semiconductor integrated circuits in which analog circuits and digital circuits are mixed. The present invention relates to techniques that are effective for use in communication LSFF such as (encoder/decoder) and MODEM (modulation/demodulation circuit).

[Background Art] For example, a digital processing type communication LSI such as MODEM is composed of an analog circuit section such as an A/D conversion circuit or a D/A conversion circuit, and a digital signal processing section in the form of a general-purpose processor. There is. It is expected that the number of LSIs in which analog circuits and digital circuits coexist on the same chip will increase in the future.

However, conventionally, an analog tester that applies an analog signal to the LSI is used to test an analog circuit (LSI), and a digital tester is used to test a digital circuit (LSI).

Therefore, L with a mixture of analog and digital circuits
When an SI is developed, in order to test the LSI using an existing tester, the LSI must be passed through both a digital tester and an analog tester, and the digital and analog circuits must be separated and tested separately. . As a result, a large number of dedicated pins for test signal input/output are required, and the defect detection rate of the digital circuit section is reduced due to the restriction on the number of test pins.

Note that LSIs with a mixture of analog circuits and digital circuits
As an invention related to the test method of
There is No. 11.

[Objective of the Invention] The object of the invention is to improve the detection rate of defects in digital circuits in LSIs in which analog circuits and digital circuits coexist without providing a large number of dedicated pins for testing. Our goal is to provide semiconductor integrated circuit technology.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

That is, a latch circuit capable of forming a shift register is interposed between the analog circuit section and the digital circuit section,
Normally, signals are transmitted between the analog circuit section and the digital circuit section through this latch circuit, and during testing, the above latch circuits are connected in cascade to operate as a shift register, and the test is directly carried out from the outside to the digital circuit section. By making it possible to input patterns and take out signals supplied from the digital circuit section to the analog circuit section directly to the outside, the analog circuit section and the digital circuit section can be tested separately using only a few test-dedicated pins, and the digital circuit section can be tested separately. This achieves the above object of improving the detection rate of defects in circuit sections.

[Example code] FIG. 1 shows a first embodiment of the invention.

In the figure, reference numeral 1 denotes an LSI (Large Scale Integrated Circuit) in which analog circuits 2a, 2b and a digital circuit 3 are formed on one semiconductor chip such as an auxiliary silicon substrate. Furthermore, 4a and 4b are analog signal input/output terminals provided on the LSI (semiconductor chip) 1, and 4c is an input/output terminal for control signals and digital signals to the digital circuit 3.

In this embodiment, the analog circuit 2a is, for example, an A/D! The converter circuit A/D converts the analog signal input to the analog input terminal 4a and supplies it to the digital circuit 3. The digital circuit 3 performs appropriate digital signal processing on the signal supplied from the analog circuit 2a and the signal input from the digital input/output terminal 4b, and the result is (
The digital output signal) is output from the digital input/output terminal 4C to the outside or supplied to the analog circuit 2b.

The analog circuit 2b is composed of, for example, a D/A conversion circuit, and the signal supplied from the digital circuit 3 is D/A converted here and outputted to the outside from an analog output terminal 4b.

The configuration up to this point is the same as the general configuration of a conventional analog/digital mixed LSI. Therefore, in this embodiment, the analog circuit 2a.

2b and the digital circuit 3, there are latch circuits 5a, 5b, 5c, . . . 5x+, which can configure a shift register.
5 y+ 5 z are provided. Normally, signals are transmitted between the analog circuits 2a, 2b and the digital circuit 3 through these latch circuits 5a, 5b.

5c... 5x, 5y, and 5z are used to pass through this.

However, the latch circuits 5a, 5b, 5c...5
x, 5y, and 5z are cascade-connected to each other, and are configured to latch signals from the analog circuit 2a and digital circuit 3 or to operate as a shift register, for example, by a control signal supplied from the outside. . An external terminal 4d is connected to the first latch circuit 5a, and by operating the launch circuit arrays 5a to 5Z as a shift register, the latch circuits 58 to 5Z shift the serial data supplied to the external terminal 4d.
It can be imported into 5Z. Further, an external terminal 4e is connected to the last latch circuit 5Z, so that signals from the analog circuit 2a and the digital circuit 3 can be latched and sequentially output from the shift register terminal 4C to the outside.

FIG. 2 shows an example of the latch circuit J a-5Z.

The latch circuit of this embodiment includes four transmission gates TG1. TG2. TG3. TG4 and 4 pieces (7)
GOMS inverter INV! ,INV,,INVl,I
NV4 and the above transmission game-I-TG, ~
Inverter V1. for forming a complementary gate control signal for TG4. V2, V3.

■It is composed of 4.

Digital signal input terminal i and digital signal output terminal 0
There are transmission gates TG, , CMO between
S inverter INv1. transmission gate TG
When the ztcMOs inverter NV2 is connected and the transmission gates 1 and TG2 are made conductive by the control signals G, G2, the same signal as that supplied to the digital input terminal i is sent to the digital input terminal. It is output from CMOS inverter N
A CMOS inverter INV is connected to the output terminal of V, and the output signal of the CMOS inverter INV is connected to the output terminal of CM
By being fed back to the input terminal of the OS inverter INV2, a latch circuit is configured, and the signal of 荊 is held even if the transmission gate TG2 is turned off.

Further, a transmission gate TG3 controlled by a clock signal φ1 is connected between the shift data input terminal Si and the input terminal (node n□) of the CMOS inverter INV.

Furthermore, the output terminal of the CMOS inverter INV (
node nz) and shift data output terminal S.

In between, there is a transmission gate TG controlled by a clock signal φ2 and a CMOS inverter INv4.
is connected.

Therefore, the above circuit controls the control signals G1°G2 to 1
10 With the transmission gate TG turned off, input the clocks φ1 and φ2 of the same period, which are 180” out of phase with each other, and turn on the TG.
Turn 3 and TG4 on and off. Thereby, the data supplied to the shift data input terminal Si can be taken in one after another in synchronization with the clock φ1, and the data can be outputted from the shift data output terminal So in synchronization with the clock φ2.

Moreover, in the above circuit, the shift data is changed to CM by TG.
, When the data is taken into the OS inverter INV1, the control signal G2 is changed to II I 11 and the transmission gate TG4 is opened, thereby supplying the data to the CMOS inverter INV2 and outputting it from the digital signal output terminal 0. can be done. Similarly, a signal inputted from digital signal input terminal j via 1-transmission gate TG,
By opening the transmission gate TG4 with the tarlock φ2, it is also possible to output the shift data to the shift data output terminal So.

When the circuit shown in FIG. 2 is used as the latch circuits 5a, 5b, 5cm, . . . 5x, 5y, 5Z in FIG. 1, the control signal G supplied to each latch circuit 5a to 52 1 and G2 are both fixed at high level ("1") during normal operation. Then,
Latch circuits 5a, 5b.

The signal output from the analog circuit 2a through 5c is supplied to the digital circuit 3, and the signal output from the digital circuit 3 is supplied as is to the analog circuit 2b through the latch circuit 5x.

On the other hand, if you want to test only the digital circuit 3 using a digital tester when testing an LSI, the latch circuit 5
The control signal G□ supplied to a to 5Z is 110
TT, and the clock signal φ1. While supplying φ2, test data is input to the external terminal 4d in synchronization with the clock φ. Then, the latch circuit arrays 5a to 5z operate as shift registers, and test data is sequentially fetched.

In this state, the digital circuit 3 is operated by applying an appropriate control signal from the digital input/output pin 4c. Furthermore, for the latch circuit that receives the output signal from the digital circuit 3, the control signal G1 is
After taking in the output signal from the digital circuit 3, the clock φ0. I will supply φ2. This results in
The data captured in the latch circuit arrays 58 to 5Z is transferred to terminal 4.
It is possible to serially output the data from C to the outside.

By operating the latch circuits 58 to 5Z as shift registers as described below, the digital circuit 3
can be separated from the analog circuits 2a and 2b and tested independently. Similarly, an appropriate sine wave or the like is input to the analog input terminal 4a, and the output signal A/D converted by the analog circuit 2a is latched by the latch circuits 5a to 5c. φ2 can be supplied, shifted, and outputted to the terminal 4e. In addition, appropriate test data is transferred from the terminal 4d to the latch circuits 5x to 5z by shift operation.
After sending the control signal G2 to i′1 u
A test digital signal is input to the analog circuit 2b, the D/A conversion is performed, and the output is observed. By doing so, it is also possible to test the analog circuits 2a and 2b individually and evaluate their performance.

According to this embodiment, there are two terminals 4d and 4e for serial input/output of test data and a control signal G.
□, G, X and clock φ1. 4 φ2 supply terminals
By simply providing one, the analog circuits 2a, 2b and the digital circuit 3 can be tested independently. However, the control signal G1.supplied to the latch circuits 58-5Z.
G2 and clock φ1. φ2 can also be generated internally by providing a circuit for forming such a signal in the LSI (semiconductor chip) 1. In such a case, in addition to the test data output terminals 4d and 4e, a test mode control pin that supplies a mode switching signal for operating a control signal and a clock forming circuit from the outside during testing. You only need to provide one.

Furthermore, when a circuit as shown in FIG. 2 is used as a latch circuit configuring shift 1 to registers, the signal input to the digital signal input terminal i is latched to the CMOS inverter INV, and then the transmission gate By closing TG2 and supplying clocks φ□ and φ2, data can be shifted and taken out to the outside while the original signal is output from digital signal output terminal 0.

Therefore, the analog circuits 2a and 2J are
) and the digital circuit 3 at the same time to execute comprehensive processing, the signal is sent from the analog circuit 2a to the digital circuit 3, and from the digital circuit 3 to the analog circuit 2.
Latch the signal to b, shift it, and take it out to the outside 1
: Can also be done. This enables dynamic testing of analog and digital mixed LSIs.

FIG. 3 shows the present invention as a digital signal processing method using GOD
An example of application to EC is shown.

Transfer data (digital signals) outputted from a microcomputer or the like is inputted to a digital l10il as an interface circuit from a digital input/output terminal 14c. The digital signal input to the digital l1011 is sent to the latch circuit array 15 that can configure a shift register.
The signal is supplied to the digital signal processing unit 13 via a. The digital signal processing unit 13 performs arithmetic processing (modulation) to convert the digital signal to be transferred into an analog signal in a voice band suitable for a telephone line. The data obtained by the calculation in the digital signal processing section 13 is transferred to the D/D signal via a latch circuit array 15d that can constitute a shift register.
The signal is supplied to the A conversion circuit 12b and subjected to D/A conversion. D/
The analog signal output from the A conversion circuit 12b is waveform-shaped through an analog filter 16b and then output to the analog output terminal 14b.

On the other hand, an analog signal input to the analog input terminal 14a from a telephone line or the like is supplied to the AID conversion circuit 12a through an analog filter 16a and converted into a digital signal. This digital signal is supplied to the digital signal processing unit 13 via the latch circuit array 15d, where arithmetic processing is performed to demodulate the original digital signal, and then the digital signal is sent to the digital input/output terminal 14c via the digital input/output terminal 1011.
Output to.

Digital signal processing unit 1 that performs processing for the above modulation and demodulation
3 is a micro ROM (SD only memory) in which a micro program is stored, for example.

ALU (arithmetic logic unit) and multiplier that perform calculations for modulation and demodulation, data ROM that stores data such as parameters necessary for calculation, various registers and RAM (random access memory) that store data to be calculated and calculation results.
It is configured in a similar manner to a general microprocessor, including memory (memory), etc.

A sequencer 17 is provided to sequentially read microinstructions from a micro ROM in the digital signal processing section 13 and execute sequential control based on control signals supplied from an external device such as a microcomputer. In addition, a reference clock φ is supplied from the outside. A timer 18 is provided to form various timing signals within the digital signal processing section 13 based on the above.

In this embodiment, latch circuit arrays 15b and 15c capable of forming a shift register are also provided between the sequencer 17 and timer 18, which are a type of digital circuit, and the digital signal processing section 13.
and the output signal of the timer 18 can be taken out directly to the outside.

Although not particularly limited, in this embodiment, in order to reduce the number of bins, the latch circuit arrays 15a, 15b, 15c,
15d is a shift data input/output terminal 14d, 14e (S
i, So) are connected in cascade to each other so as to form one shift register. Latch circuit row 1
Control signal G for controlling 5a to 15d to operate as normal gates or shift registers>
r02 or clock φ1. Terminals 21 to 24 are provided so that φ2 can be supplied from the outside. As a result, all internal digital signals passing through the latch circuit arrays 15a to 15d can be taken out from the terminal sO, and testing can be performed by inputting test data directly into the inner part of the LSI from the outside.

In the above embodiment, there is of course a digital l1011 as a digital circuit and a sequencer 17.
Latch circuit arrays 15a to 15c that can also configure a shift register between the timer 18 and the digital signal processing section 13
is provided. Therefore, in addition to separate evaluations of the digital circuit section and analog circuit section, we can further increase the detection rate of defects within the digital circuit section by extracting signals between the digital circuit sections or directly inputting appropriate test signals. can do.

In the above embodiment, four latch circuits ]-5a to 1
The latch circuits 15a to 15d can be connected to operate as a shift register, but if the number of pins is sufficient, it is possible to operate each of the latch circuits 15a to 15d as separate shift registers, or connect the four latch circuits 15a to 15d. Circuits 15a-15
Any two or three of d may be connected to form a 2 or more -J2 shift register.

[Effects] (1) A latch circuit that can configure a shift register is interposed between the analog circuit section and the digital circuit section, and signals are normally transmitted between the analog circuit section and the digital circuit section through this latch circuit. During testing, the above latch circuits are connected in cascade to operate as a shift register, so test patterns can be input directly from the outside to the digital circuit section, and signals supplied from the digital circuit section to the analog circuit section can be input directly to the digital circuit section. By being able to take out the data directly to the outside, it is possible to test the analog circuit section and the digital circuit section separately using only a few test-dedicated pins.
This has the effect of improving the detection rate of defects in the digital circuit section and also allowing independent evaluation of the analog circuit section.

(2) Since a latch circuit that can configure a shift register is interposed between multiple digital circuits in an LSI that is a mixture of analog and digital, the test signal can be input directly into the deep part of the digital circuit. This has the effect of improving the detection rate of defects in the circuit section.

(3) A latch circuit that can configure a shift register is interposed between the analog circuit and the digital circuit, and
When the circuit described in J2 is operated as a shift register, it is configured so that it can latch the original data to be shifted, so it can move the analog circuit and digital circuit simultaneously and transfer data between them. The effect of being able to take out the signals transmitted by the device to the outside is that dynamic testing becomes possible.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example,
In an LSI with a mixture of analog and digital, between digital circuits and analog circuits, and between digital circuits,
Although a latch circuit array capable of forming a shift register is interposed, it is also possible to apply it to an LSI with only digital circuits and no built-in analog circuits.

[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to CODEC, which is the field of application that formed the background of the invention, but this invention is not limited thereto, and is applicable to MODEM and other communication LSIs. Of course, it can also be used for r, SI in general where analog circuits and digital circuits are mixed.

[Brief explanation of drawings]

FIG. 1 shows an analog/digital mixed L according to the present invention.
FIG. 2 is a block diagram showing one embodiment of SI, FIG. 2 is a circuit diagram showing an example of a latch circuit as a gate means that can configure a shift register, and FIG. 3 is a circuit diagram showing an example of a latch circuit as a gate means that can configure a shift register. FIG. 3 is a block diagram showing an example in the case of the above. 1-- ・-Semiconductor chip (LSI), 2a, 12a・
...Analog circuit (A/D converter), 2b, 12b・
...Analog circuit (D/A converter), 3゜13...
・Digital circuit, 4a, 14a...Analog input terminal, 4b, 14b...Analog output terminal, 4c,
14c...Digital input/output terminal, 58~5Z...
...Gate means (latch circuit), 4 e g 4 d
*14e, l4d...Shift data (test data) input/output terminal, ]-5a to 15d...
...Latch circuit row, TG□~T G4...1-transmission gate, INV□~INV,...CM
OS inverter.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which an analog circuit and a digital circuit are formed on the same semiconductor chip, wherein a plurality of shift registers can be configured between the analog circuit and the digital circuit. gate means are provided, and signals are transmitted between the analog circuit and the digital circuit through these gate means, and the first and last of the gate means are connected to an external terminal, and the gate means A semiconductor integrated circuit characterized in that when the means is operated as a shift register, serial data can be input and output from the external terminal. 2. The semiconductor according to claim 1, wherein the digital circuit is divided into a plurality of circuit blocks, and gate means capable of forming a shift register is provided between each of the circuit blocks. integrated circuit. 3. When operated as a shift register, the gate means latches the original data to be shifted and supplies it to the digital circuit or analog circuit, while shifting the data to the gate means at the subsequent stage. A semiconductor integrated circuit according to claim 1 or 2, characterized in that the semiconductor integrated circuit is enabled. 4. Claim 1, characterized in that a signal forming circuit for forming a signal for operating the gate means as a shift register is formed on the same semiconductor substrate.
A semiconductor integrated circuit according to item 1, 2 or 3.