JPS6293244U - - Google Patents
Info
- Publication number
- JPS6293244U JPS6293244U JP17893386U JP17893386U JPS6293244U JP S6293244 U JPS6293244 U JP S6293244U JP 17893386 U JP17893386 U JP 17893386U JP 17893386 U JP17893386 U JP 17893386U JP S6293244 U JPS6293244 U JP S6293244U
- Authority
- JP
- Japan
- Prior art keywords
- audio
- information
- adapter
- memory
- voice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002159 abnormal effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第1図は本考案の一実施例構成、第2図はイン
タフエース制御アダプタの一実施例説明図、第3
図は本考案の一実施形態の例についての説明図を
示す。
図中、1は電子計算機システムの本体系装置、
2は中央処理装置、3はメモリ制御装置、4はメ
モリ、5は障害情報格納エリア、6はインタフエ
ース制御回路、7は保守パネルまたは操作パネル
、8はメモリアクセス装置、9はメモリアクセス
制御部、10は読出し専用メモリ、11は音声記
憶部、12はインタフエース制御アダプタ、13
は音声アダプタ、14はラインアダプタ、15は
多周波受信装置、16は網制御装置、17は押釦
付加入電話機、28は異常状態検出アダプタ、2
9は自動発信回路を表す。
Fig. 1 shows the configuration of an embodiment of the present invention, Fig. 2 is an explanatory diagram of an embodiment of the interface control adapter, and Fig. 3 shows the configuration of an embodiment of the present invention.
The figure shows an explanatory diagram of an example of an embodiment of the present invention. In the figure, 1 is the main system device of the electronic computer system;
2 is a central processing unit, 3 is a memory control device, 4 is a memory, 5 is a failure information storage area, 6 is an interface control circuit, 7 is a maintenance panel or operation panel, 8 is a memory access device, 9 is a memory access control unit , 10 is a read-only memory, 11 is an audio storage section, 12 is an interface control adapter, 13
1 is a voice adapter, 14 is a line adapter, 15 is a multi-frequency receiving device, 16 is a network control device, 17 is a telephone with push button addition, 28 is an abnormal state detection adapter, 2
9 represents an automatic transmission circuit.
Claims (1)
3と、メモリ装置4とを有する電子計算機システ
ムのメモリ情報音声通知装置であつて、 上記メモリ制御装置3を介して上記メモリ装置
4にアクセスするインタフエースをコントロール
するインタフエース制御アダプタ12と、 音声情報を格納してある音声記憶部11と、 該音声記憶部11に格納されている音声情報を
音声に変換し回線に送出する音声アダプタ13と
、 システムに障害が発生し異常状態が検出された
場合に、所定の電話機に対し自動発信制御を行う
自動発信回路29と、 押釦付電話機17から回線を経由して送出され
てくる情報を受信するラインアダプタ14と、 上記自動発信回路29により、上記所定の電話
機に対し、異常状態に関する情報を、上記音声ア
ダプタ13を介して音声により通知すると共に、
上記ラインアダプタ14が受信した情報に従つて
、上記メモリ装置4にアクセスし、該アクセスし
て得られた情報を上記音声アダプタ13を介して
上記押釦付電話機17に音声により通知する制御
手段9と を備えたことを特徴とする電子計算機システムの
メモリ情報音声通知装置。[Claims for Utility Model Registration] A memory information audio notification device for a computer system having at least a central processing unit 2, a memory control device 3, and a memory device 4, An interface control adapter 12 that controls the interface that accesses the device 4; an audio storage unit 11 that stores audio information; and converts the audio information stored in the audio storage unit 11 into audio and sends it to the line. an automatic dialing circuit 29 that automatically controls dialing to a predetermined telephone when a system failure occurs and an abnormal state is detected; The line adapter 14 receives information about the abnormal state, and the automatic call circuit 29 notifies the predetermined telephone of information regarding the abnormal state by voice via the voice adapter 13.
a control means 9 for accessing the memory device 4 in accordance with the information received by the line adapter 14 and notifying the push button telephone 17 of the information obtained through the access by voice via the audio adapter 13; 1. A memory information voice notification device for a computer system, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986178933U JPS6324504Y2 (en) | 1986-11-20 | 1986-11-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986178933U JPS6324504Y2 (en) | 1986-11-20 | 1986-11-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6293244U true JPS6293244U (en) | 1987-06-15 |
JPS6324504Y2 JPS6324504Y2 (en) | 1988-07-05 |
Family
ID=31121532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986178933U Expired JPS6324504Y2 (en) | 1986-11-20 | 1986-11-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6324504Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299009A (en) * | 1976-02-17 | 1977-08-19 | Nec Corp | Automatic voice responding system |
JPS556628A (en) * | 1978-06-29 | 1980-01-18 | Fujitsu Ltd | Fault transfer systen |
-
1986
- 1986-11-20 JP JP1986178933U patent/JPS6324504Y2/ja not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5299009A (en) * | 1976-02-17 | 1977-08-19 | Nec Corp | Automatic voice responding system |
JPS556628A (en) * | 1978-06-29 | 1980-01-18 | Fujitsu Ltd | Fault transfer systen |
Also Published As
Publication number | Publication date |
---|---|
JPS6324504Y2 (en) | 1988-07-05 |
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