JPS6292765A - Driving circuit for gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To shorten a storage time on turn-OFF, by arranging the series circuit of the first DC power source of specified voltage and a diode, and the series circuit of a condenser and the second switch, in parallel with each other or in the like manner, between a gate and a cathode of a gate turn-OFF thyristor (GTO). CONSTITUTION:The driving circuit of a GTO3 is organized by connecting the series circuit of the first semiconductor switch S1, the first DC power source 1 set to be equal to or less than breakdown voltage between a gate and a cathode, and a diode D1, between the gate and the cathode. To the series circuit, the series circuit of a condenser C and the second semiconductor switch S2 is connected in parallel with each other, and to the condenser C, the series circuit of the second DC power source 2 set to be equal to or more than said breakdown voltage and a resistance R is set in parallel with each other. Then, the attenuation factor of gate current ig gets higher as the initial value of the voltage of the condenser C is set to be higher, and this phenomenon can be realized with DC power source voltage V2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drive circuit for a gate turn-off thyristor (hereinafter referred to as GTO thyristor) as a semiconductor device, and particularly relates to an improvement of a turn-off circuit.

C. Prior Art] A GTO thyristor is a self-extinguishing semiconductor device that can extinguish the anode current by flowing a reverse current through its gate. A series circuit consisting of a semiconductor switch S1 and a DC power supply 1 is connected between the gate and cathode of No. 3. In the figure, 1g is the inductance of the wiring.

As shown in FIG. 5, the operation is to close the switch S1 at time t1 and supply current from the DC power supply 1 to the gate. That is, by closing the switch S1, the ten poles of the DC power supply 1 - the cathode of the GTO thyristor 3 - the gate of the GTO thyristor 3 -> the wiring inductorless I
g→Switch S1 - Forms a one-pole closed loop of DC power supply 1 and supplies reverse current to the gate of GTO thyristor 3.

The reason why the gate current iG increases negatively with a certain slope during the period from time t1 to time t2 in FIG. 5 is due to the influence of the wiring inductance Ig in the closed loop. Also, time t
This is because the gate current iG decreases toward zero after 2, and the reverse blocking ability between the gate and the cathode recovers and the impedance increases. In this example, the DC power supply voltage V1 is set lower than the breakdown voltage between the gate and cathode of the GTO thyristor 3.

[Problem that the invention seeks to solve]

However, in FIG. 2, the rate of change (dig/
dt) is -50 to -60A/μ for large capacity GTO.
Although a large value of s or more is required, the circuit shown in FIG. 4 cannot obtain such a large dig/dt.

dig /dt in the circuit of Figure 4 is dig / dt
= V1/Ig. From the above formula, dig/
In order to increase dt, it is possible to increase the DC power supply voltage v1, but if the DC power supply voltage v1 is made higher than the breakdown voltage between the gate and cathode of the GTO thyristor 3, the impedance between the gate and the cathode after time t2 Since the gate current ig does not decrease during the period when the gate current ig is high, gate loss becomes excessive, and a snubber circuit is required to process the energy stored in Ig when switch S1 is opened, making the circuit complicated. , become larger.

If the required di at turn-off of GTO thyristor 3
If g/dt is not obtained, the accumulation time (the time from the time the gate reverse current reaches 10% of its peak value until the anode current decreases to 90% of its value just before turn-off)
becomes long, which impedes high-frequency operation.Furthermore, if dig/dt is significantly small, the GTO thyristor 3 may fail to turn off and be permanently destroyed.

In addition, the turn-off time of the GTO thyristor 3 (the above-mentioned M
The variation in the sum of the reception time and fall time (the time from when the anode current decreases to 90% of the value immediately before turn-off until the value decreases to 10%) tends to decrease as dig/dt increases. It is in. In particular, when connecting GTO thyristors 3 in series and parallel to increase capacity, if there is a large variation in turn-off time, overvoltage may be applied to the GTO thyristors 3, which turn off quickly when connected in series, or when connected in parallel. Sometimes, current concentrates on the GTO thyristor 3, which turns off late.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drive circuit for a gate turn-off thyristor that can eliminate the disadvantages of the conventional example and increase the rate of change dig /dt of the gate reverse current at turn-off.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention includes a first DC power supply and a diode, which are set to be lower than the breakdown voltage between the first switch and the gate and cathode of the gate turn-off thyristor, between the gate and cathode of the gate turn-off thyristor. A series circuit of a capacitor and a second switch are connected in parallel, and the capacitor is connected to a second DC power supply set to a breakdown voltage higher than the breakdown voltage between the gate and cathode of the gate turn-off thyristor, and a resistor. The gist is that series circuits are connected in parallel.

[Effect]

According to the present invention, the rate of decrease in gate current ig is dig /d
t increases as the initial value Tco of the voltage of the capacitor C is set higher. In other words, the second DC power supply voltage ■2
This is achieved by increasing dtg/dt to a value that provides the desired dtg/dt. Further, the initial value Vco of the voltage Vc of the capacitor C at time to is set higher than the breakdown voltage between the gate and the cathode, but after that, the Vc is discharged and set to a voltage lower than the breakdown voltage between the gate and the cathode. After the reverse blocking ability between the gate and cathode of the GTO Sirisk is recovered, the gate current ig decreases to zero, so the gate loss does not become excessive. , a snubber circuit for the second switch is not required.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a gate turn-off thyristor drive circuit according to the present invention. In the figure, 3 is a GTO thyristor, and between its gate and cathode, a first semiconductor switch S1 and a GTO thyristor 3 are connected. A series circuit of a first DC power supply 1 set to a breakdown voltage between the gate and the cathode or less and a diode D1 is connected. In the figure, 1g indicates wiring inductance.

On the other hand, a series circuit consisting of a capacitor C and a second semiconductor switch S2 is connected in parallel to the series circuit, and a second semiconductor switch S2 is connected to the capacitor C in parallel with a breakdown voltage set to be higher than the breakdown voltage between the gate and cathode of the GTO thyristor 3. A DC power supply 2 and a series circuit of a resistor R are connected in parallel.

Note that, in FIG. 1, the description of the gate drive circuit for turning on the GTO thyristor 3 is omitted.

Next, to explain the operation, Fig. 2 is a time chart when there is an anode cut-off current of GTO thyristor 3, and Fig. 3 is a time chart when there is no anode cut-off current of GTO thyristor 3. t=Q
The turn-off operation will be described below under the condition that Vco>VGR, where the initial value of the voltage at is Vco and the breakdown voltage between the gate and cathode of the GTO thyristor 3 is VGR.

1. When there is anode cutoff current of GTO Cyrisk (
(See Figure 2) (1) Period 1 (Time tO to t1) From the time to when switches S L and S 2 are closed, GT
Period 1 is defined as the period up to time t1 when the anode current of the o-thyristor decreases to almost zero, the reverse blocking ability between the gate and the cathode is recovered, and the gate current ig begins to decrease toward zero. Further, assume that the voltage Vc of the capacitor C becomes equal to the first DC power supply voltage ■1 at time t1.

During this period, when switches S1 and S2 are closed at time to, a series resonant circuit (loop shown by the broken line in Fig. 2) is formed between the capacitor C charged with the second DC power supply voltage v2 and the inductance Ig. An oscillating circuit flows to the gate of GTO thyristor 3.

The gate current ig during this period is It is expressed as The rate of change of this current is can be achieved by increasing Vco.

During this period, since Vc > Vl, the diode D1 is in a reverse bias state, and therefore no current is supplied from the first DC power supply 1.

(2) Period 2 (Times t1 to 12) Period 2 is defined as the period from time t1 at the end of period 1 to time t2 when the gate current of the GTO thyristor 3 decreases to zero.

At time t1, the voltage Vc of the capacitor C drops to the first DC power supply voltage ■1, so the diode D1 becomes conductive.
(The diode is assumed to be an ideal diode.) Subsequently, the voltage Vc of the capacitor C during this period is clamped to the first DC power supply voltage V1. Since Vl<VGR is set, the gate voltage g during this period decreases.

(3) Period 3 (time t2 to ti) Period 3 is defined as the period from time t2 at the end of period 2 to time t3 when switch S2 is turned off.

During this period, the gate current ig is zero, and the first DC power supply voltage v1 is applied as a reverse voltage between the gate and the cathode. Also, the voltage Vc of the capacitor C is
Similarly, it is clamped to the first DC power supply voltage (1).

(4) Period 4 (times t3 to 1+) Period 4 is defined as the period from time t3 at the end of period 3 to time t4 when the voltage Vc of capacitor C is charged up to the second DC power supply voltage V2.

Since the switch S2 is opened at time t3, the capacitor C is charged from the second DC power supply 2 through the resistor R to the second DC power supply voltage 2 during this period.

Between the gate and cathode during this period, as in period 3,
The first DC power supply voltage v1 is applied as a reverse voltage.

2. When there is no anode cutoff current of GTO Cyrisk (
(See Figure 3) This will be explained as Vco-2/VGR-Vt.

(1) Period 1 (time to-tl) Switch S1. Period 1 is defined as a period from time to when S2 is closed and gate current ig starts flowing to time t1 when gate current ig reaches its peak value.

During this period, when the switch S□132 is closed at time to, similar to when there is an anode cutoff current of the GTO Sirisk, the capacitor C charged to Vco (=second DC power supply voltage V2) and the inductance Ig A series resonant circuit is formed and an oscillating current flows through the gate.

At this time, the voltage between the gate and cathode of the GTO thyristor 3 is at its breakdown voltage VGR, so the gate current i
g becomes the following formula.

ig=-(Vco-VGR)-Sin
ωtg h=r during this period Voltage Vc of capacitor C at time t1
becomes Vc=VGR.

(2) Period 2 (time 1 to t2) Period 2 is defined as the period from time t1 at the end of period 1 to time t2 when the gate current of GTO thyristor 3 decreases to zero.

During this period, the oscillating current of the period 1 continues to flow, and the current decreases to zero.

At the end time t2 of this period, the voltage Vc of the capacitor C is: Vc=V, become.

(3) Period 3 (Time t2 to t3) Period 3 is defined as the period from time t2 at which period 2 ends to time t3 when switch S2 is turned off.

The gate current during this period is zero, and the first DC power supply voltage 1 is applied as a reverse voltage between the gate and the cathode. Further, the voltage Vc of the capacitor C is clamped to the first DC power supply voltage 1.

(4) Period 3 (Time t3-1.) This is the same as Period 4 when there is an anode cutoff current of the GTO Cyrisk, so the explanation will be omitted.

〔Effect of the invention〕

As described above, the gate turn-off thyristor drive circuit of the present invention can increase the current change rate (d ig / dt) of the current supplied to the gate at the time of turn-off of the thyristor. Accumulation time can be shortened, high frequency operation is possible, and destruction of the GTO sirisk due to turn-off failure can be prevented. In addition, when connected in series and parallel, by increasing dig/dt, variations in turn-off time can be reduced, allowing for miniaturization of anode reactors and snubber circuits.
This makes it possible to relax the element selection conditions.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the gate turn-off thyristor drive circuit of the present invention, Fig. 2 is an operating waveform diagram when there is an anode cutoff current of GTO Thyrisk, and Fig. 3 is a diagram when there is no anode cutoff current. FIG. 4 is a circuit diagram showing a conventional example, and FIG. 5 is an operation waveform diagram of the circuit shown in FIG. 1... First DC power supply 2... Second DC power supply 3.
...GTO thyristor Sl...first switch S2...first switch 1g...wiring inductance C...capacitor R...resistance D1...diode

Claims (1)

[Claims] Between the gate and cathode of the gate turn-off thyristor,
A series circuit of a first DC power supply and a diode, which is set to a breakdown voltage below the breakdown voltage between the first switch and the gate and cathode of the gate turn-off thyristor, and a series circuit of a capacitor and a second switch are connected in parallel. . A drive circuit for a gate turn-off thyristor, characterized in that the capacitor is connected in parallel with a series circuit of a resistor and a second DC power supply set to be higher than the breakdown voltage between the gate and cathode of the gate turn-off thyristor.