JP2000184693A - Driving circuit of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the consumption energy of a power supply, and a loss being generated in each switch. SOLUTION: A driving circuit is equipped with an on-high-gate circuit consisting of a switch 12b for on-high-gate that is opened and closed in synchronization with an on-high-gate signal, a first switch 19, and a capacitor parallel circuit 33. In the capacitor parallel circuit 33, a first series circuit 31 consisting of a first capacitor 8 and a resistor 10 is connected in parallel with a second series circuit 32 consisting of a second capacitor 9 and a second reactor 11d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, for example, a gate turn-off thyristor (hereinafter abbreviated as GTO).
And a drive circuit for controlling on / off of the driving circuit.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a circuit diagram showing a driving circuit (gate circuit) of a conventional semiconductor element, for example, a GTO disclosed in Japanese Patent Application Laid-Open Publication No. H11-209,036. In the figure, 1 is a GTO, G is a gate electrode, and K is a cathode electrode. Reference numeral 3 denotes an on-gate power supply, and reference numeral 3a denotes an on-gate power supply capacitor. 2 is a chopper circuit,
It comprises a chopper switch 14 for switching the on-gate power supply 3, current detecting means 16 for detecting an output current of the chopper circuit 2, and a freewheeling diode 15. Reference numeral 11 denotes a reactor, which includes a primary winding 11a and a secondary winding 11b. 8 is the first capacitor, 9 is the second capacitor
Is a resistor, and 10 is a resistor. An on-gate switch 12 supplies an output current of the chopper circuit 2 and the first capacitor 8 to the GTO 1 as an on-gate current. Reference numerals 6 and 17 denote first and third diodes for charging the first capacitor 8, and reference numerals 7 and 18 denote the second capacitor 9.
, And second and fourth diodes for charging. An off-gate switch 13 supplies an off-gate current to the GTO 1. Reference numeral 4 denotes an off-gate power supply, and reference numeral 4a denotes an off-gate power supply capacitor. 19 is each capacitor 8, 9
Is a first switch connected between the common connection portion X of the capacitors 8 and 9 and the zero potential, and 20 is a second switch connected between the common connection portion X of each of the capacitors 8 and 9 and the negative potential.

Next, the operation will be described. The chopper circuit 2 that supplies the on-gate current in combination with the on-gate power supply 3 has a constant current function, detects the gate current Ig by the current detection unit 16, and adjusts the conduction ratio of the chopper switch 14 to adjust the on-gate current. Keep the value constant. The free-wheeling diode 15 conducts when the chopper switch 14 is off, and functions to make the gate current continuous via the reactor 11. On-gate switch 12
Is off, the GTO
1 is supplied with an off-gate current. Turning on / off the on-gate switch 12 will be described with reference to the operation waveform diagram shown in FIG. Before time t1, the on-gate switch 12 and the first switch 19 are off, the second switch 20 and the off-gate switch 1
3 is on, the common connection portion X of the first and second capacitors 8 and 9 has a negative potential, and the third and first diodes 1 and 2 have a negative potential.
The first capacitor 8 is charged through 7, 7 and the second capacitor 9 through the fourth diode 18 to the polarity shown. At time t1, the on-gate switch 12
Is turned on, the gate current Ig flows as the sum of the discharge current Ic of the first capacitor 8 and the oscillating current Icc of the second capacitor 9 and the secondary winding 11b of the reactor 11.

At time t2, the voltage of the second capacitor 9 decreases, and the voltage generated in the primary winding 11a of the reactor 11 (the reverse polarity of the power supply occurs at a turn ratio of 1: n) changes to the on-gate power supply 3. , The current of the secondary winding 11 b of the reactor 11 is transferred to the primary winding of the reactor 11. Assuming that the turn ratio of the primary and secondary windings 11a and 11b of the reactor 11 is 8: 1, the output current Ich of the chopper circuit 2 becomes Ich at time t2.
= Icc / 8 and begins to flow. The current flowing between t1 and t2a is expressed as an on-high gate current. The current flowing between t2 and t3 is expressed as an on-state current. In practice, it is desirable to determine the turns ratio of the reactor 11 such that the initial value of the primary winding 11a of the reactor matches the constant current control value of the chopper circuit 2.
After time t2, the gate current Ig flows as a substantially constant current due to the constant current control function of the chopper circuit 2.
At time t3, the on-gate switch 12 is turned off and the off-gate switch 13 is turned on, so that a negative off-gate current as shown is supplied to the GTO1. At the same time, when the first switch 19 is turned off and the second switch 20 is turned on, the common connection portion X of the first and second capacitors 8 and 9 has a negative potential, and the third and first diodes 17 , 6 through the first capacitor 8
Further, the second capacitor 9 is connected through the fourth diode 18.
Are instantaneously charged to the respective off-gate power supply voltages. That is, the first capacitor 8 and the second capacitor 9 are instantaneously greatly charged when the off-gate current is supplied. Ich does not flow after time t4.

[0005]

The conventional driving circuit for a semiconductor device is constructed as described above. In the circuit shown in FIG. 22, when the on-gate switch 12 is turned on, the gate current Ig is reduced by the first capacitor 8. It flows with the sum of the discharge current Ic and the oscillating current Icc generated by the second capacitor 9 and the secondary winding 11b of the reactor 11. The current Ic2 by the second capacitor 9 and the secondary winding 11b of the reactor 11 is uncontrolled, and the current after the peak value of Ic2, that is, t2a
The portion of the current that exceeds the ON steady-state current value (the shaded portion of Ig in FIG. 23) is unnecessary current for turning on the GTO, and leads to the loss generated in each switch. In addition, there is a problem that the second capacitor 9 needs to be charged for this loss in order to flow a current after the peak current.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. An on-high gate current specified by a simple circuit is supplied for a specified time to reduce the energy consumption of an on-high gate power supply. It is another object of the present invention to provide a driving circuit for a semiconductor device which can reduce a loss generated in each switch. Also, an on-high gate signal is created in the drive circuit of the semiconductor element,
It is an object of the present invention to reduce the energy consumption of an on-high gate power supply and the loss generated in each switch. In addition, an on-high gate signal is generated in the drive circuit of the semiconductor element, an error of the on-high gate current due to a change or an error of a circuit constant of the drive circuit of the semiconductor element is corrected, and a specified amount of current and time are supplied to allow an on-high gate It is an object of the present invention to reduce energy consumption of a power supply and reduce a loss generated in each switch.

[0007]

According to a first aspect of the present invention, there is provided a drive circuit for a semiconductor device, wherein an on-high gate circuit switches on and off in synchronization with an on-high gate signal, and a capacitor parallel circuit for supplying an on-high gate current. And a first switch that opens and closes in synchronization with the on-high gate signal. The capacitor parallel circuit includes a first series circuit in which a first capacitor and a resistor are connected in series, and a second capacitor. And a second series circuit composed of a series connection of a power supply and a reactor, and one of a gate and an on-high gate switch, the other of the on-high gate switch and a resistance of a capacitor parallel circuit, a reactor side. The first and second capacitor sides of the capacitor parallel circuit and one of the first switches, and the other of the first switch and the zero potential portion. The first and second capacitors are connected to each other and have first to third diodes for charging the first and second capacitors. The zero potential portion and the anodes of the first and second diodes, the first capacitor and the resistor are connected to each other. The connection point and the cathode of the first diode, the connection point between the second capacitor and the reactor and the cathode of the second diode, the connection point between the first and second capacitors and the first switch, and the connection point of the third diode The anode and the gate are connected to the cathode of the third diode, respectively.

According to a second aspect of the present invention, there is provided a driving circuit for a semiconductor element,
In the first aspect, a bypass diode is provided in parallel with the resistor of the first series circuit, and the anode of the bypass diode is connected to the reactor and the cathode of the bypass diode is connected to the first capacitor. According to a third aspect of the present invention, in the drive circuit for a semiconductor element according to the first aspect, a second switch that opens and closes in synchronization with a signal after an on-high gate is connected in parallel with the resistor of the first series circuit. According to a fourth aspect of the present invention, in the drive circuit for a semiconductor device, the on-high gate circuit opens and closes in synchronization with the on-high gate signal, a capacitor parallel circuit that supplies an on-high gate current, and the on-high gate signal. 1st to open and close
The capacitor parallel circuit includes a first series circuit formed by connecting a first capacitor and a resistor in series, and a second capacitor and a primary winding of a two-winding reactor. A second series circuit connected in series is configured to be connected in parallel, and one of the gate and the on-high gate switch, the other of the on-high gate switch and the resistance of the capacitor parallel circuit, the reactor side, the capacitor parallel circuit Of the first and second capacitors and one of the first switches, and the other of the first switch and the zero potential portion, respectively, and for charging the first and second capacitors and the on-gate power supply capacitor. A first diode, a fourth diode, a zero potential portion, anodes of first and second diodes, a connection point between a first capacitor and a resistor, and a first node.
The cathode of the diode, the connection point between the second capacitor and the reactor and the cathode of the second diode, the connection point between the first and second capacitors and the first switch, the anode, the gate and the The secondary winding connected to the cathode of the diode of No. 3, the primary winding of the reactor, and the fourth
And the on-gate power supply capacitor connected to the cathode of the fourth diode. According to a fifth aspect of the present invention, there is provided a drive circuit for a semiconductor element according to any one of the first to fourth aspects, wherein an on-high gate signal is externally supplied to the on-high gate circuit.

According to a sixth aspect of the present invention, there is provided a driving circuit for a semiconductor element,
5. A voltage detecting means for detecting a voltage of a second capacitor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, and a result of the comparing means being included in an on-state gate signal. An on-high gate signal generating means having a holding means for holding is provided. According to a seventh aspect of the present invention, there is provided a drive circuit for a semiconductor device according to any one of the first to third aspects, wherein the voltage detector detects a voltage of the reactor, a comparator compares an output of the voltage detector with a reference voltage, and a comparator. An on-high gate signal generating means having a holding means for holding the result of the means during the on-state gate signal is provided. The drive circuit for a semiconductor element according to claim 8 is a circuit according to claim 4, wherein the voltage detection means detects the voltage of the primary winding of the reactor, the comparison means compares the output of the voltage detection means with a reference voltage, and the comparison means. An on-high gate signal generating means having a holding means for holding the result during the on-state gate signal is provided.

According to a ninth aspect of the present invention, there is provided a driving circuit for a semiconductor element,
A voltage detecting means for detecting the voltage of the second capacitor, a comparing means for comparing the output of the voltage detecting means with a reference voltage, and a result of the comparing means being held in the on-state gate signal. And an on-high gate signal generating means having an OR means for performing a logical OR of an output from the holding means and a reference time signal. According to a tenth aspect of the present invention, there is provided a drive circuit for a semiconductor device according to any one of the first to third aspects, wherein: a voltage detecting means for detecting a voltage of the reactor; a comparing means for comparing an output of the voltage detecting means with a reference voltage; An on-high gate signal generating means having holding means for holding the result of the means during the ON steady gate signal, and OR means for performing a logical OR of an output from the holding means and a reference time signal. The drive circuit of a semiconductor device according to claim 11 is the drive circuit according to claim 4, wherein the voltage detector detects a voltage of the primary winding of the reactor, a comparator that compares an output of the voltage detector with a reference voltage, and a comparator. An on-high gate signal generating means having a holding means for holding the result during the on-state gate signal and an OR means for performing a logical OR of an output from the holding means and a reference time signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a circuit diagram showing a driving circuit for a semiconductor device according to a first embodiment of the present invention. In the drawing, reference numeral 1 denotes a semiconductor device GTO.
G is a gate electrode and K is a cathode electrode. 3 is an on-gate power supply, 3a is an on-gate power supply capacitor connected in parallel with the on-gate power supply 3 to suppress voltage fluctuation,
2 is a chopper circuit, 14 is a chopper switch for switching the on-gate power supply 3, 16 is current detection means, 1
Reference numeral 5 denotes a reflux diode, which is a chopper switch 1
4. The chopper circuit 2 is composed of the current detecting means 16 and the freewheeling diode 15. Reference numeral 11c denotes a first reactor for making the on-state gate current constant, and 12a denotes an on-state gate switch for controlling the on-state current. The on-gate power supply 3 and the on-gate power supply capacitor 3
a, a chopper circuit 2, a first reactor 11c, and an on-state gate switch 12a constitute an on-state gate circuit, which has a constant current control function and supplies a constant on-state gate current to the gate G of the GTO1. It has become.

8 is a first capacitor, 10 is a resistor, 9 is a second capacitor, 11d is a second reactor,
A first capacitor 8 and a resistor 10 are connected in series to form a first series circuit 31 and a second capacitor 9
And the second reactor 11d are connected in series to form a second series circuit 32, and the first series circuit 31 and the second series circuit 32 are connected in parallel to send an on-high gate current to the gate G. This constitutes a capacitor parallel circuit 33 for supplying. Reference numerals 12b and 19 denote an on-high gate switch and a first switch which open and close in synchronization with the on-high gate signal. The gate G of the GTO 1 and the on-high gate switch 1
2b, the other of the on-high gate switch 12, the resistor 10 of the capacitor parallel circuit 33, and the second reactor 1
1d side, one of the first and second capacitors 8 and 9 of the capacitor parallel circuit 33 and one of the first switches 19, and the first
, And the other end of the switch 19 is connected to the zero potential portion E.

Reference numeral 17 denotes a first diode for charging the first capacitor 8, 18 denotes a second diode for charging the second capacitor 9, and 21 denotes a first diode for charging the first and second capacitors 8 and 9. A third diode for charging includes a zero potential portion E, anodes of the first and second diodes 8 and 9, and a first diode.
The connection point between the capacitor 8 and the resistor 10 and the cathode of the first diode 8, the connection point between the second capacitor 9 and the second reactor 11d and the cathode of the second diode 9,
A connection point between the first and second capacitors 8 and 9 and the first switch 19, an anode of the third diode 21, and G
The gate G of TO1 and the cathode of the third diode 21 are connected respectively. 4 is an off-gate power supply, 4a is an off-gate power supply capacitor connected in parallel with the off-gate power supply 4 to suppress voltage fluctuation, 13 is an off-gate switch, and is an off-gate power supply 4, an off-gate capacitor 4a and an off-gate switch 13; An off-gate circuit that controls the supply of the off-gate current to the circuit is configured.

Next, the operation of the present embodiment will be described with reference to the waveform diagram of FIG. FIG. 2A shows an ON steady gate signal. During this ON period, the ON steady gate switch 12a is turned on. (B) is an on-high gate signal. During this on-period, a large gate current flows as an on-high gate current.
And the on-high gate switch 12b is turned on. Note that the on-state gate signal and the on-high gate signal are externally applied in this embodiment. An off signal (not shown) that turns off when the on-state gate signal is on and turns on when the on-state gate signal is off is also provided. (C) and (d) are the charging and discharging currents of the first and second capacitors 8 and 9, (e) are the voltages of the first and second capacitors 8 and 9, and Ec8 is the voltage of the first capacitor 8. , Ec9 indicate the voltage of the second capacitor 9. (F) is the current Ich of the chopper circuit 2, (g) is the gate current Ig, and the horizontal axis t is time.

Before time t1, the ON steady gate switch 12a, the ON high gate switch 12b and the first
Switch 19 is turned off, and the first and second capacitors 8 and 9 are charged to the polarity shown in FIG. 1 through the off-gate switch 13 and the first diode 17 and the second diode 18. At time t1, the on-high gate switch 12b and the first switch 19 are turned on in synchronization with the on-high gate signal, and the on-high gate current starts to discharge the first capacitor 8 through the resistor 10 first. If the inductance due to the wiring is ignored, the current from the first capacitor 8 starts flowing at the initial peak of Ec8s / r, where the charging voltage of the first capacitor 8 is Ec8s and the resistance value is r. The second capacitor 9 also outputs the second capacitor at time t1.
Assuming that the charging voltage of the capacitor 9 is Ec9s and the inductance of the second reactor 11d is L11d, Ec9s / L11
It begins to flow as a current with an initial slope of d. By the time t2a, the voltage of the first capacitor 8 decreases due to the discharge and the current flowing through the resistor 10 decreases, but the peak current of the oscillating current by the second capacitor 9 and the second reactor 11d is changed to the time t2a. If adjusted, the gate current Ig
Can flow as a substantially square wave as shown in the figure.

At time t2a, on-high gate switch 12
When b and the first switch 19 are turned off, the current of the second reactor 11d, which has flowed most of the on-high gate current until time t2a, is diverted to the resistor 10, so that the on-high gate current is cut off. 2 reactors 11
The commutation current becomes an oscillating current and attenuates in the series circuit of d, the resistor 10, the first and second capacitors 8, 9. Time t
Since the on-high gate current is cut off at 2a, the gate current of GTO1 is only the absolutely necessary amount of the on-state gate current. After time t2a, the gate current Ig changes to the chopper circuit 2
The constant current control function described above causes a substantially constant current to flow. At time t3, the ON steady gate switch 12
By turning off a and turning on the off-gate switch 13, a negative off-gate current as shown in (g) is supplied to the GTO1. At the same time, the common connection portion X of the first and second capacitors 8 and 9 has a negative potential, so that the first capacitor 8 is connected to the first diode 17 and the third diode 21 and is connected to the second diode 18 and the second diode 18. 3, the second capacitor 9 is instantaneously charged to the off-gate power supply voltage. Ich after time t3
Does not flow.

As described above, the on-high gate current flows for the specified time, and thereafter becomes a constant on-state gate current, so that unnecessary current does not flow. Therefore, the energy consumption of the power supply is reduced, the loss of each switch (for example, the on-high gate switch 12d and the like) using a semiconductor element such as an FET is reduced, and the commutated current flows as an oscillating current. The off signal turns on at G
When the turning-off operation of the TO1 is started, since the voltage at which the oscillating current flows is smaller than the off-gate power supply voltage, the energy of the oscillating current is recovered as the charging energy of the first and second capacitors 8 and 9 for flowing the on-high gate current. As a result, the energy of the charging current for the capacitors 8 and 9 can also be reduced.

Embodiment 2 FIG. FIG. 3 is a circuit diagram showing a drive circuit of a semiconductor element according to a second embodiment of the present invention. In the figure, reference numeral 22 denotes a bypass diode provided in parallel with resistor 10, and the anode is connected to second reactor 11.
While connected to the d side, the cathode is connected to the first capacitor 8 side. The rest is the same as the first embodiment shown in FIG.

Next, the operation will be described with reference to the waveform diagram shown in FIG. Before t2a, the operation is the same as that of the first embodiment, and the description is omitted. When the on-high gate switch 12b and the first switch 19 are turned off at time t2a, the current of the second reactor 11d, which has flowed most of the on-high gate current until time t2a, is diverted to the bypass diode 22, and the on-high gate is turned off. The current is cut off, the commutation current becomes a resonance current in one series circuit of the second reactor 11d, the bypass diode 22, and one of the first and second capacitors 8, 9, and the ON voltage of the bypass diode 22 is supplied to the resistor 10. Only the current due to the voltage of VF flows, and the resistance loss during this period is determined by the on-voltage V
If F ≒ 0, there is no loss. Also, a commutation current flows in the opposite direction in the other series circuit of the second reactor 11d, the resistor 10, the first and second capacitors 8, 9, and becomes an oscillating current and attenuates. The attenuation is slower than in the first embodiment, and the oscillating current continues for a long time. At time t2a, the on-high gate current is cut off, so that the GTO gate current is only the absolutely necessary amount of the on-state gate current. Hereinafter, it operates similarly to the case of Embodiment 1.

From the above, the loss of each switch is reduced because the on-high gate current flows for the specified time, and the commutated current flows as the oscillating current for a long time, during which the off signal is turned on. When the GTO is turned off, the energy of the oscillating current is recovered as the charging energy of the first and second capacitors 8 and 9 to reduce the energy of the charging current of the first and second capacitors 8 and 9. be able to.

Embodiment 3 FIG. 5 is a circuit diagram showing a drive circuit of a semiconductor device according to the third embodiment of the present invention. In the figure, reference numeral 23 denotes a second switch connected in parallel with resistor 10, which is synchronized with a signal after on-high gate. It opens and closes. Here, the post-on-high gate signal means a signal that is the reverse of the on-high gate signal during the period when the on-steady gate signal is on, that is, a signal that turns off when the on-high gate signal is on and turns on when the on-high gate signal is off. Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

Next, the operation will be described with reference to the waveform diagram shown in FIG. (A) to (g) of FIG.
(A) to (g). FIG. 6H shows a signal after the on-high gate, which indicates the on-period of the second switch 23. Before t2a, the operation is the same as that of the first embodiment, and the description is omitted. When the on-high gate switch 12b and the first switch 19 are turned off at time t2a, time t2a
Up to now, the current of the second reactor 11d, which has flowed most of the on-high gate current, is diverted to the second switch 23 which operates in synchronization with the signal after the on-high gate, and the on-high gate current is cut off. The commutation current becomes a resonance current in the series circuit without the damping element of 11d, the second switch 23, and the first and second capacitors 8, 9. At time t2a, the on-high gate current is cut off,
One gate current is only the absolutely necessary amount of the on-state gate current. Hereinafter, it operates similarly to the case of Embodiment 1.

As described above, the loss of each switch is reduced because the on-high gate current flows for the specified time, and the commutated current that can flow for a long time oscillates until the off signal is input. When the GTO 1 is turned off, the energy of the oscillating current is recovered as the charging energy of the first and second capacitors 8 and 9 so that the first and second capacitors 8 and 9 are charged. The energy of the current can be reduced.

Embodiment 4 FIG. 7 is a circuit diagram showing a drive circuit of a semiconductor device according to a fourth embodiment of the present invention. In the figure, reference numeral 24 denotes a two-winding second reactor, which includes a primary winding 24a and a secondary winding 24a. 24b,
The secondary winding 24b has n times the number of turns of the primary winding 24a. Reference numeral 25 denotes a fourth diode for charging the on-gate power supply capacitor. Second reactor 2
4, the primary and secondary windings 24a and 24b are connected to each other, from which a tap Y is drawn. At both ends of the second reactor 24, the primary winding 24a side is connected to the second capacitor 9, and the secondary winding 24b side is connected to the fourth diode 25.
And the fourth diode 2
The cathode of 5 is connected to the on-gate power supply capacitor 3a. The second series circuit 3 is connected to the second capacitor 9 and the primary winding 24a of the second reactor 24 in series.
2. Then, tap Y is connected to first series circuit 3
1 connected to the resistor 10 side, the first and second series circuits 31 and 32 are connected in parallel to form the capacitor parallel circuit 3.
3. Other configurations are the same as those in the first embodiment, and a description thereof will be omitted.

Next, the operation of this embodiment will be described with reference to FIG. (A) of FIG.
(G) respectively correspond to (a) to (g) of FIG. FIG. 8 (i) shows the voltage of the second reactor 24, E24
a indicates the voltage of the primary winding 24a, and nE24a which is n times the voltage of the primary winding 24a indicates the voltage of the secondary winding 24b. Before t2a, the operation is the same as that of the first embodiment, and the description is omitted. However, the second in FIG.
Instead of the action of the inductance of the reactor 11d, the inductance of the primary winding 24a of the second reactor 24 in FIG.

At time t2a, the on-high gate switch 12
When b and the first switch 19 are turned off, the voltage of E24a is generated in the primary winding 24a by the energy of the current flowing through the primary winding 24a of the second reactor 24,
A voltage of nE24a is generated in the secondary winding 24b having a turns ratio n times that of the primary winding 24a. When the number of turns of the secondary winding 24b is set so that this voltage is higher than that of the on-gate power supply 3, energy is regenerated to the on-gate power supply capacitor 3a by the fourth diode 25. At time t2a, the on-high gate current is cut off, so that the GTO gate current is only the absolutely necessary amount of the on-state gate current. Hereinafter, it operates similarly to the case of Embodiment 1. The primary and secondary windings 2 of the second reactor 24
The connection method of 4a and 24b may be other than that shown in FIG. 7, for example, the connection shown in FIG.

As described above, the loss of each switch is reduced because the on-high gate current flows for the specified time, and the energy of the primary winding 24a is directly transferred from the secondary winding 24b of the reactor 24 to the on-gate power supply. Since the power is regenerated, power energy can be reduced.

Embodiment 5 This embodiment is used in combination with the first embodiment. In the first embodiment, while the on-high gate signal is externally applied,
Here, an on-high gate signal is generated internally. The generation of the on-high gate signal will be described below, but the other parts are the same as in the first embodiment, and a description thereof will be omitted. FIG. 10 is a circuit diagram showing an on-high gate signal generating means according to the fifth embodiment, where D is the output voltage of the voltage detecting means L for detecting the voltage of the second capacitor 9 shown in FIG. The output A is Lo level when the output of the voltage detecting means L is lower than the reference voltage, and Hi level when the output is higher than the reference voltage. However, the reference voltage is a small positive value set in advance. B is a trigger means for performing the operation of the set / reset flip-flop. When the output A of the comparison means D is at the Lo level, the trigger is made to the Lo level while the ON steady gate signal is on, and at the input edge of the off signal. It is designed to reset. C is its output, and once set by the trigger means B during the ON period of the ON steady gate signal, it is not reset until the OFF signal is input, but becomes Lo level when set and Hi level when reset. F is AND means for logically ANDing the ON steady gate signal and the output of the trigger means B. The trigger means B and the AND means F constitute a holding means for holding the output of the comparing means D during the ON steady gate signal.

Next, the operation of the present embodiment will be described with reference to a signal waveform diagram shown in FIG. Time t1
Since the second capacitor 9 has been charged before, the comparison circuit D
Is set to the Hi level, and the output of the trigger means B is also set to the Hi level. When the ON steady gate signal is input at time t1, the AND means F becomes Hi level, so that the ON high gate switch 12b and the first
Of the first high-gate current, the discharge of the first capacitor 8 begins to flow through the resistor 10. If the inductance due to the wiring is ignored, the current due to the first capacitor 8 will be equal to the first capacitor 8 at this time.
Assuming that the charging voltage is Ec8s and the resistance value is r, it starts flowing at an initial peak of Ec8s / r. The second capacitor 9 also changes the charging voltage of the second capacitor 9 at time t1 to Ec9s,
Assuming that the inductance of the reactor 11d is L11d, it starts to flow as a current having an initial slope of Ec9s / L11d. The voltage of the first capacitor 8 decreases due to the discharge, and the current flowing through the resistor 10 decreases. Then, when the voltage of the second capacitor 9 drops to the reference voltage, (t
2a), the output A becomes Lo level, so that the output C also becomes L
The level becomes o level, the on-high gate signal is turned off, and the on-high gate switch 12b and the first switch are turned off. Second capacitor 9 and second reactor 1
If the peak current of the oscillating current according to 1d is adjusted to time t2a and the voltage of the second capacitor 9 is set to the same value as the reference voltage at that time, the gate current Ig becomes
And can be flowed as a substantially square wave. Hereinafter, it operates similarly to the case of Embodiment 1. Note that t2b is the second
At the time when the voltage of the capacitor 9 has recovered to the reference voltage.

As described above, the same low loss and energy saving effects as those of the first embodiment can be obtained, and the capacitance of the second capacitor 9 increases due to a temperature change or a manufacturing error. If the on-high gate signal is determined only by time when the inductance of the reactor 11d is increased, a peak current that satisfies the on-high gate current of the semiconductor element cannot be obtained, and the on-high gate current may be interrupted on the way. However, in the present embodiment, an on-high gate current time can be secured by flowing the current of the second reactor 11d until it reaches a peak, and a reliable on operation of the semiconductor element can be obtained.
If a problem is expected in the accuracy of the capacitance value of the second capacitor or the inductance value of the second reactor, these may be manufactured slightly larger and this embodiment may be employed.

Embodiment 6 FIG. This embodiment is shown in FIG.
Is used in combination with the first embodiment. In the first embodiment, the on-high gate signal is supplied from the outside, but here, the on-high gate signal is generated internally. Further, the voltage detecting means L detects the voltage of the second capacitor 9 in the fifth embodiment, but in this embodiment, the second reactor 11
The voltage of d is detected. The reference voltage is a small negative value. The rest is the same as in the fifth embodiment, and a description thereof will be omitted.

Next, the operation of the present embodiment will be described with reference to a signal waveform diagram shown in FIG. Time t1
Since no current has previously flowed through the second reactor 11d, for example, when the reference voltage is set slightly negative from 0 V, the output of the comparison circuit D is set to the Hi level, and the output of the trigger means B is also set to the Hi level. Have been. When an on-state gate signal is input at time t1, AN
Since the D means F goes to the Hi level, the on-high gate switch 12b and the first switch 19 are turned on.
Start flowing through. If the inductance due to the wiring is neglected, the current from the first capacitor 8 starts flowing at the initial peak of Ec8s / r, where the charging voltage of the first capacitor 8 is Ec8s and the resistance value is r. The second capacitor 9 starts to flow as a current having an initial slope of Ec9s / L11d at time t1, where the charging voltage of the second capacitor 9 is Ec9s and the inductance of the second reactor 11d is L11d. The voltage of the capacitor 8 decreases due to the discharge, and the current flowing through the resistor 10 decreases. Then, when the voltage of the second reactor 11d drops and reaches the reference voltage (t2a), the output A goes to the Lo level, the output C also goes to the Lo level, the on-high gate signal turns off, and the on-high gate switch 12b And the first switch is turned off. The second capacitor 9 and the second
The voltage at the connection point of the reactor 11d on the negative side swings to the negative side by an amount corresponding to the ON voltage of the second diode 18 with respect to the zero potential, so that when the current of the second reactor 11d input to the comparing means D reaches an extreme value, If the voltage of the second reactor 11d and the reference voltage have the same value, the gate current Ig can flow as a substantially square wave as shown in FIG. Hereinafter, it operates similarly to the case of Embodiment 1. As described above, the same low loss and energy saving effects as those of the first embodiment can be obtained, and the capacity of the second capacitor 9 and the second reactor 11
When the inductance of d changes, the same effect as in the fifth embodiment is obtained.

Embodiment 7 This embodiment is shown in FIG.
Is used in combination with the second embodiment. In the second embodiment, the on-high gate signal is supplied from the outside, but here, the on-high gate signal is generated internally. Figure 3 shows the circuit configuration
The description is omitted because it is the same as FIG. The voltage detecting means L detects the voltage of the second capacitor 9. FIG.
Numeral 3 is a signal waveform diagram showing the operation. An on-high gate signal is generated in the same manner as in FIG. 11, and the same effects as in the second and fifth embodiments are obtained.

Embodiment 8 FIG. This embodiment is shown in FIG.
Is used in combination with the second embodiment. In the second embodiment, the on-high gate signal is supplied from the outside, but here, the on-high gate signal is generated internally. Figure 3 shows the circuit configuration
The description is omitted because it is the same as FIG. Voltage detection means L detects the voltage of second reactor 11d.
FIG. 14 is a signal waveform diagram showing the operation. An on-high gate signal is generated in the same manner as in FIG. 12, and the same effects as in the second and sixth embodiments are obtained.

Embodiment 9 This embodiment is shown in FIG.
Is used in combination with the third embodiment. In the third embodiment, the on-high gate signal is supplied from the outside, but here, the on-high gate signal is generated internally. Figure 5 shows the circuit configuration
The description is omitted because it is the same as FIG. The voltage detecting means L detects the voltage of the second capacitor 9. FIG.
Numeral 5 is a signal waveform diagram showing the operation. An on-high gate signal is generated in the same manner as in FIG. 11, and the same effects as in the third and fifth embodiments are obtained.

Embodiment 10 FIG. This embodiment is shown in FIG.
The on-high gate signal generation means shown in FIG.
In the third embodiment, an on-high gate signal is supplied from the outside, whereas here, an on-high gate signal is generated internally. The circuit configuration is the same as in FIGS. 5 and 10, and a description thereof will be omitted. Voltage detection means L detects the voltage of second reactor 11d. FIG. 16 is a signal waveform diagram showing the operation. An on-high gate signal is generated in the same manner as in FIG. 12, and the same effects as in the third and sixth embodiments are achieved.

Embodiment 11 FIG. This embodiment is shown in FIG.
The on-high gate signal generating means shown in FIG.
In the fourth embodiment, the on-high gate signal is supplied from the outside, whereas the on-high gate signal is generated internally here. The circuit configuration is the same as in FIGS. 7 and 10, and a description thereof will be omitted. The voltage detecting means L detects the voltage of the second capacitor 9. FIG. 17 is a signal waveform diagram showing the operation. An on-high gate signal is generated as in the case of FIG.
Also, the same effects as those of the fifth embodiment can be obtained.

Embodiment 12 FIG. This embodiment is shown in FIG.
The on-high gate signal generating means shown in FIG.
In the fourth embodiment, the on-high gate signal is supplied from the outside, whereas the on-high gate signal is generated internally here. The circuit configuration is the same as in FIGS. 7 and 10, and a description thereof will be omitted. The voltage detecting means L detects the voltage of the primary winding 24a of the second reactor 24. FIG. 18 is a signal waveform diagram showing the operation. An on-high gate signal is generated in the same manner as in FIG. 12, and the same effects as in the fourth and sixth embodiments are obtained.

Embodiment 13 FIG. This embodiment is used in combination with the first embodiment. In the first embodiment, the on-high gate signal is externally applied, whereas the on-high gate signal is generated internally here. FIG. 19 is a circuit diagram showing an on-high gate signal generation means according to the thirteenth embodiment, where H is an OR means for taking a logical OR of the output of the AND means and the reference time signal. The reference time signal is a signal indicating a minimum necessary period during which an on-high gate current is required to flow according to the specifications of GTO1. The rest is the same as in the fifth embodiment, and a description thereof will be omitted.

Next, the operation in the present embodiment will be described with reference to a signal waveform diagram shown in FIG. FIG.
In 0, the voltage a of the second capacitor 9 indicates case 1 and the voltage b indicates case 2. Case 1 is a case where the capacitance of the second capacitor 9 is reduced due to a temperature change or a manufacturing error, or the inductance of the second reactor 11d is reduced. This is the case where the capacitance of the capacitor 9 increases or the inductance of the second reactor 11d increases.

Before time t1, the second capacitor 9 is charged, so that the output of the comparison circuit D is set to the Hi level, and the output of the trigger means B is also set to the Hi level.
When the ON steady gate signal is input at time t1,
Since the AND means F is at the Hi level, the on-high gate switch 12b and the first switch 19 are turned on, and the on-high gate current starts to flow through the resistor 10 through the discharge of the first capacitor 8 first. If the inductance due to the wiring is neglected, the current through the first capacitor 8 can be expressed as follows: the charging voltage of the first capacitor 8 at this time is Ec8s, and the resistance value is r.
Then, it starts to flow at the initial peak of Ec8s / r. Second
If the charging voltage of the capacitor 9 is Ec9s and the inductance of the second reactor 11d is L11d at time t1, the capacitor 9 starts flowing as a current having an initial slope of Ec9s / L11d. The voltage of the first capacitor 8 decreases due to the discharge, and the current flowing through the resistor 10 decreases.
Then, when the voltage of the second capacitor 9 drops and drops to the reference voltage (t2a1 or t2a2), the output A becomes Lo level, and therefore the output C also becomes Lo level.

The peak current of the oscillating current generated by the capacitor 9 and the second reactor 11d is adjusted so as to be at the time t2a0 at which the reference time signal is matched. At this time, the gate current Ig can be adjusted to the same value as the reference voltage. Required period,
As shown in FIG. 2, it can flow as a substantially square wave. However, in case 1 shown by the voltage waveform a of the second capacitor 9, the output of the AND means F that ANDs the on-state gate signal and the output of the trigger means B is equal to the on-high gate current defined by the reference time signal. It is set to the Lo level at t2a1 before the time. Therefore, in order to allow a specified time to flow, an OR circuit H that performs an OR operation on the output J of the AND circuit F and the reference time signal outputs the signal to the on-high gate switch 12b and the first switch 19 as shown in FIG. Time t
Extend from 2a1 to t2a0 defined by the reference time signal.

In case 2 shown by the voltage waveform b of the second capacitor 9, the current of the second capacitor 9 does not rise within the time specified by the reference time signal, and the semiconductor element is reliably turned on. For this purpose, it is necessary to supply a current longer than a specified time. Therefore, as shown in FIG. 20, the time of the signal to the on-high gate switch 12b and the first switch 19 is extended from t2a0 to t2a2 by the OR means H which takes the OR of the output J of the AND means F and the reference time signal. t
2a2 is the time when the voltage b of the second capacitor 9 drops to the reference voltage. In this way, the output of the OR means H is used as an on-high gate signal, the on-high gate switch 12b and the first switch 19 are turned off from t2a0 to t2a2, and thereafter the operation is the same as in the first embodiment.

As described above, the same low loss and energy saving effects as those of the first embodiment can be obtained. In addition, when the capacitance of the second capacitor 9 is increased due to a temperature change, a manufacturing error, or the like, If the on-high gate signal is determined only by time when the inductance of the reactor 11d is increased, a peak current that satisfies the on-high gate current of the semiconductor element cannot be obtained, and the on-high gate current may be interrupted on the way. However, in the present embodiment, the current flows through the second reactor 11d until the current reaches a peak. Conversely, when the capacitance of the second capacitor 9 is reduced or when the inductance of the second reactor 11d is reduced, if only the voltage of the second capacitor 9 determines the time, it is required from the semiconductor element. It is conceivable that a time that satisfies the specified time of the on-high gate current cannot be obtained.However, in the present embodiment, it is possible to flow up to the specified time based on the reference time signal, so that an appropriate period of the on-high gate current can be secured. In both cases 1 and 2, a reliable ON operation of the semiconductor element can be obtained. In the above description, the on-high gate signal generation means of FIG. 19 is combined with the first embodiment, but can be combined with any of the second to fourth embodiments, and the same effect is obtained.

Embodiment 14 FIG. Embodiment 14 of the present invention will be described below with reference to FIG. Voltage detection means L
Detects the voltage of the second capacitor 9 in the thirteenth embodiment, but detects the voltage of the second reactor 11d in the thirteenth embodiment.
The voltage of is detected. The reference voltage is a small negative value. Other features are the same as those in the thirteenth embodiment, and a description thereof will be omitted. Next, the operation in the present embodiment will be described with reference to FIG.
1 will be described with reference to a signal waveform diagram shown in FIG. In FIG. 21, a of the voltage of the second reactor 11 d indicates Case 1 similar to that of the thirteenth embodiment, and b indicates Case 2. Since no current flows through the second reactor 11d before the time t1, for example, when the reference voltage is set slightly negative from 0 V, the output of the comparison circuit D is set to the Hi level,
The output of the trigger means B is also set to the Hi level.
When the ON steady gate signal is input at time t1,
Since the AND means F is at the Hi level, the on-high gate switch 12b and the first switch 19 are turned on, and the on-high gate current starts to flow through the resistor 10 through the discharge of the first capacitor 8 first. If the inductance due to the wiring is ignored, the current from the first capacitor 8 starts flowing at the initial peak of Ec8s / r, where the charging voltage of the first capacitor 8 is Ec8s and the resistance value is r. The second capacitor 9 starts to flow as a current having an initial slope of Ec9s / L11d at time t1, where the charging voltage of the second capacitor 9 is Ec9s and the inductance of the second reactor 11d is L11d. The voltage of the first capacitor 8 decreases due to the discharge, and the current flowing through the resistor 10 decreases.

Then, when the voltage of the second reactor 11d drops and reaches the reference voltage (t2a1 or t2a2), the output A goes low, and the output C also goes low. Second capacitor 9 and second reactor 11d
Is connected to the second diode 18 with respect to 0 potential.
Swings to the negative side by the ON voltage of the second reactor 11d, so that the voltage of the second reactor 11d and the reference voltage when the current of the second reactor 11d input to the comparison means D reaches an extreme value are the same. If so, the gate current Ig can flow as a substantially square wave as shown in FIG. However, in case 1 shown by the voltage waveform a of the second reactor 11d,
The output of the AND means F that ANDs the on-state gate signal and the output of the trigger means B is set to the Lo level at t2a1 before the time of the on-high gate current specified by the reference time signal. Therefore, in order to spend the specified time, AN
As shown in FIG. 21, an on-high gate switch 1 is provided by an OR means H which performs an OR operation between the output J of the D means F and the reference time signal.
The time of 2b and the signal to the first switch 19 is extended from t2a1 to t2a0.

In case 2 shown by the voltage waveform b of the second reactor 11d, the current does not rise within the specified time according to the reference time signal, and the current does not rise for the reliable ON operation of the semiconductor element. Need to flow for longer than the specified time. Therefore, as shown in FIG. 21, the time of the signal to the on-high gate switch 12b and the first switch 19 is extended from t2a0 to t2a2 by the OR means H which takes the OR of the output J of the AND means F and the reference time signal. t2a2 is the time when the voltage b of the second reactor 11d has dropped to the reference voltage. In this way, the output of the OR means H is used as an on-high gate signal, the on-high gate switch 12b and the first switch 19 are turned off from t2a0 to t2a2, and thereafter the operation is the same as in the first embodiment. As described above, effects similar to those of the thirteenth embodiment can be obtained. In the upper diagram, the on-high gate signal generation means of FIG. 19 is combined with the first embodiment, but can be combined with any of the second to fourth embodiments, and the same effect is obtained.

In the first to fourteenth embodiments, the conversion method using the combination of the on-gate power supply 3 and the chopper circuit 2 is described as the on-state gate circuit having the function of controlling the on-gate current constant. It may have a function of constant current control by controlling the phase of a high-frequency AC power supply with a mag amplifier, and may be a converter having a function of constant current control and a DC output. .

[0049]

According to the semiconductor device drive circuit of the first aspect, the first capacitor is discharged through the resistor,
In discharging the second capacitor from the second capacitor through the second reactor to flow the on-high gate current, the second switch which does not directly contribute to the turning on of the semiconductor element is provided by the first switch and the on-high gate switch which is turned on for a specified time. Cut off the current after the peak current of the reactor current,
An ON steady gate current is supplied to the gate. As a result, the loss generated in each switch can be reduced.
In addition, the cut-off current of the second reactor is connected to the resistance and the first reactor.
Flows as an oscillating current through the capacitor, the second capacitor, and the second reactor. When the off signal is turned on while the oscillating current is flowing and the GTO is in the off operation, the capacitor is used to pass an on-high gate current. There is an effect that the energy of the charging current of the first and second capacitors can be reduced by recovering the charging energy of the first and second capacitors. According to the driving circuit of the semiconductor device according to the second aspect,
As in the case of the above, the generated loss can be reduced, and when the on-high gate current is cut off, the cut-off current of the second reactor flows as a resonance current through the bypass diode, the first capacitor, the second capacitor, and the second reactor. ,
In the reverse direction, the current flows through the resistor, the first capacitor, the second capacitor, and the second reactor as an oscillating current, thereby extending the time during which the oscillating current flows, and transferring the energy of this current to the first and second capacitors. By recovering the charging energy, the energy of the charging current for the first and second capacitors can be reduced.

According to the driving circuit of the semiconductor device according to the third aspect, it is possible to reduce the occurrence loss as in the case of the first aspect, and to cut off the second cut-off when the on-high gate current is cut off.
Of the reactor flows as a resonance current through the second switch, the first capacitor, the second capacitor, and the second reactor that move in synchronization with the signal after the on-high gate, and the oscillation current flows until the off-gate signal is input. Therefore, the energy of this current can be more efficiently recovered as the charging energy of the first and second capacitors, so that the energy of the charging current of the first and second capacitors can be reduced. According to the drive circuit for a semiconductor device according to claim 4,
As in the case of the first aspect, the generated loss can be reduced, and when the on-high gate current is interrupted, the energy of the interrupted primary winding current of the second winding type second reactor is reduced to the secondary winding of the primary winding. By regenerating the power to the on-gate power supply through the fourth diode, the power supply energy of the drive circuit of the semiconductor element can be reduced.

According to the driving circuit of the semiconductor device according to the fifth aspect, the same effects as those of the first to fourth aspects can be obtained. According to the driving circuit of the semiconductor device according to the sixth to eighth aspects, the same effect as that of the first to fourth aspects is obtained, and the on-high gate signal is internally generated, whereby the second capacitor is formed. The on-high gate current can flow until the discharge current of the semiconductor device reaches a peak, so that the necessary amount of on-high gate current can be secured even when the capacity of the second capacitor or the inductance of the second reactor increases. Is obtained.

According to the driving circuit of the semiconductor device according to the ninth to eleventh aspects, the same effects as those of the first to fourth aspects can be obtained, and the on-high gate signal is internally generated, so that at least If the peak of the discharge current of the second capacitor exceeds the specified time while securing the minimum specified time, the on-high gate current can flow until the peak time, so that the capacity of the second capacitor or the second reactor In both cases where the inductance of the semiconductor device increases and decreases, the necessary on-high gate time and current amount can be secured, and a reliable ON operation of the semiconductor element can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a drive circuit of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the drive circuit of the semiconductor element according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a drive circuit of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a waveform chart showing an operation of the drive circuit of the semiconductor element according to the second embodiment of the present invention;

FIG. 5 is a circuit diagram showing a drive circuit of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a waveform chart showing an operation of the drive circuit of the semiconductor element according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a drive circuit of a semiconductor element according to a fourth embodiment of the present invention.

FIG. 8 is a waveform chart showing an operation of a drive circuit of a semiconductor element according to a fourth embodiment of the present invention.

FIG. 9 is a connection diagram showing another example of the second reactor of the drive circuit of the semiconductor element according to the fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing an on-high gate signal generation means of a semiconductor element drive circuit according to the fifth to twelfth embodiments of the present invention.

FIG. 11 is a waveform diagram showing signals of a drive circuit according to a fifth embodiment of the present invention.

FIG. 12 is a waveform chart showing signals of a drive circuit according to a sixth embodiment of the present invention.

FIG. 13 is a waveform chart showing signals of a drive circuit of a semiconductor element according to a seventh embodiment of the present invention.

FIG. 14 is a waveform chart showing signals of a driving circuit of a semiconductor element according to an eighth embodiment of the present invention.

FIG. 15 is a waveform chart showing signals of a drive circuit of a semiconductor element according to a ninth embodiment of the present invention.

FIG. 16 is a waveform chart showing signals of a drive circuit of a semiconductor element according to a tenth embodiment of the present invention.

FIG. 17 is a waveform chart showing signals of a drive circuit of a semiconductor element according to an eleventh embodiment of the present invention.

FIG. 18 is a waveform chart showing a signal of a drive circuit of a semiconductor element according to a twelfth embodiment of the present invention.

FIG. 19 is a circuit diagram showing on-high gate signal generation means of a drive circuit for a semiconductor element according to Embodiments 13 and 14 of the present invention.

FIG. 20 is a waveform chart showing signals of a drive circuit of a semiconductor element in a thirteenth embodiment of the present invention.

FIG. 21 is a waveform chart showing signals of a drive circuit of a semiconductor element in a fourteenth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a conventional driving circuit for a semiconductor element.

FIG. 23 is a waveform chart showing an operation of a conventional semiconductor element drive circuit.

[Explanation of symbols]

1 GTO, 8, 9 First and second capacitors, 10
Resistor, 11d second reactor, 12a on-state gate switch, 12b on-high gate switch,
13 Off-gate switch, 17, 18, 21, 25
1st to 4th diodes, 19, 23 First and second switches, 22 bypass diodes, 24 second reactors, 24a, 24b Primary and secondary windings, 31, 32
First and second series circuits, 33 capacitor parallel circuits, B
Trigger means, D comparison means, E zero potential part, F A
ND means, G gate, HOR means, L voltage detection means.

Claims (11)

[Claims] An on-high gate circuit for supplying an on-high gate current for driving the semiconductor element to a gate of the semiconductor element, an on-state gate circuit having a constant current control function and supplying a constant on-state gate current. An on-high gate circuit, comprising: an on-high gate switch that opens and closes in synchronization with an on-high gate signal; and a capacitor parallel circuit that supplies the on-high gate current. And a first switch that opens and closes in synchronization with the on-high gate signal.
A first series circuit formed by connecting a first capacitor and a resistor in series, and a second series circuit formed by connecting a second capacitor and a reactor in series; and One of the gate and the on-high gate switch, the other of the on-high gate switch and the resistance of the capacitor parallel circuit, the reactor side, the first and second capacitor sides of the capacitor parallel circuit and the first switch One of the first switch and the other of the first switch are connected to the zero potential portion, respectively, and the first and second capacitors have first to third diodes for charging the capacitor. 1, the anode of the second diode, the connection point between the first capacitor and the resistor, and the cathode of the first diode, and the connection between the second capacitor and the reactor And the cathode of the second diode, the connection point between the first and second capacitors and the first switch, the anode of the third diode, and the gate and the cathode of the third diode, respectively. A driving circuit of a semiconductor element, characterized by comprising: 2. The device according to claim 1, wherein a bypass diode is provided in parallel with the resistor of the first series circuit, and an anode of the bypass diode is connected to the reactor and a cathode of the bypass diode is connected to the first capacitor. The driving circuit of the semiconductor device according to the above. 3. The driving circuit for a semiconductor device according to claim 1, wherein a second switch that opens and closes in synchronization with a signal after on-high gate is connected in parallel with the resistance of the first series circuit. 4. An on-high gate circuit for supplying an on-high gate current for driving the semiconductor element to a gate of the semiconductor element, and a constant on-state gate current having a constant current control function and an on-gate power supply capacitor. In a drive circuit for a semiconductor device, comprising: an on-steady gate circuit for supplying an off-gate current; and an off-gate circuit for supplying an off-gate current, the on-high gate circuit includes an on-high gate switch that opens and closes in synchronization with an on-high gate signal; A capacitor parallel circuit for supplying a current; and a first switch that opens and closes in synchronization with the on-high gate signal. The capacitor parallel circuit includes a first capacitor and a resistor connected in series. And the series connection of the second capacitor and the primary winding of the two-winding reactor in series. A second series circuit is connected in parallel, and one of the gate and the on-high gate switch, the other of the on-high gate switch and the resistance of the capacitor parallel circuit, the reactor side, Connecting the first and second capacitor sides of the capacitor parallel circuit to one of the first switches, and the other of the first switches to the zero potential portion, respectively;
A first to a fourth diode for charging the first and second capacitors and the on-gate power supply capacitor;
A connection point between the zero potential portion and the anodes of the first and second diodes, a connection point between the first capacitor and the resistor,
The cathode of the diode, the connection point between the second capacitor and the reactor and the cathode of the second diode,
A secondary winding connected to a connection point between the first and second capacitors and the first switch, an anode of the third diode, a gate of the third diode, a cathode of the third diode, and a primary winding of the reactor And an anode of a fourth diode, and the on-gate power supply capacitor and a cathode of the fourth diode, respectively. 5. The driving circuit for a semiconductor device according to claim 1, wherein an on-high gate signal is externally applied to the on-high gate circuit. 6. A voltage detecting means for detecting a voltage of the second capacitor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, and a holding means for holding a result of the comparing means in an on-state gate signal. 5. The driving circuit for a semiconductor device according to claim 1, further comprising an on-high gate signal generation unit having the on-gate signal generation unit. 7. An on-high gate having voltage detecting means for detecting a voltage of a reactor, comparing means for comparing an output of the voltage detecting means with a reference voltage, and holding means for holding a result of the comparing means in an on-state gate signal. 4. The driving circuit for a semiconductor device according to claim 1, further comprising a signal generating unit. 8. A voltage detecting means for detecting a voltage of a primary winding of a reactor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, and holding a result of the comparing means in an on-state gate signal. 5. A driving circuit for a semiconductor device according to claim 4, further comprising an on-high gate signal generating means having means. 9. A voltage detecting means for detecting a voltage of the second capacitor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, a holding means for holding a result of the comparing means in an on-state gate signal, and 5. The driving of a semiconductor device according to claim 1, further comprising an on-high gate signal generating means having an OR means for performing a logical OR of an output from the holding means and a reference time signal. circuit. 10. A voltage detecting means for detecting a voltage of a reactor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, a holding means for holding a result of the comparing means during an on-state gate signal, and a holding means for holding the result 4. The drive circuit for a semiconductor device according to claim 1, further comprising an on-high gate signal generating means having an OR means for performing a logical OR of an output from the means and a reference time signal. 11. A voltage detecting means for detecting a voltage of a primary winding of a reactor, a comparing means for comparing an output of the voltage detecting means with a reference voltage, and holding the result of the comparing means in an on-state gate signal. 5. The driving circuit for a semiconductor device according to claim 4, further comprising: an on-high gate signal generating means having an OR means for performing a logical OR of an output from the holding means and a reference time signal.