JPS6292029A - Microprogram control circuit - Google Patents

Abstract

PURPOSE:To shorten the processing time of a processor by shortening an instruction decoding time through an instruction word pre-fetching/decoding circuit for only the corresponding instruction, etc., when the arithmetic is carried out among registers with each other. CONSTITUTION:The data stored in a ROM11 are sent to a ROM data signal line 13 by an address signal 12 designated by an address control circuit 10 and latched by an instruction latch circuit 14 or fetched by an instruction word pre-fetching/decoding circuit 15. The circuit 15 fetches the ROM data from the front edge of a clock BR6 only when an operation A+B A, for example, is carried out between registers. Then a specific instruction of the next cycle is pre-fetched and decoded by the clocks BR6 and BR7. If this instruction indicates an arithmetic operation, a switch 21 is controlled by a register address control signal 20 so that an address of the register can be immediately designated from the front edge of the first clock BR0 of the next cycle.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The invention relates to an instruction preemption decoding circuit in a processing device using micro-10 gram control, and in particular to a control circuit suitable for shortening the instruction execution processing time between registers. Regarding.

[Background of the invention]

In register tow calculations under microprogram control, as processing speed increases, register access time becomes a problem, so a circuit that takes 277 cycles for this process alone is adopted, or a circuit that takes 277 cycles for the process itself is used. We are trying to improve efficiency. However, in the former case,
In the latter case, a 90,000-instruction system with 90,000 commands is being considered, as in P# 58-48146, but this excludes register (memory) access. An instruction prefetching method that involves access between registers is not described.

[Purpose of the invention]

The purpose of obscurity is to speed up the instruction decoding time by using an instruction preemption circuit to speed up the processing speed of one machine cycle when performing operations between registers that take the longest processing time in a processing device controlled by a microprogram. It is an object of the present invention to provide a circuit system that improves the processing speed of a processing device by reducing the burden of accelerating the access time of a register or RAM for improving performance.

[Summary of the invention]

When performing arithmetic processing using a microprogram, for example, A, +
In the process of B-A, if you try to execute this instruction in one cycle, the register address must be accessed five times, and the register access time is constrained to be less than or equal to τ of one cycle, so a high-speed register is required. becomes. In the present invention, a special instruction preemption W4 reading circuit is provided, and even if the same register (RAM) as the conventional one is used, it is possible to realize a control system capable of faster processing than the conventional circuit.

[Embodiments of the invention]

An embodiment of the present invention will be described with reference to FIGS. 1 and 2.

In FIG. 1, 1 is an arithmetic circuit (hereinafter abbreviated as ALU)
2 a registers (BH14(J)), 6 b registers (bRH()) and aBUs4, bBUs5 respectively.
, and sends a single unit of aBUs and bBUs to aBUs6.

The data of the operation result sent to aBUs6 is stored in the general-purpose register g7 or external register 8. Further, 10 is an address control circuit, and 11Gj is a memory for storing a microprogram (hereinafter referred to as MPg), which is usually R.
To OM or P-O, set to 1. According to the address signal 12 specified by 10, the data in the 0M11 is sent to the ■70M data signal intelligence 13, and the instruction word launch circuit 14 latches or preempts the instruction logic P!
6 reading circuit 15. 14 is latched and 1 is f(
AJA4 data becomes command focus and command signal a11
6, the command IP! It is connected to the register address switching circuit 18 so as to be the address of the I reading circuit 17, bRHtJ3, or general-purpose register.

Figure 'aJ2 shows the tally B when calculating k+B-hA in the microprogram control circuit of the present invention.
This shows the time relationship for 几. Similarly, in the control circuit, it is assumed that one machine cycle is divided into eight parts, from B0 to B7.

Now, general purpose 1 (in EG7, register ACAI7G
) and register B(BH, 1(G)),
Consider the case where a command is issued to store the result in AR); (). First, in the instruction word latch circuit 14, the instruction word latched by the leading edge trigger of tarok BHJo is 1
6 sends the instruction to the instruction decoding circuit 17. 17 decodes that the instruction is an instruction A+B-A (DgCOD
E) Do. This R4 reading (1) EC) time is B in Figure 2.
It is assumed that it extends to the midpoint of H1. Therefore, the register address signal 19 specifies the address of EGA or the middle point of EGA1 to the trailing edge of BH2. Then, by the trailing edge trigger of BH2, the contents of AIG are stored in BG2, and then the contents of AIG are stored from the leading edge of BH3 to the trailing edge of BH5.
19 specifies the address of GB.

1) REG3 is the register signal 9 at the leading edge of BRs.
Latch. In ALU1, the calculation of A+8 starts when the data of bRgG3 is finalized, and the calculation process ends between BRs. And A.L.
The results from Ul, 13 It.

During 6.7, specify the IOA address and enter ■3几7
At the trailing edge trigger, it backs into the EGA like a 'froco'.
When performing an operation such as A+B-A, the address of a register must be specified sequentially during one machine cycle, so as one machine cycle becomes faster, one register is used. l(, AM must also be fast. In this example, the minimum value of the access time of the RAM used must be (σ) that satisfies the address access time of (ri) in FIG. 2. According to the present invention, by using the 15 arithmetic instruction prefetch V decoding circuits 15, the register address control signal 20, and the register address switching control circuit 21, the access time of LE A M is reduced to the minimum iut or RA l~ 1
It may be used for historical purposes.

In other words, only when calculating between EG and BH30 such as A+M-A, in the previous cycle, the ROM data signal, l
Jl 31C Yoris 15&”l, from the front side of BH6,
Import ROM data. Then, in B-6.7, the next cycle or one example instruction is decoded in advance (
In;C). And, if that instruction is an arithmetic instruction, R immediately starts from the leading edge of 3 it O at the beginning of the next cycle.
21 by signal 20 so that the address of gdA can be specified.
operate.

However, 1. , regarding the data in the ROM, it is assumed that the command word of the current cycle is read out in the previous cycle VC, and furthermore, it is assumed that it has been determined by the previous cycle of B6 of the previous cycle.

As described above, according to 15.20.21, as shown in the lL g G address access time at instruction prefetch 9 in Figure 2, the time comparable to ■ during instruction prefetch is 2 times the time of ■
It would be better to double the access time. Therefore, the access time of l(, AM to be used is RA
If it is M, it will be possible to use the convenience, and due to the pre-emption of 9 circuits, 1
．． A memory with an access time of about 5B or a memory with an access time of 28R will suffice.

〔Effect of the invention〕

11.? ; If you try to realize even faster μPg-controlled processing WR without increasing the G or RAM access time, conventionally, RKG (I
tAM) for simultaneous parallel access, or L1. , () - R80 only, the processing takes two machine cycles to set up, leading to an increase in node costs or prolonging the processing time. For example, 几E(
) - By providing a circuit that preempts instructions only during calculations between R80, the processing time is not delayed, and the amount of codes does not increase due to the two-point REG.
Since high speed can be achieved using the conventional R,g(J(RAM)), it is effective in reducing cost and processing time.

[Brief explanation of drawings]

11!1■ is a block diagram of a circuit showing one embodiment of the present invention, and the second factor is the BE for the clock signal in the embodiment.
FIG. 3 is an explanatory diagram showing the time relationship of G access times. 1-...Arithmetic circuit, 7...General-purpose register, 8...Outside 9. v register, 9... register output signal -j[,10...
...Address control circuit, 14...Instruction word latch circuit,
15... Instruction word prefetch decoding circuit, 16... Instruction signal line, 17... Instruction decoding circuit, 18... Address switching circuit, 19... Register address signal, 20... Register address control signal, 21...Register address switching control circuit. )1. tage

Claims (1)

[Claims] In a processing device controlled by a microprogram that has a general-purpose register consisting of a temporary memory circuit that can be read and written, such as a RAM, only when operations between general-purpose registers are performed within one machine cycle, the instruction is executed in the previous cycle.
The feature is that it is equipped with a special instruction prefetch circuit that prefetches and decodes the register address, and a register address switching control circuit.Even if the same RAM is used without the above circuit, it takes one machine cycle more than before. A microprogram control circuit characterized by increasing processing speed and making it possible to shorten the processing time of a processing device.