JPS6291872A - Testing circuit - Google Patents
Testing circuitInfo
- Publication number
- JPS6291872A JPS6291872A JP60232678A JP23267885A JPS6291872A JP S6291872 A JPS6291872 A JP S6291872A JP 60232678 A JP60232678 A JP 60232678A JP 23267885 A JP23267885 A JP 23267885A JP S6291872 A JPS6291872 A JP S6291872A
- Authority
- JP
- Japan
- Prior art keywords
- test
- circuit
- rom
- signal
- tested
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はICの機能が正常か否かを判別する為に、該I
C内に設けられたテスト用回路に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a method for determining whether the function of an IC is normal or not.
This relates to a test circuit provided in C.
従来、ICに内蔵されるテスト回路としては、該IC全
体の規模に対して極力小さくする争で、該ICのコスト
を抑え様とした為、第2図に示すようにテスト回路23
としては、設計段階にて想定して設計された入力回路2
1および制御回路22を有し、設計通シのテスト方法、
順番でしか、テスト出来ない回路構成となっていた。Conventionally, the test circuit built into an IC has been designed to be as small as possible compared to the overall size of the IC, and in order to reduce the cost of the IC, a test circuit 23 has been used as shown in FIG.
Input circuit 2, which was assumed and designed at the design stage, is
1 and a control circuit 22, a design-through testing method;
The circuit configuration was such that it could only be tested in sequence.
上述した従来のテスト回路はテストの自由度と言う点で
は全くと言って良い程無く、ICの不良箇所、不良テス
ト項目等の実積に基ついて、IC内部の所定被テスト回
路の駆動信号波形を変える事は、かなり難しく、テスト
回路を動作させる順番等を決定するプログラムを組み換
える事に依ってのみ、ある程度迄は可能であった。The conventional test circuit described above has almost no freedom in testing, and the drive signal waveform of a given circuit under test inside the IC is determined based on the actual number of defective parts of the IC, defective test items, etc. It is quite difficult to change this, and to a certain extent it was possible only by recombining the program that determines the order in which test circuits are operated.
本発明のテスト回路は、被テスト回路をテストする時に
主体的に駆動し、その出力信号をテスト時にのみ、駆動
の目的に沿って利用する様なテスト専用のR(JM (
リード・オンリーメモリー)を有し、このR(JMの出
力状態に従って所定被テスト回路の駆動信号を池々変化
させたり、被テスト回路各部のテスト順番を変えたり出
来る様に構成したものである。The test circuit of the present invention is a test-dedicated R (JM (
The circuit is configured such that the drive signal for a given circuit under test can be changed from time to time according to the output state of this R (JM), and the test order of each part of the circuit under test can be changed.
つまシ、従来のテスト回路のうち主黴なテスト用制御回
路をEPROM、EEPROM等のプログラムROM、
或いはMASK ROM等ハード的に内容が変えられ
る凡OMの様な各種のROMに置き換える事で、テスト
の自由度を上げたものである。Of the conventional test circuits, the main test control circuit is a program ROM such as EPROM, EEPROM, etc.
Alternatively, the degree of freedom in testing can be increased by replacing the ROM with a MASK ROM or other ROM whose contents can be changed by hardware.
第1図は本発明の一実施例を示す回路構成である。 FIG. 1 shows a circuit configuration showing one embodiment of the present invention.
11は入力信号制御回路でおり、テストプログラムに従
って入力端子から入力されてくる入力信号に応じて12
のROMの動作を制御する。12はラスト専用に置かれ
たROMであり、11の出力信号に応じて所定の部分(
通常はアドレス)が駆動され、所定の信号を出力する。11 is an input signal control circuit, and 12
Controls the operation of the ROM. 12 is a ROM placed exclusively for the last, and a predetermined portion (
address) is driven and outputs a predetermined signal.
ROM12の出力信号はテスト信号発生回路13に入り
、ROM12の出力に応じたテスト信号が作られ、被テ
スト回路に供給される。The output signal of the ROM 12 enters a test signal generation circuit 13, where a test signal corresponding to the output of the ROM 12 is generated and supplied to the circuit under test.
したがって、ROM12の内容を任意に設定する墨に依
シ、被テスト回路に供給されるテスト信号波形を任意に
決められる様に構成されている。Therefore, depending on the content of the ROM 12 being arbitrarily set, the test signal waveform supplied to the circuit under test can be arbitrarily determined.
以上説明した様に本発明は、テスト回路の一部にテスト
専用ROMを置く事を特徴とし、このROMの内容を変
える事に依シ、被テスト回路を駆動する信号波形つ一1
シは、被テスト回路内の各部分のテスト順番、テスト方
法等を任意に変える事が出来る。As explained above, the present invention is characterized in that a test-dedicated ROM is placed in a part of the test circuit, and by changing the contents of this ROM, the signal waveform that drives the circuit under test can be changed.
It is possible to arbitrarily change the testing order, testing method, etc. of each part in the circuit under test.
従って、従来は例えばテスト内容の不備を改善するKは
、テストプログラムを作シ直す事しか対応が取れなかっ
たが、本発明では、テスト専用ROMの内容を変えられ
ると15余地が出来る為、テストに対する自由度が飛躍
的に犬さくなり、テスト品質の高揚に多大な効果が期待
出来る。今後、更に大規模化するICのテストについて
は、ますます困難さを増す事が予想され、テストに対す
るN要度が増大する現状に於いて、本発明になるテスト
回路の需要が出てくるものと考える。Therefore, in the past, for example, the only way to improve deficiencies in test content was to rewrite the test program, but with the present invention, if the content of the test-specific ROM can be changed, there is 15 more room for testing. This dramatically reduces the degree of freedom for testing, and can be expected to have a significant effect on improving test quality. In the future, it is expected that testing of larger-scale ICs will become more and more difficult, and in the current situation where the N requirement for testing increases, there will be a demand for the test circuit of the present invention. I think so.
第1図は本発明の一実施例を示す回路構成図、第2図は
従来例のテスト回路である。
11.21・・・・・入力信号制御回路、12・・・・
・テスト専用ROM、13・・・・・テスト信号発生回
路、14 、23・・・・・テスト回路、22・・・・
・・テスト制御及び信号発生回路。
代理人 弁理士 内 原 晋t′ 茅 2 図FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIG. 2 is a conventional test circuit. 11.21... Input signal control circuit, 12...
・Test-only ROM, 13...Test signal generation circuit, 14, 23...Test circuit, 22...
...Test control and signal generation circuit. Agent Patent Attorney Susumu Uchihara t' Kaya 2 Figure
Claims (1)
いるテスト回路に於いて、テスト専用に設けられたRO
Mを有する事を特徴とするテスト回路。In the test circuit built into the IC to test whether the IC is a good product or not, an RO is installed exclusively for testing.
A test circuit characterized by having M.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60232678A JPS6291872A (en) | 1985-10-17 | 1985-10-17 | Testing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60232678A JPS6291872A (en) | 1985-10-17 | 1985-10-17 | Testing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6291872A true JPS6291872A (en) | 1987-04-27 |
Family
ID=16943076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60232678A Pending JPS6291872A (en) | 1985-10-17 | 1985-10-17 | Testing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6291872A (en) |
-
1985
- 1985-10-17 JP JP60232678A patent/JPS6291872A/en active Pending
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