JPS6289139A - Performance control system for information processor - Google Patents

Abstract

PURPOSE:To improve the efficiency and the flexibility by replacing the contents of a dummy pitch register and a dummy cycle register and controlling finely the instruction executing performance. CONSTITUTION:A counting action is started by the signal of a signal line 420, the contents of the dummy pitch register 401 outputted to a signal line group 411 are set to a counter A403, and simultaneously, the counting-down is started. The contents of a counter A403 come to be all '0', and then, '1' is outputted to a signal line 413, a latch A405 is set, and simultaneously, the contents of the dummy cycle register outputted to a signal group 412 by the main signal are set to a counter B404, and the counting-down action of a counter B is started. When the contents of the counter B come to be all '0', '1' is outputted to a signal line 414, a latch A405 is reset and simultaneously, the parameter fetching and the counting-down of the counter A403 are started. By the repeating of the action, the latch A405 can output the output of the time chart to a signal line 415.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a performance control method for an information processing device.

[Background of the invention]

In conventional information processing equipment, when realizing seven deltas with different performance using the same hardware, the first step is to take a larger machine cycle for the higher-level hardware with higher performance, or to install dummy cycles at regular intervals in the processing cycle. It was common to achieve a model with lower performance by inserting . This means of increasing the machine cycle and the conventional means of inserting dummies at regular intervals into the processing cycle have the following problems.

First, the method of increasing the machine cycle has the disadvantage that it cannot be increased indefinitely due to the nature of hardware logic. As this increases the machine cycle,
This is because the switching speed of hardware elements and the speed at which signals propagate on signal sets are relatively faster than machine cycles. Another disadvantage is that the machine cycle itself is used in a logic circuit and cannot be changed without changing the logic circuit. In other words, it has the disadvantage of not being able to significantly control performance.

Next, there is a means of inserting dummy cycles into the processing cycle at regular intervals.
No. 955 discloses a specific method thereof. Although it is possible to perform significant performance control using the method disclosed in JP-A-57-207955, the performance control is exemplified to be 1/2, 1/3, and 1/4 of the original performance. , the range of control is generally coarse, and in this example it is possible to combine each mode to achieve more fine-grained control, but no specific method is provided, and for example, 9/10. Performance control is not possible. Furthermore, the Japanese Patent Publication 1982
-207955 discloses a means of inserting a dummy cycle into the preceding control section of an instruction, but this example can only control the performance of only the preceding control section, and the actual execution section of the instruction cannot be controlled. Control of certain processing stages is not possible.

Furthermore, in the example of JP-A No. 57-207955,

Although panel switches, flip-flops, memory, etc. are used as the source of the signal for controlling performance, no means for dynamically changing the performance control is disclosed, and static performance control is not disclosed. It is not something that has been realized.

[Objective of the Invention 1 The object of the present invention is to eliminate the above-mentioned problems and drawbacks, and to provide a means for finely and dynamically inserting dummy cycles in an information processing device; A more efficient and flexible performance control method for information processing equipment? : To provide.

[Summary of the invention]

The present invention is characterized by a function of inserting a dummy cycle into the execution cycle of the central processing unit of an information processing device, and a dummy pitch register that controls how many cycles a dummy cycle is inserted. A dummy cycle register is provided to control whether or not to insert a duplex cycle, and by combining the contents of the dummy pitch register with the contents of the dummy cycle register, the method is much smoother and more flexible than conventional methods. The purpose of this invention is to realize a performance control method for information processing equipment with high performance.

A further feature of the present invention is that by providing a means for dynamically changing the contents of the double pitch register and the dummy cycle register, a performance control method for an information processing device that can dynamically change the performance of the VC is realized. There is a particular thing.

[Embodiments of the invention]

Next, embodiments of the present invention will be explained using drawings.

FIG. 1 is a block diagram of an information processing apparatus equipped with the performance control method of the present invention. In this example, there is one double pitch register and one dummy cycle register for inserting dummy cycles, but a plurality of registers may be provided and switched depending on conditions for summer use.

In Fig. 1, the control declaration 101 indicates each device that is connected in parallel! 1J5U, dummy pitch register 102, via signal lines 111, 112, 115 and 116 respectively
Dummy cycle register 103, dummy signal generation circuit 1
04 and the instruction execution power supply 105. The dummy pitch register 102 is a register that defines the issuing pitch of the dummy insertion instruction signal, and is connected to the control device 101 and the dummy signal generation circuit 104 via signals @111 and 113.

The dummy cycle register 103 is a register that specifies how many cycles of the dummy insertion signal are to be sent at one time, and is connected to the control unit fIt101 and the dummy signal generation circuit 104 via the signal line 112 and signals 111 and 114, respectively. .

The dummy signal generation circuit 104 has one pitch register 1.
This circuit generates an instruction signal to insert a dummy based on the information from the dummy pitch register 102, dummy cycle register 103, and dummy cycle register 10'5 through the signals @113, 114, and 115, respectively. It is connected to the control device 101. The instruction execution unit [105 is.

The signal line 116 is responsible for the execution of instructions.
It is connected to the control unit ft101 via.

In FIG. 1, the parameters defining the pitch at which the dummy is inserted are signal lines +111. ) via the control device 101
is dynamically set in the dummy pitch register 102 by. A parameter defining the number of dummy cycles per cycle is set in the dummy cycle register 103 by the control device 101 via the signal line 112. The tummy signal generation circuit 104 extracts the dummy insertion instruction signal from the dummy pitch register 102 and the dummy cycle register sent via the signal lines 113 and 114, and sends it to the blue control device 101 via the signal line 115ft.

The control device IQ1 outputs the signal l1li! Based on the received dummy insertion instruction signal via signal line 115, the receiver issues an instruction to insert a dummy or a temporary stop instruction to instruction execution device j1105 via signal line 116.

Next, the relationship between the contents of the dummy pitch l register 102, the contents of the dummy cycle register 103, and the output of the double insertion instruction signal 115 is shown in a time chart using FIGS. 2 and 3 of the IC.

FIG. 2 shows an example in which the contents of the dummy pitch register 102 are 131 and the contents of the dummy cycle register 103 are +2°. Time check in Figure 2? -), the output of two cycles is output to the dummy insertion instruction signal 115 every five cycles, and in this case, the instruction execution device executes the instruction processing of three cycles in five cycles. In other words, the performance is reduced to 6 degrees compared to when no dummy insertion signal is sent.

In FIG. 3, the contents of the dummy pitch register 102 are 151.
So, let's take an example where the content of dummy cycle register 103 is 111. In this case, the die is only for one cycle every six cycles.
An insertion instruction signal is output, and the performance can be reduced to about 83 inches.

FIG. 4 shows a more detailed circuit diagram of the dummy pitch register, dummy cycle register, and dummy signal generation circuit.

Parameters are set in the dummy pitch register 401 via the signal line 41B and output to the signal line group 411. Dummy cycle register 402 IC is signal line 419
Parameters are set and output to the signal line group 412 via. Counter A and counter B are counters with a function of decreasing X.

When the CK large input is 111, the data of Do=Dn is latched and the countdown is started, and the contents of the counter are all l□1.
When this happens, one cycle of output is sent from the T output.

Latch A is a latch with a boot/reset function.

The operation will be explained below using 419'&. The counting operation is started by a count start signal from the signal @420, and the contents of the dummy pitch register 401 output to the signal line group 411 are set to the counter A403K.
A countdown will start at the same time. Counter A 40
When all the contents of 3 become 1olIC, it becomes No. 1 @413'
1' is output, the latch A 405 is set, and at the same time, the contents of the dummy cycle register output to the signal 4N 412 are set to the counter BAQAK and the color/color B countdown operation is started. Signal @4 when the contents of counter B are all IoliC
14 ['1' is output, the latch A 405 is reset, and at the same time, the counter A 405 starts to take in parameters and count down.

By repeating the above operation Q-gL, the latch λ405 is set.

The outputs shown in the timer charts in Figures 2 and 3 can be output to the signal line 415.

The AND gate 405 controls whether or not to output to the signal line 416 which is the latch A 405 @dummy insertion instruction signal output to the signal line 415.

In other words, when the input of the signal line 417 is 111, the signal line 415
The contents of are output to the signal line 416. By inputting a hardware mode signal to the signal line 417, a reduced performance mode can be implemented. Furthermore, by inputting a part of the program status word, a part of the control register, or a combination condition thereof to the signal line 417, performance control depending on the running state of the program can be realized.

407 is an or gate.

Next, referring to the fifth decoy, a description will be given of how the dummy insertion instruction signal shown in FIG. 4 is generated.

Figure 5 is a control circuit diagram for controlling the arithmetic execution stage (based on microinstructions) in this embodiment. Lunch A3
In this example, the output of 01 controls the reading of the microinstruction that controls the execution of arithmetic operations, and when this latch is set to 111, the corresponding microinstruction is read out.

In the first example, the output of the launch B 502 has the role of permitting execution of the read micro'instruction. This latch is +1
If set to 1, previously read microinstructions will be executed. The output of latch C3D3 allows the second half of the execution of the microinstruction, and the output of latch D50
4σ) Output &i Allows the operation result of that cycle to be stored in the result storage register. The operation will be explained below using FIG.

When the microinstruction read start signal is applied to the signal line 511, the signal line 520 is applied to S;
2Kj, p+A301 is set on '1' lc. The contents of the latch A301 are output to the signal line 512□, and the power 1 and no signal input to the AND gate 505 are;
Z 11! Micro 66, get bored with Ij monovalent,
C) It is a congratulatory command signal. The contents of the AND gate 505 and the signal line 512 are ANDed with the condition of the signal line 510. The signal output to the signal line 513 is the signal from launch B 502 f? :F(]+hj
This is the output of Agate 507. To the OR gate 507Vc, a condition for inhibiting the execution of a microinstruction necessary for the operation of the hardware is inputted via a signal line 522, and a dummy matchmaker instruction signal according to the present invention is inputted to a signal line 523. In other words, the latch B104 outputs a signal to permit the execution of the micro command when it is necessary for the operation of the software and when the dummy instruction signal is sent.
The effect of inserting a dummy cycle is brought about by inhibiting the setting of the dummy cycle and, as a result, inhibiting the execution of the read microinstruction. Lunch B output to No. 48 edge 514
5020 set input, launch B5 at clock TO
02, and the set value is output to the signal line 515. A signal on a signal line 515 is distributed to each calculation section, and controls whether or not the calculation section executes a microfunction that has been read out in advance. That is, when this signal is 111, each arithmetic unit executes the arithmetic operation specified by the corresponding microinstruction, and when this signal is +01, the arithmetic operation is suppressed. Signal line 51
The micro operation controlled by 5 is the first half of the operation.

Furthermore, the output of the signal line 515 is input to the latch C503 and set to the latch 503 by the clock T2.
The signal line 516, which is the output of SOS, controls whether or not to execute the micro operation of each arithmetic processing unit in the same way as the output of the signal line 515. It is.

The output of the signal line 516 is input to the analog signal line 506 and the signal line 5170 input and 8NL) are taken. signal f35
At 17&c, a signal is manually input to prevent the execution result of the micro operation from being stored in the result register. For example, as a result of executing a micro-operation that is permitted to be executed by signals 515 and 516, an exception related to an operation is detected in operation 'xHis, and the register storing the result must not be rewritten. The value tt1011C of the signal line 518, which is the output of the gate 506, inhibits the setting of the latch D504.

Next, latch D504 latches the contents of signal line 51B at clock TO and sends the result to signal line 519.

The output of the signal line 519 is distributed to each controller, and the signal ga5
Indicate whether or not to write the results of the micro operations executed in steps 15 and 516 to the result storage register. II 'ji (do.

If this signal is 111, write 4k according to the micro operation to the register, and if it is “O”, write the result.
Suppress and result register answers! ! : Leave the value as it was before the calculation. This signal should be set to 111 when an operational exception is detected in an operation specified by a microinstruction.

Figure 6 shows the outputs of the latch person 501, latch B 502, latch C 503, and lunch D 504 shown in 1g5[F] when the outputs t are execution A, smile execution B, execution C, and execution, respectively, and there is no execution inhibition input.・This is a time chart for the case where there is no write inhibition or input. Clock TO is 111
The next interval of 111 is a basic cycle suitable for processing one report, and is called a Q-man cycle. One micro-operation is executed over two cycles, with half-cycles overlapping each other, as shown in the time sequence of Hawk 6 Ri I.

In execution A, (i a predetermined microinstruction is read out,
In execution B, the first half of the microinstruction is executed, in execution C, the second half of the microinstruction is executed, and in execution (the microinstruction is executed and the result of the operation is stored in the result register): be included.

? 7. 7th: Apply the Dubby Nakanin Abduction Indication Code created in the present invention to the signal line 523 in Figure 5, tψ11.
shows. The non-dummy input instruction word is 2 in 5 cycle pitch.
In this example, in Fig. 7, microinstructions 0), 2 and 3 are executed for 4hc, and then microinstruction 2 is sent out only to the executor who receives the read instruction signal and is executed. B, C and execution are inhibited from sending out two cycles.

After that, microinstructions (2), (2), and (2) are executed, and the execution of microinstruction (2) continues for two cycles. In other words, in this example, two dummy cycles are inserted into five cycles, and a performance of 7 can be obtained, which is 60 yen compared to the processing performance when a microinstruction is executed with in+7.

By inputting the above-mentioned dummy cycle insertion signal to the microinstruction execution unit j in this example, an information processing device having an arbitrary performance range can be realized.

〔Effect of the invention〕

As is clear from the above, according to the present invention, the instruction execution performance of the information processing machine can be controlled finely and almost continuously, and the performance of more advanced information processing equipment can be controlled continuously. We can provide a wide range of performance examples.

[Brief explanation of drawings]

The first factor is a structural diagram of an embodiment of the invention, FIGS. 2 and 3 are time charts explaining the sending of the dummy insertion signal of the invention, and FIG. 4 is a specific example of the dummy signal generation circuit of the invention. The circuit shown in FIG.
The figure is a time lead explaining the output tt of the circuit diagram of 451 yen, l. 101... Control 51 Yellow 102... Dummy pitch register 103... Dummy cycle register 104... Dummy signal generation circuit 105... Instruction execution performance. High 2 Figure name 3 Tsurumi 3 Yu - = 7 t, o Wooden piece, q] η FP 1

Claims (1)

[Claims] In an information processing device consisting of a main memory, an input/output processing unit, and a central processing unit, there is a function to insert a dummy cycle into the instruction execution cycle of the central processing unit, and a means for inserting this dummy cycle. It is equipped with a dummy pitch register that specifies whether to insert a dummy cycle every cycle, and a dummy cycle register that specifies the number of dummy cycles to be inserted, and the contents of the dummy pitch register and dummy cycle register can be statically or dynamically written. A performance control method for information processing equipment that is characterized by being able to finely control the instruction execution performance of a central processing unit by replacing the central processing unit.