JPS6286979A - Signal integrating type preamplifier - Google Patents

Abstract

PURPOSE:To reproduce faithfully a picture element signal in an input signal by synchronizing an integrating circuit and a sample holding circuit respectively to a capacitor and a selecting pulse and being composed of a switching element where ON and OFF are controlled by respective types of the control pulse having the prescribed phase difference and the prescribed pulse width. CONSTITUTION:The output edge of a buffer 55 is connected to the base of an NPN type transistor 57 of an integrating circuit K2, an emitter is grounded through a resistor 60, and the collector is connected to the collector of a PNP type transistor 56. The base of the transistor 56 is connected to a bias electric power source 59, and the collector is connected through a resistor 58 to an electric power source +B. The connecting middle point of transistors 56 and 57 is grounded through an integrating capacitor 61, connected to the base of an NPN type transistor 64 of a sample holding circuit K3 and connected through a switching element 62 to a positive electric power 63. The emitter of the transistor 64 is grounded through a resistor 65 and the collector is connected to the electric power source +B.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example H. Effect of the invention A. Industrial FIELD OF THE INVENTION The present invention relates to a signal integrating preamplifier suitable for application to liquid crystal display devices, MO8 imaging devices, and the like.

B. Summary of the Invention The present invention relates to a signal integrating preamplifier, in which a second integrating circuit is provided at the next stage of the first integrating circuit to which an input signal consisting of a pixel signal superimposed on a differential pulse of a selection pulse for reading out a pixel signal is supplied. An integrating circuit is connected, and a sample hold (gl path is connected to the next stage of the 20th) integrating circuit. and a switching element whose on/off is controlled by each control pulse having a predetermined pulse width, thereby eliminating the need for a ronno filter, eliminating the need for adjustment, and faithfully reproducing the pixel signal in the input signal. It has been made possible.

C. Prior Art First, a conventional liquid crystal display device will be explained with reference to FIG. In the third factor, (IJ is an input terminal, and the television signal (video signal) from this terminal is a switching confectionery M made of, for example, N-channel PET.
Signal H in the vertical (Y-axis) direction through l, M2...Mm
Lls L2...L, is supplied.

Note that m is a number corresponding to the number of pixels in the horizontal (X-axis) direction. Further, an m-stage shift register (2) is provided, and this shift register (2) is supplied with clock signals ΦIM and Φ2H of one time the horizontal cycle.
) from the output terminal of each stage, the pixel switch signal ΦIH2Φ is sequentially scanned by the clock signal ΦIH2Φ + moving part...gum is the switching element (MOS FE'I')
Each 11i1J of M1 to iVLm is supplied to both terminals.

Note that the shift register (2) is supplied with a low potential (Vss) and a high potential (VDD), thereby setting the maximum level and minimum level of the pixel switch signal.

In addition, each signal lfML1 to L- is connected to a switching element M11, for example, an N-channel MOS FET.
゜Ml1...Muni2M122M22...MrL2
．． ...Ml, 52M2. ! ...One end of Mny+ is connected. Note that the number is a number corresponding to the number of horizontal scanning lines.

The other ends of the switching elements Mll to Myu are liquid crystal cells C1□, C2, .

- Connected to target terminal (3) through C□.

Furthermore, an n-stage shift register (4) is provided, and this shift register (4) receives a horizontal frequency clock signal ΦIV.
'+Φ2V is supplied, and the scanning line switch signals uvl, ρv2, which are sequentially scanned by the clock signal ψIV'+Φ2v from each output terminal of this shift register (4).
...915vn is the gate point Gl in the horizontal (X-axis) direction,
q2...Switching elements M11-Mf through G3
&, each column in the X-axis direction (Mll-MlA) p (Ml
1-M7. , )...(Myu1 to Pigeon □) are respectively supplied to the control terminals. In addition, shift register (4)
Similarly to shift register (2), Hirohito v85. VDD
is supplied.

That is, in this circuit, a shift register (2).

(4) As shown in Fig. 2A and B, the lock signal ΦI
HpΦ2HpΦIVyΦ2v is supplied. The shift register (2) outputs a switch signal OHx-111m for each pixel period as shown in Figure 2C, and the shift register (4) outputs a switch signal OHx-111m for each horizontal period as shown in Figure 2C. Signals UVt to J'v3 are output.

Furthermore, a television signal (video signal) as shown in FIG. 2E is supplied to the input terminal tlJ.

Then, when the switch signals 1vlp lul are output from the shift register <4), (2J,
Switching confections M1 and Mll-Ml are turned on,
Input terminal (IJ → switching element M1 → signal HL1 →
A current path from the switching element Mll to the liquid crystal cell C1l to the target terminal (J) is formed, and the potential difference between the voltage at the input terminal (IJ) and the voltage at the target terminal (,3) is formed in the liquid crystal cell C1l. Therefore, a charge corresponding to the potential difference due to the signal of the first pixel is sampled and held in the capacitance of the liquid crystal cell C11.

The light transmittance of the liquid crystal changes depending on the amount of charge. A similar process is repeated for the cells C12 to C3, and when the next field signal is supplied, the amount of charge in each of the cells C11 to C□ is changed.

In this way, the light transmittance of the liquid crystal cells C1l to Cyo is changed corresponding to each pixel of the video signal, and this is sequentially repeated to display a television image.

By the way, when displaying with a liquid crystal, AC drive is generally used to improve its reliability and lifespan. For example, in displaying a television image, a signal obtained by inverting the television signal is supplied to the input terminal (11) for each field or frame.

That is, the input terminal (11 has 1 as shown in Fig. 2E)
An inverted television signal is provided for each field (or one frame).

By the way, in the above-mentioned apparatus, there is a demand for displaying an arbitrary television image as a still image. In that case, conventionally, for example, a memory for one field or one frame is provided, a desired image is stored in this memory, this is repeatedly output, and the phase of the read signal is inverted for each field. It is proposed to feed the above-mentioned input terminal (1).

However, the memory for one field or one frame as described above is itself large and expensive.
It is difficult to apply it to general consumer equipment.

In response to this, it has been proposed to display still images by utilizing the memory function of the liquid crystal cell C, as shown in Japanese Patent Application Laid-Open No. 58-107,782, for example. That is, in this device, in a liquid crystal video display drive circuit having a first sample and hold circuit that supplies a video signal whose polarity is inverted for each screen to a plurality of pixels in time series, this video signal is inverted and the polarity of the video signal is inverted. a second sample and hold circuit that outputs video signals from the plurality of pixels in time series; and a video signal from an external terminal or a video signal from this second sample and hold circuit. This is a liquid crystal video display driving circuit having a switching means for switching and supplying the signal to an inverting means.

However, in the case of this device, as stated in the publication, the image shifts by one pixel in the i-direction every time one field is displayed, so the scanning direction must be reversed for each field. However, switching the scanning direction in this way requires a large-scale circuit, and there remains a state in which each field is alternately shifted by one pixel. There is a risk that

Also, since the signal from liquid crystal cell C is taken out, this signal is returned to liquid crystal cell C, and this is repeated to display a still image, if there is a distortion in the transmission percentage of this dark signal, This distortion accumulates and the image quality deteriorates significantly in a short period of time. For this purpose, it has been shown that the gain of the inverting means can be adjusted, but it is impossible to make such an adjustment completely, and it is extremely difficult to display normal still images for a long period of time. It is.

Furthermore, when a signal is extracted from the liquid crystal cell C, if there is a residual charge in the stray capacitance or the like at the edge of the signal, the signal will also be degraded by this, making it impossible to display a still image for a long time.

Therefore, the present applicant proposed that since the signal taken out from the liquid crystal cell C is returned to the same liquid crystal cell C, there will be no image shift etc., no special scanning etc. will be required, and the drive circuit etc. will be the same as the conventional one. can be used as is, and since the signal is normalized and the potential of the signal line is reset, the image quality does not deteriorate due to these, and the product display can display good still images for a long time. equipment,%
It was proposed as Application No. 59-190,783. This will be explained with reference to FIG. 5 and subsequent figures.

In FIG. 5, the switching element M1 of FIG.
In place of the area, first switching elements (MOS PET) MA1 to MAm equivalent to these are provided, and second switching elements (MOS FET) equivalent to these are provided.
ET) MB1 to MB are provided. In addition to the shift register (2) described above, an m-stage shift register 4 equivalent to the shift register 2 is provided, and a clock signal ΦIH1Φ2H is supplied to the shift register 4.

The pixel switch signals B, D, D, etc. from the output terminals of each stage of the shift register (2U) are supplied to each control terminal of the switching elements MBI to MBm. A start pulse related to horizontal synchronization of the video signal (video signal) is supplied to shift register 4, and a start pulse with an earlier phase is supplied to shift register 4.

is supplied. Then, the input terminal (IJ is the normal display side contact N of the normal display/still image display changeover switch αυ)
It is connected to the switching element MAl "" MAm.

In addition, the connection midpoint of the switching element MBI xMB is connected to the input terminal of a preamplifier α4, the output terminal of this preamplifier α is grounded through a capacitor αJ, and this output terminal is connected to a normalizer (normalizer) through an inverting circuit a.
Connected to Alpha Mound. The output end of this normalization circuit is connected to the still image display side contact □S of the changeover switch Uυ. Furthermore, each signal ML1%L□ is connected to a predetermined abrasive pressure source, for example, a target terminal (3), through switching elements MR1+MR2...MRA.

In this device, switching elements MAI to M
The gate terminal of A is provided with a lock signal ΦIHyΦ2H as shown in FIG. 6A and B, and a 5 eggplant f as shown in FIG. 6C.
i-) A pixel switch signal IHx-1& as shown in the figure is supplied, which is formed by pulsed. In addition, a lock signal ΦIH is applied to the gate terminal of the switching element MBl ''=MBa as shown in FIG. 6A and B.
? A pixel switch signal (a selection pulse for starting a pixel signal) as shown in FIG. 2F formed by Φ2H and five start pulses 2 shown in FIG.

As a result, for example, at the target phase of the pixel switch signal, the signal of the liquid crystal cell C corresponding to the 2-in L3 is extracted by the in-phase pixel switch signal 0Ii3, and after this signal is amplified through the preamplifier α, the capacitor (
13, and its output is written into the same liquid crystal cell C through the inversion circuit α and the normalization circuit α~ at the phase of the pixel switch No. 6 H3 after a time τ. Here, liquid crystal cell C
The potential of the signal from is VS, and the capacitance of capacitor a is C5.
By setting the value of -A so that the preamplifier capacity is , the same inverted signal is rewritten into the liquid crystal cell C, and a still image is displayed by AC drive.

However, in this case, it is impossible to predetermine the value of -A in the manner described above. Therefore, normalization circuit u51
is provided. In other words, the input/output characteristics of this normalization circuit are as shown in FIG. Can be set to a constant value.

Furthermore, a horizontal blanking signal pHBLK is supplied to the gate terminals of the switching elements MRI to MRs.

Therefore, each signal HL1 to L1 is reset to the target voltage for each horizontal blanking. Therefore, the signals remaining on each signal line are reset, and unnecessary signals are not mixed in when the signal from the liquid crystal cell C is extracted.

In this way, still images are displayed, and the above-mentioned device has an extremely simple configuration, and the signal does not deteriorate even if it is displayed for a long time (it always maintains a good quality). Still images can be displayed.

In the above-mentioned device, the delay time τ from reading to writing is regulated by the cycle of the clock signal ΦIH2Φ2H, but it can be adjusted by arbitrarily determining the phase of the clock signal supplied to the shift register (21%4). , you can also set more detailed delay times.

In addition, in the above-mentioned device, the normalization circuit αω needs to perform the normalization process every time in a time shorter than one pixel clock.
If the processing time is not enough to increase the resolution of normalization, it is also possible to do as shown in FIG. 8, for example. The figure is shown without the display section. Further, FIG. 9 shows a timing chart.

That is, in FIG. 9, for example, the liquid crystal cell C connected to the signal line Ll at the phase of the horizontal switch signal ρd□ shown in A.
The signal successively output from is the sampling pulse P shown in B.
It is held in the sample hold (SH) circuit (31a) at point a, and is supplied to the normalization circuit (15a) through the switching element Ma during the period of the switch signal ρ2 shown at point E. Then, the signal normalized over two pixel clock periods is applied to the switching element M during the period of the switch signal sl shown at H.
Through a', the sample pulse PI shown at K is held in the sample hold circuit (32a), and written into the liquid crystal cell C connected to the signal #Lx at the phase of the horizontal switch signal 9!5H1 shown at N. Thereafter, similar operations are performed in the circuits with suffixes b and c for each pixel clock, and are repeated by returning to the circuit with the suffix a every three pixel clocks. Therefore, with the apparatus shown in FIG. 8, it is possible to set a processing time twice as long as that of the apparatus shown in FIG.

Note that this device can be applied to a liquid crystal display device using an active matrix using TPT such as amorphous silicon, polysilicon, silicon on sapphire, and organic semiconductor.

In addition, the shift registers (2) 1 (4), (21
j may be provided outside the IC constituting the device.

Furthermore, the display can be applied either point-sequentially or line-sequentially.

According to the above-mentioned liquid crystal display device, since the signal taken out from the liquid crystal cell C is returned to the same liquid crystal cell C, there is no occurrence of blurring of one image, there is no need for special scanning, etc., and the drive circuit etc. can be replaced with the conventional one. can be used as is. Furthermore, since the signal is normalized and the potential of the signal line is reset, the image quality does not deteriorate due to these, and it is now possible to display a good still image for a long time.

Now, the preamplifier α in the liquid crystal display device shown in FIG. 5 is a signal integration type preamplifier, and is actually configured as shown in FIG. 10. In other words, the switching device "Bl p "B2 p...MBm in FIG. and its collector is connected to the collector of a PNP type transistor (4υ). The base of the transistor (4υ is connected to the bias power supply (4tJ), and its emitter is connected to the collector of the resistor 11 through 4
Connected to L source 10B. The middle point of the connection of the transistors (4υ, (42) is grounded through the integrating capacitor 09, and the NPN type transistor (47j is connected to the emitter of the transistor The basis of glance is bias′
! Its collector is connected to the m source B through a resistor 6, and to the base of an hPN type transistor 5. The emitter of the transistor 6υ is grounded through a resistor Q, and is also connected to the input side of a low-pass filter Q, and its collector is connected to the I4 source 1B.

The operation of this preamplifier will be explained with reference to FIG.

FIG. 11A shows pixel switch signals (pixel signal selection pulses) obtained from the output terminals of each stage of the shift register 4 in FIG. 5.
11B shows the input signal Virc (switching element "B 1 , MB 2 y of FIG. 5) supplied to the base of the transistor (42) of FIG.
MB 3...Mlha force)), which is the switch signal J'Hi pg H(i+1)p door ■(i
+2) The pixel signal component Qs is superimposed on the differential node of p.... The coupling between the rising edge and the falling edge of the input signal ■i becomes zero when integrated. Switch signal Hisda1i(i+x) pJ'a(112n,
... Integral pulse ρ that is synchronized with and has a predetermined phase difference
! (See Figure 11C) By controlling the switching confectionery on and off, the signal current i5 is transferred to the capacitor (451
Accumulate and integrate. Note that a direct current Io flows through the emitter of the transistor (41), and a current IO+j5 flows through the emitter of the transistor (6). In this way, a voltage vA corresponding to the signal component Qs is obtained at one end of the capacitor α4. The output voltage VB (see Fig. 11E) corresponding to the accumulated charge of this capacitor (c) is controlled by the switching element (
46) is taken out to the collector of the transistor decoy, received by an emitter follower circuit including a transistor (51), and supplied to the low-pass filter Q. Thus, at the output side of the low-pass filter Q, there is an output signal ■ corresponding to the signal component Qs. ut (see FIG. 11C) is obtained.

D. Problems to be Solved by the Invention Since the prian;' shown in FIG. 10 is composed of discrete components, it occupies a large area and is difficult to adjust. Furthermore, since the output VB obtained at the collector of the transistor decoy itself is pulse-like, it is difficult to average it with a low-pass filter.

In view of these points, the present invention seeks to propose a signal integrating preamplifier that eliminates the need for a low-pass filter, eliminates the need for FA adjustment, and can faithfully reproduce pixel signals in input signals.

E. Means for Solving the Problems The signal integrating preamplifier according to the present invention includes a first integrating circuit Kl to which an input signal formed by superimposing a pixel signal on a differential pulse of a selection pulse that outputs pixel No. 18; , a second integrator circuit connected to the next stage of the first integrator circuit Kl, and a sample hold circuit 3 connected to the second integrator circuit in the next stage of the second integrator circuit Kl, and 1t K2 in the second integration circuit and 3 in the sample and hold circuit are respectively turned on and off by a capacitor (451, 1υt(b7)) and a separate control pulse synchronized with the selection pulse and having a predetermined phase difference and a predetermined pulse width. is controlled by a switching element (4
6), ia, -.

F The input signal is integrated by 1 in the first integrating circuit, the integrated output is integrated again by 2 in the second integrating circuit, and the integrated output is sampled and held in the sample hold circuit by 3, and the input signal is pixel signals are reproduced.

G. Example Hereinafter, with reference to FIG. 1, an example in which the present invention is applied to the above-mentioned liquid crystal display device shown in FIG. 5 will be described in detail. In addition, in FIG. 1, the parts corresponding to FIG. 10 are as follows:
The same reference numerals are given. Switching element MB in Figure 5
l p MB2 g . . . MBm The signal voltage Vi is supplied to the first integrating circuit.

The emitter of the NPN type transistor (6), whose pace is supplied with the signal voltage Vi, is grounded through the resistor (441), and its collector is connected to the PNP type transistor (441).
Connected to the collector of υ. The transistor (4υ pace is connected to the bias source (41J), and its emitter is connected to the power supply 1B through the resistor [having the same resistance value as the resistor ■] (4'5). The transistor (4υ, (Q
The middle point of the connection is grounded through the integrating capacitor 4, and connected to the emitter of the NPN transistor (4) through the series circuit of the switching element 0Q and the resistor (4).The pace of the transistor Cal is connected to the bias power supply (4). The collector is connected to the power supply 1B through a resistor (50J), and is also connected to the input terminal of a buffer for impedance conversion.

The output end of the buffer (b) is connected to the second integration circuit with 2 NPs.
It is connected to the base of an N-type transistor I5η, its emitter is grounded through a resistor (6), and its collector is connected to the collector of a PNP-type transistor state.

The pace of the transistor group is connected to the bias power supply 60), and its collector is connected to the extension +B through a resistor (T). Transistor gloss 1. The connection midpoint of (57) is grounded through the integrating capacitor 6, and the sample and hold circuit is connected to the 3 NPN transistors (connected to the circle pace) and the switching element (connected to the positive power supply through 62). Ru.

The emitter of the transistor diagram is grounded through a resistor, and its collector is connected to the area source B.

The emitter of the transistor connects the pace Ka of the output transistor 6υ through the sample switching element.
dl, and the pace is set for hold. The part surrounded by a circle is a new circuit part that is not present in the preamplifier shown in FIG. 10, and is a replacement for the low-pass filter shown in FIG.

Next, with reference to FIG. 2, the operation of the preamplifier shown in FIG. 1 will be explained. 2A to 2E correspond to FIGS. 11A to 11E. FIG. 2A shows a pixel switch signal (pixel signal selection pulse) uHi obtained from the output terminal of each stage of the shift register 4 in FIG.

Fig. 2B shows the input signal Vif & (switching wire M in Fig. 5) supplied to the pace of the transistor (6) in Fig. 1.
B l 2MB 2 vMB3...obtained from MBゎ), which is the switch signal IH4t OH ('H
at)? The pixel signal component Q is superimposed on the partial pulse of 916H(i+2)°°°.

The coupling between the rising edge and the falling edge of the input signal Vin becomes zero when integrated. Switch signal DHipdaH(i+1
).

The signal current i is stored and stored in the capacitor (49) by controlling the switching element on and off using the integrating pulse 11 (see Fig. 2 Cβ) which is synchronized with the data H(j+2), . . . and has a predetermined phase difference. Integrate.Incidentally, a single current lo flows through the emitter of the transistor H, and the transistor (
s'afiIo+i3 flows to the emitter of 6).

In this way, a voltage vA corresponding to the signal component Qs is obtained at one end of the capacitor (49). The output from the collector of the transistor (5η) is taken out to the collector of the transistor 0 and supplied to the base of the transistor (5η) through the buffer Q, and the output obtained at the collector is applied to the capacitor A to accumulate and integrate the charge. , DaH(i+1).

By controlling the switching element 64 on and off by the precharging pulse 96P synchronized with the falling edge of uu(i0z), . . . , the capacitor 6υ is precharged and the DC potential of the base of the transistor is is held in place. The output voltage Vo (see 211F) obtained at one end of the capacitor 6υ is supplied to the base of the transistor. The switching cable is controlled on/off by the sampling pulse 0s (1 @ 2, see H#), which has the same phase as the precharge pulse DA P, and the output voltage of the emitter of the transistor is sampled to the capacitor Q37. will be held. Thus,
An output voltage VOUT corresponding to the pixel signal component Qs of the input signal vin as shown in FIG. 2 is obtained at the emitter of the transistor 15Jl.

Note that the preamplifier according to the present invention can also be applied to a two-dimensional MO8 imaging device.

H Effects of the Invention According to the invention described above, there is provided a signal integral type that does not require a low-pass filter, does not require adjustment, can be easily integrated into an IC and miniaturized, and can faithfully reproduce pixel signals in an input signal. You can get a preamp.

[Brief explanation of drawings]

FIG. 1 is a circuit showing a signal integrating preamplifier according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the same, and FIG. 3 is a circuit diagram showing a conventional liquid crystal display device.
FIG. 2 is a timing diagram for explaining the timing chart, and FIG. 5 is a circuit diagram showing a previously proposed liquid crystal display device.
FIG. 6 is a timing chart for explaining the same, FIG. 7 is a characteristic curve diagram of the normalization circuit of FIG. 5, and FIG. 8 is a block diagram showing another example of the previously proposed display device.
Figure 9 is a timing chart for explanation), Figure 10
The figure is a circuit diagram showing a specific example of the preamplifier in Figure 5, and Figure 11.
The figure is a time chart for explanation. K1 is a first integrating circuit, K2 is a second integrating circuit, K3 is a sample hold circuit, (c) 2nd, 6η is a capacitor, α61.4a, (f) is a switching element. Dai Kaede Kai Ito 111.7. ' Same as Hidemori Matsukuma Figure 2 Figure 3 Figure 2 Figure 6 Figure 6 Control section 4 Hi circuit control raw curve diagram Figure 7 Figure 8 -111-J station; -1 low -2z iE+= 1st, 2nd, 2nd, 3rd, 3rd, 3rd, 3rd, 3rd, 3rd, 3rd, 2nd

Claims (1)

[Scope of Claims] A first integrating circuit to which an input signal obtained by superimposing a pixel signal on a differential pulse of a selection pulse for reading out a pixel signal is supplied, and the circuit is connected to the next stage of the first integrating circuit. It has a second integrator circuit and a sample hold circuit connected to the next stage of the second integrator circuit, and the first and second integrator circuits and the sample hold circuit each include a capacitor and the selected pulse. 1. A signal-integrating preamplifier comprising a switching element whose on/off state is controlled by each control pulse synchronized with , and having a predetermined phase difference and a predetermined pulse width.