JPS6286569U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention; Fig. 2 is a block diagram of an embodiment of the invention;
The figure is a timing chart of the present invention, FIG. 3 is an enlarged explanatory diagram of delay pulses, drive pulses, and binary signals, and FIG. 4 is a diagram showing states of pulse signals. A: Frequency dividing circuit, B: Delay circuit, C: Light emitting circuit,
D: Light receiving circuit, E: Flip-flop, 1: Oscillator circuit, 2: Current amplification circuit, 3: Light emitting element, 5:
Light receiving element, 6: Level discrimination circuit, 7: D input terminal, 8: Clock input terminal, 9: Clear input terminal,
10: Signal processing circuit.

Claims (1)

[Claims for Utility Model Registration] A drive pulse generation circuit that creates a drive pulse with a predetermined cycle; a delay circuit that delays the drive pulse and creates a light emission pulse in which the drive pulse signal and the pulse signal are superimposed; and the delay. A light emitting circuit that emits light in response to a light emitting pulse created by the circuit; a light receiving circuit that receives a signal emitted by the light emitting element and binarizes it into a high level and a low level; A flip-flop that stores a signal at the falling or rising edge of the driving pulse; and a photoelectric device that prevents malfunctions due to spike noise generated at the rising or falling edge of the pulse included in the emitting signal. Switch.