JPH059660Y2 - - Google Patents

Description

[Detailed description of the invention] [Industrial application field] This invention is used in various industries to inspect the position, shape, etc. using optical signals, and is used to eliminate the effects of spike noise caused by the characteristics of light emitting elements, etc. This invention relates to a photoelectric switch that makes it possible to remove

[Conventional technology]

Conventionally, a light emitting diode (LED) is usually used as the light emitting element of a photoelectric switch, and the light emitting diode (LED) is lit in pulses to project pulsed light.

[Problem that the invention attempts to solve]

However, a light emitting element that receives a driving pulse as input increases the peak value of the pulsed light, so the peak value is
Since a pulse current of 100mA to 500mA is passed through the LED, sharp spike noise is generated at the rise and fall of the output signal due to the response characteristics of this light emitting element to large currents. Even when no reflected light from an object to be detected enters the light-receiving element, the spike noise inevitably mixes into the output of the light-receiving element, causing malfunction.

In view of this problem, the present invention aims to prevent the influence of spike noise by delaying the light emission timing and counting the received light signal at a timing when spike noise does not exist.

[Means for solving problems]

In order to achieve the above object, the present invention has the following configuration.

First, a drive pulse with a predetermined period is created. A delay circuit delays this drive pulse to create a light emission pulse in which the drive pulse signal and the pulse signal are superimposed.

The output state in which the pulse signal of the driving pulse and the pulse signal of the light emitting pulse are superimposed will be explained with reference to FIG.

The pulse signal of the drive pulse and the pulse signal of the light emitting pulse indicated by diagonal lines in the figure can have both high and low levels relative to each other, and the delay circuit detects the rising edge or rising edge of the drive pulse indicated by the arrow in the light emitting pulse signal (i.e., It is the rear edge and the second
The driving pulse is delayed so that there is a falling edge in FIGS.

The light emitting element emits light in response to this light emission pulse and projects a light emission signal. If an object to be detected exists in the projected light range, the light receiving circuit receives the light reflected by the object to be detected, and if no object to be detected exists, the emitted light signal is transmitted. The light receiving circuit receives the reflected light and converts it into an electrical signal, and
Binarize into high level and low level. The flip-flop circuit stores this binary signal at the timing of the trailing edge of the drive pulse (falling if a high level is an effective pulse, rising if a low level is an effective pulse).

Due to the circuit operation described above, the light emission timing is delayed from the drive pulse, and even if the spike noise generated at the rise or fall of the light emission pulse enters the light receiving element, the flip-flop circuit will convert the light emission timing into two values by the light receiving circuit. It is possible to avoid the period in which spike noise is mixed in as the timing for storing the converted signal, and it is possible to store only the signal at the timing normally required to determine the presence or absence of the own light emission pulse. It can be done.

〔Example〕

Embodiments of the present invention will be explained in more detail with reference to FIGS. 1, 2, and 3. Note that an example will be described in which a light emission pulse rises after the drive pulse rises, and then the drive pulse falls.

In FIG. 1, A is a frequency dividing circuit, B is a delay circuit, C is a light emitting circuit, D is a light receiving circuit, and E is a flip-flop.

A frequency divider circuit A divides the clock pulse a of an oscillation circuit 1 that generates a clock pulse a with a constant period to generate a drive pulse b with a predetermined period and an output pulse c whose phase is shifted from this pulse b by a predetermined number of clock pulses. It consists of a counter IC.

The delay circuit B sets the delay time δ to a predetermined time by arranging several stages of inverters in series, is composed of a capacitor and a resistor, or provides a delay cable, and generates a delay pulse d that is a delay of the driving pulse b. is output and supplied to the light emitting circuit C.

The light emitting circuit C includes a current amplifying circuit 2 that current amplifies the supplied delayed pulse d to create a light emitting pulse.
and a light emitting element 3 that repeatedly emits light based on the light emission pulse and projects a light emission signal onto the object 4 to be detected.

The light-receiving circuit D includes a light-receiving element 5 that converts an incident light signal reflected from an object to be detected 4 into an electric signal e, and a light-receiving element 5 that distinguishes this electric signal e into high level and low level and generates a binary signal f. The light receiving element 5 is compactly made of a semiconductor element such as a photodiode. Although the level discrimination circuit 6 is generally composed of a comparator, it may also be composed of an inverter, a Schmitt trigger circuit, etc. to discriminate the electric signal e at a predetermined height. This binary signal f is supplied to a flip-flop E.

The flip-flop E is constituted by a D-type flip-flop having an output pulse c as an input to a clear terminal 9, a binary signal f as an input to a D input terminal 7, and a drive pulse b as an input to a clock input terminal 8. However, as the element of the flip-flop E, other semiconductor elements such as a JK type flip-flop or the like may be used.

The embodiment with the above configuration operates as shown in the timing chart shown in FIG. That is, the oscillation circuit 1 generates a reference clock pulse a, and the reference clock pulse a is frequency-divided by a frequency divider circuit A to generate a drive pulse b with a predetermined period and an output pulse with the same period as the drive pulse b but slightly advanced in phase. generate c. The drive pulse b is input to the delay circuit B and is also supplied to the clock input terminal 8 of the flip-flop E via an inverter, while the output pulse c is supplied to the clear input terminal 9 of the flip-flop circuit E.

The time δ by which the drive pulse b supplied to the delay circuit B is delayed by the delay circuit B will be explained with reference to FIG. That is, the falling edge h of the driving pulse b
The delay time δ is set so that the signal is located within the effective pulse k of the portion of the binary signal f outputted from the level discrimination circuit 6 excluding the noise pulse j, and the delay time δ is set so that the signal f is located within the effective pulse k of the portion of the binary signal f outputted from the level discrimination circuit 6 excluding the noise pulse j. The set value is determined based on the circuit conditions. In this way, drive pulse b
The delayed pulse d, which has been delayed, is supplied to the light emitting circuit C.

The delayed pulse d is generated by the current amplifier circuit 2 with a very large current (100mA) compared to other signals in this circuit.
~500mA), resulting in a light emission pulse (waveform is the same as the delayed pulse d). When the light emitting element 3 emits light in response to this light emitting pulse, sharp spike noise is generated at the rise and fall of the light emitting pulse due to the characteristics of the light emitting element 3. Due to the influence of this spike noise, the light receiving signal output from the light receiving element 5 becomes as shown in FIG. 2e.

This electrical signal e is discriminated into high level and low level by a level discrimination circuit 6, and outputs a binary signal f containing a noise pulse j due to spike noise and an effective pulse k.

This binary signal f is the D of flip-flop E.
The driving pulse b is supplied to the clock input terminal 8 of the flip-flop E through the inverter, so that the drive pulse b is supplied to the clock input terminal 8 of the flip-flop E.
holds the binary signal f input to the D input terminal 7 at the timing of the edge h of the drive pulse b. This held signal is cleared by the output pulse c which is out of phase with the drive pulse b input to the clear terminal 9, so that the output terminal Q of the flip-flop E outputs the output waveform i. be.

In this embodiment, the output pulse i delays the light emission signal by a set time δ from the drive pulse b, so that the falling edge of the drive pulse b is located within the width of the effective pulse k of the binary signal f, and the falling edge of the pulse The light reception signal is held at the falling edge h, and counting is performed when there is no noise pulse j. here,
Counting at the falling edge h of the drive pulse b may be inverted using an inverter or the like and counting at the rising edge. That is, by delaying the light emission pulse drive pulse b so that the pulse signal of the drive pulse b and the pulse signal of the light emission pulse are superimposed, the influence of spike noise at the rise of the output signal e of the light receiving element 5 is removed. be.

Furthermore, there is no need to consider the spike noise that occurs when the light emission signal falls, since it exists while the flip-flop E is holding the signal.

Based on the output signal i created in this manner, the signal processing circuit 10 creates control signals suitable for various industrial equipment, thereby allowing the photoelectric switch to function as an accurate eye.

[Effect of idea]

The present invention as described above makes it possible to prevent malfunctions due to the effects of pike noise generated during light emission by delaying the light emission signal by a predetermined time from the counting signal. In addition, when the circuit is constructed using semiconductors, everything other than the light emitting element and the light receiving element can be manufactured on one chip, making it possible to mass produce and reduce costs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention; Fig. 2 is a block diagram of an embodiment of the invention;
The figure is a timing chart of the present invention, FIG. 3 is an enlarged explanatory diagram of delay pulses, drive pulses, and binary signals, and FIG. 4 is a diagram showing states of pulse signals. A... Frequency divider circuit, B... Delay circuit, C... Light emitting circuit, D... Light receiving circuit, E... Flip-flop, 1... Oscillator circuit, 2... Current amplifier circuit, 3...
... Light receiving element, 5 ... Light receiving element, 6 ... Level discrimination circuit, 7 ... D input terminal, 8 ... Clock input terminal, 9 ... Clear input terminal, 10 ... Signal processing circuit.

Claims (1)

[Claims for Utility Model Registration] A drive pulse generation circuit that generates a drive pulse with a predetermined cycle; a delay circuit that delays the drive pulse and creates a light emission pulse that is superimposed on the drive pulse; a light-emitting circuit that emits light in response to a light-emitting pulse; a light-receiving circuit that receives a signal emitted by the light-emitting circuit and binarizes it into a high level and a low level; A photoelectric switch comprising: a flip-flop that stores timing at the trailing edge of a pulse;