JPS61269522A - Photoelectric switch - Google Patents

Photoelectric switch

Info

Publication number
JPS61269522A
JPS61269522A JP11245585A JP11245585A JPS61269522A JP S61269522 A JPS61269522 A JP S61269522A JP 11245585 A JP11245585 A JP 11245585A JP 11245585 A JP11245585 A JP 11245585A JP S61269522 A JPS61269522 A JP S61269522A
Authority
JP
Japan
Prior art keywords
circuit
light
output
signal
waveform shaping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11245585A
Other languages
Japanese (ja)
Inventor
Norio Onchi
恩地 紀夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP11245585A priority Critical patent/JPS61269522A/en
Publication of JPS61269522A publication Critical patent/JPS61269522A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled

Abstract

PURPOSE:To prevent generation of mis-detection by opening the 2nd gate circuit at a time zone where no light is irradiated from a light projection section and using an integration circuit to integrate a light signal during the zone thereby inhibiting the detection output when the output level reaches a prescribed value. CONSTITUTION:A light projection section 13 and a photodetector section 14 are provided to a photoelectric switch, a signal having a prescribed frequency from an oscillation circuit 11 is frequency-divided by a frequency division circuit 12, clocks a, b being at H level not at the same time, the light emitting section 13 is driven by a pulse of the clock (a) and irradiated to a detection region 24. The light signal from the region 24 is received by the light receiving section 14, amplified (15) into a prescribed level and fed to the 1st and 2nd gate circuits 16, 17. The circuit 17 is opened during the clock (b) when the light projection section 13 does not irradiate any light. Then the optical signal obtained during this period is integrated by an integration detection circuit 19 and a waveform shaping circuit 21, an inhibition signal is fed to an inhibition circuit 22 while regarding it as an external disturbance light so as to prevent mis-output of the detection signal from the region 24 through the circuit 16.

Description

【発明の詳細な説明】 〔発明の分野〕 本発明は光電スイッチに関し、特に外乱光による誤動作
を防止した光電スイッチに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a photoelectric switch, and more particularly to a photoelectric switch that prevents malfunctions caused by ambient light.

〔発明の概要〕[Summary of the invention]

本発明による光電スイッチは、投光素子をパル大信号に
よって駆動すると共にその駆動タイミングと異なるタイ
ミングで得られる受光信号を積分し、積分レベルが所定
値以上に達したときに外部より外乱光が連続して加えら
れたものとして物体の検知出力を停止するようにしてい
る。こうすれば誤った信号によって光電スイッチが物体
検知信号を出力することがなく、光電スイッチの信願性
を向上させることができる。
The photoelectric switch according to the present invention drives a light emitting element with a large pulse signal and integrates a light reception signal obtained at a timing different from the driving timing, and when the integration level reaches a predetermined value or more, disturbance light from the outside is continuously generated. The detection output of the object is stopped as if the object was added to the object. In this way, the photoelectric switch will not output an object detection signal due to an erroneous signal, and the reliability of the photoelectric switch can be improved.

〔従来技術とその問題点〕[Prior art and its problems]

従来の光電スイッチでは、発光素子をクロックパルスを
用いて駆動し物体からのパルス状の受光信号を積分検波
回路を用いて連続した受波レベル信号に変換すると共に
、ノイズ等による誤動作を防止するため積分回路の時定
数を例えばクロックパルスの5周期分に設定し、それ以
下のノイズを除去して誤動作を防止している。
In conventional photoelectric switches, the light emitting element is driven using clock pulses, and the pulsed light reception signal from the object is converted into a continuous reception level signal using an integral detection circuit, and at the same time, it is used to prevent malfunctions due to noise, etc. The time constant of the integrating circuit is set to, for example, five cycles of clock pulses, and noise below that value is removed to prevent malfunction.

第4図はこのような従来の反射型光電スイッチのブロッ
ク図であり、第5図はそのa ’−eの各部の波形図で
ある。この光電スイッチではクロックパルスの発振回路
1の出力によって投光部2を駆動すると共に受光部3の
受光出力を増幅し、駆動クロックと同一のタイミングで
開閉するゲート回路5に与えて投光時に得られる受光信
号のみを積分検波回路に与えてノイズの混入を防止して
いる。
FIG. 4 is a block diagram of such a conventional reflective photoelectric switch, and FIG. 5 is a waveform diagram of each part of the switch a' to e. In this photoelectric switch, the output of the clock pulse oscillation circuit 1 drives the light emitting part 2, and the received light output of the light receiving part 3 is amplified and applied to the gate circuit 5, which opens and closes at the same timing as the driving clock. Only the received light signal is fed to the integral detection circuit to prevent noise from entering.

そしてゲート回路5を通過した信号を積分検波回路6に
与え、その出力を所定レベルで弁別して物体検知信号を
得るようにしている。このような光電スイッチでは連続
して外乱光が加わった場合には第5図(C1,(dlに
示すように積分レベルが閾値を越えて光電スイッチが誤
動作することがある。このような誤動作の可能性は積分
回路の時定数を長くすることによって少なくすることが
できるが、あまり長くすれば光電スイツチの応答性が低
下してしまう。従って従来の光電1.スイ・ソチにおい
ては、検出物体が存在しないときに受光部に外乱光が連
続して照射されたときに□誤動作を完全に防止すること
ができないという問題点があった。
The signal passed through the gate circuit 5 is then applied to an integral detection circuit 6, and its output is discriminated at a predetermined level to obtain an object detection signal. When disturbance light is continuously applied to such a photoelectric switch, the integral level may exceed the threshold and the photoelectric switch may malfunction, as shown in Figure 5 (C1, (dl). This possibility can be reduced by lengthening the time constant of the integrating circuit, but if it is made too long, the responsiveness of the photoelectric switch will decrease.Therefore, in the conventional photoelectric switch 1. There was a problem in that it was not possible to completely prevent malfunctions when the light receiving section was continuously irradiated with disturbance light when the light receiving section was not present.

〔発明の目的〕[Purpose of the invention]

本発明はこのような従来の光電スイッチの問題点を解消
するためになされまたものであって、積分回路の時定数
をあまり長くすることなく、応答性が速く外乱光に基づ
く誤動作を防止することができる光電スイッチを提供す
ることを目的とする。
The present invention has been made in order to solve the problems of the conventional photoelectric switch, and provides a fast response and prevents malfunctions caused by ambient light without making the time constant of the integrating circuit too long. The purpose is to provide a photoelectric switch that can.

〔発明の構成と効果〕[Structure and effects of the invention]

本発明は投光部及び受光部を有し、投光部をパルス駆動
して物体を検出する光電スイッチであって、受光部より
受光信号が与えられ投光部の駆動信号に対応するゲート
タイミングを有する第1のゲート回路と、受光部より受
光信号が与えられ投光部のパルス駆動信号と異なるゲー
トタイミングを有する第2のゲート回路と、第1.第2
のゲート回路の出力を夫々積分検波する第1.第2の積
分検波回路と、第1.第2の積分検波回路の出力を夫々
所定の閾値で弁別して波形整形する第1゜第2の波形整
形回路と、第1の波形整形回路出力に基づいて物体検知
信号を出力すると共に、第2の波形整形回路の出力によ
り第1の波形整形回路出力を禁止する禁止回路と、を有
することを特徴とするものである。
The present invention is a photoelectric switch that has a light projecting section and a light receiving section, and detects an object by driving the light projecting section in pulses, and the gate timing corresponds to the drive signal of the light projecting section when a light reception signal is given from the light receiving section. a first gate circuit having a first gate circuit; a second gate circuit to which a light receiving signal is applied from a light receiving section and having a gate timing different from a pulse drive signal of the light projecting section; Second
The first one integrally detects the output of each gate circuit. a second integral detection circuit; a first integral detection circuit; A first waveform shaping circuit that discriminates and shapes the output of the second integral detection circuit by a predetermined threshold value, respectively; and a second waveform shaping circuit that outputs an object detection signal based on the output of the first waveform shaping circuit; and a prohibition circuit that prohibits the output of the first waveform shaping circuit based on the output of the first waveform shaping circuit.

このような特徴を有する本発明によれば、投光部より光
を照射しない時間帯に第2のゲート回路を開放しその間
に得られる光信号を積分回路により積分し、その出力レ
ベルが所定以上に達すれば連続して外乱光が加わったも
のとして検知出力を禁止する′ようにしている。このた
め誤って物体検知出力を出す恐れがなくなり、応答時間
を長くすることなく物体検出の信頼性を向上させること
が可能である。
According to the present invention having such characteristics, the second gate circuit is opened during the time period when no light is emitted from the light projecting section, and the optical signal obtained during that time is integrated by the integrating circuit, and the output level thereof is equal to or higher than a predetermined level. When it reaches , it is assumed that disturbance light has been continuously added and the detection output is prohibited. This eliminates the possibility of erroneously outputting an object detection output, and it is possible to improve the reliability of object detection without increasing the response time.

〔実施例の説明〕[Explanation of Examples]

(実施例の全体構成) 第1図は本発明を拡散反射型の光電スイッチに適用した
場合の一実施例を示すブロック図である。
(Overall Configuration of Embodiment) FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a diffuse reflection type photoelectric switch.

本図において発振回路11は所定の周波数の信号を発生
する発振器であり、その出力は分周回路12に与えられ
る。分周回路12は同一の周期を有し同時に“H″レベ
ルならない2つのクロック信号を発生するものであり、
その一方のクロック信号を投光部13に与える。投光部
13は発光ダイオード等の発光素子を有し、こうして与
えられたクロック信号に基づいて断続的に発光素子を発
光させて検知領域に照射する。受光部14は検出物体か
らの反射光を受光するものであって、その出力を増幅回
路15に伝える。増幅回路15は反射波信号を所定レベ
ルに増幅してその出力を2つのゲート回路16.17に
伝える。ゲート回路16は分周回路12より投光部13
の駆動信号と同一のクロック信号が与えられ、ゲート回
路17には分周回路12の他方のクロック信号が与えら
れている。そして夫々そのタイミングでゲートを開放す
ることによってゲート回路16より投光部13の駆動タ
イミングで与えられる受光信号を通過させて積分検波回
路18に与え、ゲート回路17はそれ以外のタイミ・ン
グで与えられる受光信号を積分検波回路19に与える。
In the figure, an oscillation circuit 11 is an oscillator that generates a signal of a predetermined frequency, and its output is given to a frequency dividing circuit 12. The frequency dividing circuit 12 generates two clock signals that have the same period and do not reach the "H" level at the same time.
One of the clock signals is given to the light projector 13. The light projector 13 has a light emitting element such as a light emitting diode, and intermittently causes the light emitting element to emit light based on the clock signal thus applied, and irradiates the detection area. The light receiving section 14 receives reflected light from the detection object, and transmits its output to the amplifier circuit 15. The amplifier circuit 15 amplifies the reflected wave signal to a predetermined level and transmits its output to two gate circuits 16 and 17. The gate circuit 16 is connected to the light emitting unit 13 by the frequency dividing circuit 12.
The same clock signal as the drive signal of is given to the gate circuit 17, and the other clock signal of the frequency dividing circuit 12 is given to the gate circuit 17. By opening the gates at the respective timings, the gate circuit 16 allows the light reception signal given at the driving timing of the light projecting section 13 to pass through and gives it to the integral detection circuit 18, and the gate circuit 17 gives it at other timings. The received light signal is given to an integral detection circuit 19.

積分検波回路1B。Integral detection circuit 1B.

19は出力信号を受光量に対応したレベルの信号に変換
するものである。積分検波回路18.19の夫々の出力
は波形整形回路20.’21に与えられる。波形整形回
路20.21は夫々閾値ThLTh3を越えた入力が与
えられたときに出力を出し、夫々閾値Th2 (<Th
1) 、 Th4 (<Th3)以下となったときに出
力を停止することにより入力信号を二値信号に変換する
整形回路であり、その出力は夫々禁止回路22に与えら
れる。禁止回路22には更に分周回路12より投光部1
3の駆動信号と同一のクロック信号が与えられる。禁止
回路22は波形整形回路21より出力が与えられている
ときに波形整形回路20の出力を禁止すると共に、出力
が禁止されていないときに波形整形回路20の出力を分
周回路12のクロックに同期させて外部に与えるもので
ある。又波形整形回路21の出力端には外部より雑音が
加わったことを示す表示灯23が接続されている。
Reference numeral 19 converts the output signal into a signal with a level corresponding to the amount of received light. The respective outputs of the integral detection circuits 18 and 19 are sent to the waveform shaping circuit 20. Given in '21. The waveform shaping circuits 20 and 21 each output an output when an input exceeding the threshold ThLTh3 is given, and the respective waveform shaping circuits 20 and 21 output an output when the input exceeds the threshold Th2 (<Th
1) This is a shaping circuit that converts the input signal into a binary signal by stopping the output when it becomes less than or equal to Th4 (<Th3), and its output is given to the inhibition circuit 22, respectively. The prohibition circuit 22 is further connected to the light emitter 1 from the frequency dividing circuit 12.
The same clock signal as the drive signal of No. 3 is given. The prohibition circuit 22 prohibits the output of the waveform shaping circuit 20 when the output is given from the waveform shaping circuit 21, and also uses the output of the waveform shaping circuit 20 as the clock of the frequency dividing circuit 12 when the output is not prohibited. It is synchronized and given to the outside. Further, an indicator light 23 is connected to the output end of the waveform shaping circuit 21 to indicate that noise has been added from the outside.

(禁止回路の構成) 次に禁止回路22の詳細な構成について第2図を参照し
つつ説明する。端子31には波形整形回路20の出力端
が接続され、波形整形出力が端子31を介してD型フリ
ップフロップ32に与えられる。D型フリップフロップ
32は出力の立上りをクロック信号と同期させるための
フリップフロップであり、そのQ出力はD型フリップフ
ロップ33、アンド回路34及びノア回路35に与えら
れる。又端子36より分周回路12のクロック信号が2
つのD型フリップフロップのクロック入力端子に与えら
れている。D型フリップフロップ33は出力信号の立下
りをクロックに同期させるためのフリップフロップであ
り、そのQ出力はアンド回路34及びノア回路35に与
えられる。更に波形整形回路21の出力は端子37を介
してインバータ38に与えられ、インバータ38の出力
が2つのアンド回路39.40に与えられる。インバー
タ38はこれらのアンド回路39,4.0をゲート回路
として動作させるものである。アンド回路39.40の
出力は夫々RSフリップフロップ410セント及びリセ
ット入力端子に与えられ、RSフリップフロップ41よ
り物体検出出力が外部に出力される。
(Configuration of Prohibition Circuit) Next, the detailed configuration of the prohibition circuit 22 will be described with reference to FIG. 2. The output terminal of the waveform shaping circuit 20 is connected to the terminal 31, and the waveform shaping output is given to the D-type flip-flop 32 via the terminal 31. The D-type flip-flop 32 is a flip-flop for synchronizing the rise of its output with a clock signal, and its Q output is given to a D-type flip-flop 33, an AND circuit 34, and a NOR circuit 35. Also, the clock signal of the frequency divider circuit 12 is input from the terminal 36 to 2.
This signal is applied to the clock input terminals of two D-type flip-flops. The D-type flip-flop 33 is a flip-flop for synchronizing the falling edge of the output signal with a clock, and its Q output is given to an AND circuit 34 and a NOR circuit 35. Further, the output of the waveform shaping circuit 21 is applied to an inverter 38 via a terminal 37, and the output of the inverter 38 is applied to two AND circuits 39 and 40. Inverter 38 operates these AND circuits 39 and 4.0 as a gate circuit. The outputs of the AND circuits 39 and 40 are applied to an RS flip-flop 410 cent and a reset input terminal, respectively, and an object detection output is output from the RS flip-flop 41 to the outside.

(本実施例の動作) 次に本実施例の動作について波形図を参照しつつ説明す
る。′第3図fa)〜(nlは第1図及び第2図にa 
−nで示す各部の波形の波形図である。分周回路12は
第3図(al、 (blに示す2つのクロック信号を発
生しており、第3図(a)のクロック信号によって投光
部13が駆動される。従って時刻t1以後第1図に示す
ように検出物体24が存在する場合には反射光がこのク
ロック信号に同期して得られ、この信号はそのままゲー
ト回路16を通過して第3図(C1,(d)に示すよう
に積分検波回路18に伝えられる。積分検波回路18は
第3図(e)に示すように入力信号に基づいて積分を開
始し、連続して受光信号が与えられればそのレベルが徐
々に上昇する。従って積分出力が閾値レベルThlを越
える時刻t2には波形整形回路20より第3図(flに
示すように出力が与えられる。そして反射光を受光しな
くなり、積分出力が閾値Th2以下となれば出力が停止
する。
(Operation of this embodiment) Next, the operation of this embodiment will be explained with reference to waveform diagrams. 'Figure 3 fa) to (nl are a in Figures 1 and 2.
It is a waveform diagram of the waveform of each part indicated by -n. The frequency dividing circuit 12 generates two clock signals shown in FIG. As shown in the figure, when the detection object 24 is present, reflected light is obtained in synchronization with this clock signal, and this signal passes through the gate circuit 16 as it is, as shown in Figure 3 (C1, (d)). The signal is transmitted to the integral detection circuit 18.The integral detection circuit 18 starts integrating based on the input signal as shown in FIG. Therefore, at time t2 when the integrated output exceeds the threshold level Thl, the waveform shaping circuit 20 provides an output as shown in FIG. Output stops.

又第3図(C)に示すように時刻t3に投光クロック信
号と同期しない光信号が受光部14に加わってもゲート
回路16を通過しないため、波形整形回路20に信号が
伝えられない。しかしこのときゲート回路17が開放し
ているので、第3図(g+、 (′h1に示すように積
分検波回路19に信号が伝えられて積分が行われる。同
様にして時刻t4以後連続して受光部14に外乱光が加
わったものとすると、増幅回路15よりゲート回路16
.ITの双方を通過して第3図(d)、 (g)に示す
ように積分検波回路18.19に伝えられる。従って積
分検波回路18.19の出力はいずれも徐々に増加し第
3図(h) 。
Further, as shown in FIG. 3(C), even if an optical signal that is not synchronized with the light projection clock signal is applied to the light receiving section 14 at time t3, it does not pass through the gate circuit 16, so that the signal is not transmitted to the waveform shaping circuit 20. However, since the gate circuit 17 is open at this time, the signal is transmitted to the integral detection circuit 19 and integration is performed as shown in FIG. Assuming that disturbance light is added to the light receiving section 14, the amplifier circuit 15 and the gate circuit 16
.. It passes through both ITs and is transmitted to integral detection circuits 18 and 19 as shown in FIGS. 3(d) and (g). Therefore, the outputs of the integral detection circuits 18 and 19 gradually increase as shown in FIG. 3(h).

(11に示すように閾値Th3を越える時刻t5に波形
整形回路21より出力が禁止回路22に与えられる。
(As shown in 11, the output from the waveform shaping circuit 21 is given to the inhibition circuit 22 at time t5 when the threshold value Th3 is exceeded.

又同様にして第3図(el、 (flに示すように時刻
t6に積分出力の上昇により波形整形回路20より禁止
回路22に物体検知出力が伝えられる6又時刻t7゜t
8には夫々積分出力の低下によって禁止回路22への入
力が停止する。ここで積分検波回路19の時定数を立上
りには積分検波回路18より速く、立下りは積分検波回
路18より遅くなるようにしておけば、第3図(e)、
 (1)に示すように波形整形回路21の出力時間は波
形整形回路20の出力時間を含むようにすることが可能
となる。
Similarly, as shown in FIG. 3 (el, (fl), the object detection output is transmitted from the waveform shaping circuit 20 to the inhibition circuit 22 due to the increase in the integral output at time t6, at time t7゜t.
8, the input to the inhibition circuit 22 is stopped due to a decrease in the integral output. If the time constant of the integral detection circuit 19 is set so that the rising time is faster than that of the integral detecting circuit 18 and the falling time is slower than that of the integral detecting circuit 18, as shown in FIG. 3(e),
As shown in (1), the output time of the waveform shaping circuit 21 can be made to include the output time of the waveform shaping circuit 20.

さて禁止回路22のフリップフロップ32.33には第
3図(alのクロック信号が加えられている。
Now, the clock signal shown in FIG. 3 (al) is applied to the flip-flops 32 and 33 of the inhibit circuit 22.

従って波形整形回路20の出力に基づいて第3図[kl
、 +11に示すようにアンド回路34及びノア回路3
5よりクロック信号に同期した出力が得られる。
Therefore, based on the output of the waveform shaping circuit 20, FIG.
, +11, AND circuit 34 and NOR circuit 3
5, an output synchronized with the clock signal can be obtained.

このとき波形整形回路21より出力が加えられなければ
これらの信号は第3図(ml、 (nlに示すようにそ
のままアンド回路39.40を通過してRSフリップフ
ロップに与えられるので、第3図01に示すように物体
検知出力となって外部に出力される。
At this time, if the output from the waveform shaping circuit 21 is not applied, these signals pass through the AND circuit 39 and 40 as shown in FIG. As shown in 01, the object detection output is output to the outside.

しかしながら波形整形回路20の出力によって第3図(
kl、 Tl)に示すようにクロック信号に同期する出
力が得られても、波形整形回路21より禁止入力信号が
与えられれば、アンド回路39.40が閉じるためRS
フリップフロップ41に出力が伝えられない。従って第
3図+J)に示すように物体検知出力は得られず誤って
出力を出す恐れがな(なる。又波形整形回路21の出力
は表示灯23に与えられ、外乱光が加わって物体が検知
できない状態であることが表示される。
However, due to the output of the waveform shaping circuit 20, as shown in FIG.
Even if an output synchronized with the clock signal is obtained as shown in (kl, tl), if an inhibit input signal is given from the waveform shaping circuit 21, the AND circuits 39 and 40 are closed, so the RS
No output is transmitted to the flip-flop 41. Therefore, as shown in Fig. 3+J), no object detection output is obtained, and there is no possibility of erroneously outputting the output.Also, the output of the waveform shaping circuit 21 is given to the indicator light 23, and the disturbance light is added to prevent the object from being detected. It will be displayed that it cannot be detected.

尚本実施例では、積分検波回路19の積分特定数は立上
りでは積分検波回路18より短く立下りは積分検波回路
18より長くするように設定しているが、波形整形回路
21のスレッシュホールドt、zへJtzTh3. T
h4ヲ波形整形回路20のスレッシュホールドレベルT
hl、 Th2より夫々わずかに低くなるように設定し
、外乱光を検出して出力を確実に禁止できるようにする
ことも可能である。
In this embodiment, the specific number of integrals of the integral detection circuit 19 is set to be shorter than the integral detection circuit 18 at the rising edge and longer than the integral detection circuit 18 at the falling edge, but the threshold t of the waveform shaping circuit 21, to z JtzTh3. T
h4ヲ Waveform shaping circuit 20 threshold level T
It is also possible to set them to be slightly lower than hl and Th2, respectively, so that disturbance light can be detected and the output can be reliably inhibited.

又本実施例は拡散反射型の光電スイッチについて説明し
ているが、第1のゲート回路の出力が与えられないとき
にクロック信号を積分するようにして物体検知出力とす
る場合には、透過型や回帰反射型の光電スイッチに本発
明を適用することも可能である。
Furthermore, although this embodiment describes a diffuse reflection type photoelectric switch, if the clock signal is integrated to provide an object detection output when the output of the first gate circuit is not given, a transmission type photoelectric switch is used. It is also possible to apply the present invention to a retroreflective type photoelectric switch.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による光電スイッチの一実施例を示すブ
ロック図、第2図はその禁止回路の詳細な構成を示す回
路図、第3図は本実施例の各部の波形を示す波形図、第
4図は従来の光電スイッチの一例を示すブロック図、第
5図はその各部の波形図である。 Q 1 、 11−−−−−−一発振回路  2.13−−
−−−−一投光部3 、 111−−−−−−一受光部
  5,16.17−・−ゲート回路  6. 18.
 1 !1l−−−−−−−積分検波回路7 、 20
 、 21−−−−−−一波形整形回路  12−−−
−−一分周回路  22−・−−−−一禁止回路  3
2.33−・−り型フリップフロップ  41 =−−
−−−−RSフリップフロップ
FIG. 1 is a block diagram showing an embodiment of the photoelectric switch according to the present invention, FIG. 2 is a circuit diagram showing the detailed configuration of the inhibition circuit, and FIG. 3 is a waveform diagram showing waveforms of various parts of this embodiment. FIG. 4 is a block diagram showing an example of a conventional photoelectric switch, and FIG. 5 is a waveform diagram of each part thereof. Q1, 11-----One oscillation circuit 2.13--
-----One light emitting section 3, 111---One light receiving section 5, 16.17---Gate circuit 6. 18.
1! 1l --- Integral detection circuit 7, 20
, 21------One waveform shaping circuit 12------
---1 frequency division circuit 22-・-----1 inhibition circuit 3
2.33−・− type flip-flop 41 =−−
---RS flip-flop

Claims (4)

【特許請求の範囲】[Claims] (1)投光部及び受光部を有し、投光部をパルス駆動し
て物体を検出する光電スイッチであって、前記受光部よ
り受光信号が与えられ投光部の駆動信号に対応するゲー
トタイミングを有する第1のゲート回路と、 受光部より受光信号が与えられ前記投光部のパルス駆動
信号と異なるゲートタイミングを有する第2のゲート回
路と、 前記第1、第2のゲート回路の出力を夫々積分検波する
第1、第2の積分検波回路と、 前記第1、第2の積分検波回路の出力を夫々所定の閾値
で弁別して波形整形する第1、第2の波形整形回路と、 前記第1の波形整形回路出力に基づいて物体検知信号を
出力すると共に、前記第2の波形整形回路の出力により
前記第1の波形整形回路出力を禁止する禁止回路と、を
有することを特徴とする光電スイッチ。
(1) A photoelectric switch that has a light projecting section and a light receiving section and detects an object by driving the light projecting section in pulses, and a gate that receives a light reception signal from the light receiving section and corresponds to a driving signal for the light projecting section. a first gate circuit having a timing; a second gate circuit to which a light reception signal is applied from a light receiving section and having a gate timing different from a pulse drive signal of the light projecting section; and outputs of the first and second gate circuits. first and second integral detection circuits that perform integral detection, respectively; first and second waveform shaping circuits that discriminate and shape the outputs of the first and second integral detection circuits using predetermined threshold values, respectively; A prohibition circuit that outputs an object detection signal based on the output of the first waveform shaping circuit and prohibits the output of the first waveform shaping circuit based on the output of the second waveform shaping circuit. photoelectric switch.
(2)前記第2の積分検波回路の時定数は、前記第1の
積分検波回路より立上り時間を短く、立下り時間を長く
設定したことを特徴とする特許請求の範囲第1項記載の
光電スイッチ。
(2) The time constant of the second integral detection circuit is set such that the rise time is shorter and the fall time is longer than that of the first integral detection circuit. switch.
(3)前記第2の波形整形回路の閾値は、前記第1の波
形整形回路の閾値より低く設定したことを特徴とする特
許請求の範囲第1項記載の光電スイッチ。
(3) The photoelectric switch according to claim 1, wherein the threshold value of the second waveform shaping circuit is set lower than the threshold value of the first waveform shaping circuit.
(4)前記第2の波形整形回路の出力に基づいて動作す
る表示器を有することを特徴とする特許請求の範囲第1
項記載の光電スイッチ。
(4) Claim 1, further comprising a display that operates based on the output of the second waveform shaping circuit.
Photoelectric switch described in section.
JP11245585A 1985-05-24 1985-05-24 Photoelectric switch Pending JPS61269522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11245585A JPS61269522A (en) 1985-05-24 1985-05-24 Photoelectric switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11245585A JPS61269522A (en) 1985-05-24 1985-05-24 Photoelectric switch

Publications (1)

Publication Number Publication Date
JPS61269522A true JPS61269522A (en) 1986-11-28

Family

ID=14587064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11245585A Pending JPS61269522A (en) 1985-05-24 1985-05-24 Photoelectric switch

Country Status (1)

Country Link
JP (1) JPS61269522A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380078A2 (en) * 1989-01-25 1990-08-01 Omron Corporation Photoelectric switch
JPH0476487A (en) * 1990-07-18 1992-03-11 Nec Corp Laser alarm device
JP2002130142A (en) * 2000-10-25 2002-05-09 San-Ei Faucet Mfg Co Ltd Automatic water feeding device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0380078A2 (en) * 1989-01-25 1990-08-01 Omron Corporation Photoelectric switch
JPH0476487A (en) * 1990-07-18 1992-03-11 Nec Corp Laser alarm device
JP2002130142A (en) * 2000-10-25 2002-05-09 San-Ei Faucet Mfg Co Ltd Automatic water feeding device
JP4570758B2 (en) * 2000-10-25 2010-10-27 株式会社三栄水栓製作所 Automatic water supply device

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