JPS6285013U - - Google Patents

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Publication number
JPS6285013U
JPS6285013U JP1985176809U JP17680985U JPS6285013U JP S6285013 U JPS6285013 U JP S6285013U JP 1985176809 U JP1985176809 U JP 1985176809U JP 17680985 U JP17680985 U JP 17680985U JP S6285013 U JPS6285013 U JP S6285013U
Authority
JP
Japan
Prior art keywords
bias
avalanche photodiode
photodiode
circuit
bias circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985176809U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985176809U priority Critical patent/JPS6285013U/ja
Publication of JPS6285013U publication Critical patent/JPS6285013U/ja
Pending legal-status Critical Current

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  • Amplifiers (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Optical Communication System (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案実施例のアバランシエフオトダ
イオードのバイサス回路図、第２図は従来の一例
を示すバイアス回路図である。 １……高電圧発生回路、２……トランジスタ、
３，１１……ダイオード、４，５……抵抗器、６
……アバランシエフオトダイオード、７……コン
デンサ、８……抵抗器、９……増幅器、１０……
カソード端子（ＤＣバイアス印加点）。 FIG. 1 is a bias circuit diagram of an avalanche photodiode according to an embodiment of the present invention, and FIG. 2 is a bias circuit diagram showing a conventional example. 1...High voltage generation circuit, 2...Transistor,
3, 11...Diode, 4, 5...Resistor, 6
...Avalanche photodiode, 7...Capacitor, 8...Resistor, 9...Amplifier, 10...
Cathode terminal (DC bias application point).

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高電圧発生回路から抵抗器を通してアノードが
接地されたアバランシエフオトダイオードにＤＣ
バイアス電圧を印加するアバランシエフオトダイ
オードのバイアス回路において、前記ＤＣバイア
ス印加点に、さらにベースとコレクタにＤＣ正電
圧が印加きれたトランジスタのエミツタがダイオ
ードを介して接続されていることを特徴とするア
バンシエフオトダイオードのバイアス回路。 DC from the high voltage generation circuit is passed through a resistor to an avalanche photodiode whose anode is grounded.
A bias circuit for an avalanche photodiode that applies a bias voltage is characterized in that the DC bias application point is further connected to the emitter of a transistor to which a DC positive voltage has been applied to the base and collector via a diode. Bias circuit for avancier photodiode.
JP1985176809U 1985-11-19 1985-11-19 Pending JPS6285013U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985176809U JPS6285013U (en) 1985-11-19 1985-11-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985176809U JPS6285013U (en) 1985-11-19 1985-11-19

Publications (1)

Publication Number Publication Date
JPS6285013U true JPS6285013U (en) 1987-05-30

Family

ID=31117415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985176809U Pending JPS6285013U (en) 1985-11-19 1985-11-19

Country Status (1)

Country Link
JP (1) JPS6285013U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250534A (en) * 1988-08-11 1990-02-20 Nec Corp Apd bias voltage control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0250534A (en) * 1988-08-11 1990-02-20 Nec Corp Apd bias voltage control circuit

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