JPS6284547A - Complementary type mos semiconductor device - Google Patents
Complementary type mos semiconductor deviceInfo
- Publication number
- JPS6284547A JPS6284547A JP60224411A JP22441185A JPS6284547A JP S6284547 A JPS6284547 A JP S6284547A JP 60224411 A JP60224411 A JP 60224411A JP 22441185 A JP22441185 A JP 22441185A JP S6284547 A JPS6284547 A JP S6284547A
- Authority
- JP
- Japan
- Prior art keywords
- region
- well
- high concentration
- channel
- source region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000000295 complement effect Effects 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 230000004888 barrier function Effects 0.000 description 3
- 244000145845 chattering Species 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は相補型ＭＯＳ半導体装置、特に、優れたラッチ
アップ耐性を有する相補型ＭＯＳ＃−導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a complementary MOS semiconductor device, and particularly to a complementary MOS #-conductor device having excellent latch-up resistance.
（従来の技術〕
第２図は従来の相補型ＭＯＳ半導体装置を表わす断面図
であり、図中、ｌはＮ型半導体基板を表わしており、該
基板１の１表面部には、Ｐ型のウェル２が画成されてい
る。ウェル外の基板１にはＰ型のソース領域およびドレ
イン領域か形成されＰチャンネル９Ｍ０Ｓトランジスタ
が形成されているが省略ぼれている。(Prior Art) FIG. 2 is a cross-sectional view showing a conventional complementary MOS semiconductor device, in which l represents an N-type semiconductor substrate, and one surface of the substrate 1 has a P-type semiconductor substrate. A well 2 is defined.A P-type source region and a drain region are formed in the substrate 1 outside the well, and a P-channel 9M0S transistor is formed therein, but these are omitted.
ウェル２内には、Ｎ型のソース領域３およびドレイン領
域４が形成されており、該ソース領域３とドレイン領域
４との間のチャンネル上には誘電膜を介してゲート５が
対向し、これらでＮチャンネルｍＭＯｓトランジスタを
構成している。In the well 2, an N-type source region 3 and a drain region 4 are formed, and a gate 5 faces the channel between the source region 3 and the drain region 4 with a dielectric film interposed therebetween. constitutes an N-channel mMOS transistor.
６はフィールド酸化膜であり、ＭＯＳトランジスタ上を
被う絶縁膜７には、スルーホールが穿設され、該スルー
ホールを通してソース領域３およびドレイン領域４に電
極８．９がそれぞれ接触している。Reference numeral 6 denotes a field oxide film, and through holes are formed in the insulating film 7 covering the MOS transistor, and electrodes 8 and 9 are in contact with the source region 3 and the drain region 4 through the through holes, respectively.
】０（″、＋１．ウェル２より高不純物濃度のＰ型領域
であり、該Ｐ型領域１０はソース領域３の側方に隣設し
て設けられ、電極８に接触しているので、ウェル２はソ
ース領域３と略々同電位に保たれている。]0('', +1. This is a P-type region with a higher impurity concentration than well 2. The P-type region 10 is provided adjacent to the side of source region 3 and is in contact with electrode 8, so that the well 2 is maintained at substantially the same potential as the source region 3.
（従来技術の問題点）
上記構成に係わる従来の相補型ＭＯＳトランジスタにあ
っては、図示していないＰチャンネル型ＭＯＳ）ランリ
スクのソース領域とＮ型半導体基板１とＰ型のウェル２
とソース領域３とで寄生サイリスタが本質的に構成され
、加えて、Ｎ型半導体基板ｌとＰ型ウェル２とドレイン
領域４とで寄生トランジスタが構成部れ′ることから、
チャタリング等によシトレイン領域４の電圧が負電位に
移行すると寄生トランジスタがオンとなり、ウェル２内
に電流が流れ、９エルの電位が上昇する。通常、ソース
領域３とＰ型領域１０とｒｌ、電極８を介して定電圧源
、例えば、接地電位に接続されているので、ウェル２の
電位上昇は抑制されるものの、ウェル２内の電位上昇が
急だと、ソース領域３直下のウェル２の電位力・ウェル
２とソース領域３との障壁電位差を超えて上昇し、ウェ
ル２とソース領域３とか順方向にバイアスされ、寄生サ
イリスタが点弧される、いわゆるラッチアップ現象か生
じるという問題点があった。(Problems with the Prior Art) In the conventional complementary MOS transistor having the above structure, a P-channel MOS (not shown) has a run risk source region, an N-type semiconductor substrate 1, and a P-type well 2.
and the source region 3 essentially constitute a parasitic thyristor, and in addition, the N-type semiconductor substrate 1, the P-type well 2, and the drain region 4 constitute a parasitic transistor.
When the voltage of the strain region 4 shifts to a negative potential due to chattering or the like, the parasitic transistor is turned on, a current flows in the well 2, and the potential of the well 9L rises. Normally, since the source region 3, the P-type region 10, rl, and the electrode 8 are connected to a constant voltage source, for example, a ground potential, the potential increase in the well 2 is suppressed; If the voltage is sudden, the potential of well 2 directly below source region 3 will rise beyond the barrier potential difference between well 2 and source region 3, and well 2 and source region 3 will be biased in the forward direction, causing the parasitic thyristor to fire. There is a problem in that a so-called latch-up phenomenon occurs.
（問題を解決するための手段）
本発明は、上記従来の札袖長Ｍ Ｏ８）ランリスクにお
ける寄生サイリスクのランチアップ現象に鑑み、ソース
領域のチャンネル仙ｊ端部全除き、ソース領域にソース
領域と逆尋電型不純物の高駄度領域を接合させ、該高濃
度領域と該高濃度領域に接合するソース領域とに渡る寺
体層を設げたことを要旨とする。(Means for Solving the Problem) In view of the launch-up phenomenon of the parasitic side risk in the above-mentioned conventional tag sleeve length M08) run risk, the present invention has been proposed to The gist of the present invention is to connect a high-density region of reverse dielectric type impurity to a high-density region, and to provide a layer covering the high-concentration region and a source region connected to the high-concentration region.
（実施例）
第１図は本発明の一実施例を示す断面図であり、従来の
相補型ＭＯＳ半導体装置と同一構成部分には同一符号の
み付し、簡略のため詳細な説明を省略する。(Embodiment) FIG. 1 is a sectional view showing an embodiment of the present invention, in which the same components as those of a conventional complementary MOS semiconductor device are denoted by the same reference numerals, and detailed explanations are omitted for the sake of brevity.
Ｐ型のウェル２のソース領域３との接合部近傍には、ウ
ェル２よりμ濃度のＰ型領域１１が形成されており、こ
のＰ型額域】１は、ソース領域３のチャンネル側端部を
除き、反チャンネル側端部方向延在し、Ｐ遮領Ｍ１０に
連続している。したがって、ソース領域３はチャンネル
側端部を除きＰ型領域１０．１１で包囲されている。Ｐ
ｆｉ領域１０．１１は全体として高濃度領域１２を構成
している。In the vicinity of the junction of the P-type well 2 with the source region 3, a P-type region 11 with a higher μ concentration than the well 2 is formed. , which extends toward the opposite end of the channel and is continuous with the P shield M10. Therefore, source region 3 is surrounded by P-type regions 10 and 11 except for the channel side end. P
The fi region 10.11 constitutes a high concentration region 12 as a whole.
次に、第３９１ ＜ａｔ （ｂ）に基き、Ｐｖ領域１１
の形成方法を説明する。まず、第３図（ａ）に示されて
いるように・フィールド醪化腓６およびＭＯＳトランジ
スタ上にマスク材を診布し、Ｐ型仲域１１の形成予定飴
域上のマスク材を除去してマスク１３を完成させる。続
いて、打ち込まれたホウ尤イオンがソース領域３とウェ
ル２との接合面で最大になるように打込エネルギを調整
し、イオン打込を行なう。Next, based on No. 391 < at (b), Pv area 11
The formation method will be explained. First, as shown in FIG. 3(a), a mask material is spread over the field solidifying layer 6 and the MOS transistor, and the mask material on the area where the P-type middle area 11 is to be formed is removed. The mask 13 is completed. Subsequently, the implantation energy is adjusted so that the implanted ions are maximized at the junction between the source region 3 and the well 2, and ion implantation is performed.
こうして、イオン打込終了後、アニールを行ない、マス
クを除去して高濃度領域１２の形成工程を終了する（第
３図（ｂ））。After completing the ion implantation, annealing is performed and the mask is removed to complete the process of forming the high concentration region 12 (FIG. 3(b)).
次に、相補型ＭＯＳ）ランリスクの使用中に、基板１と
ウニ／Ｉ／２とドレイン領域４とで構成される寄生トラ
ンジスタが、ドレイン領域４に印加されている信号のチ
ャタリング等によｐオン状態になった場合の高濃度領域
１２の作用について説明する。Next, during the use of the complementary MOS (complementary MOS) run risk, a parasitic transistor composed of the substrate 1, U/I/2, and the drain region 4 is generated due to chattering of the signal applied to the drain region 4, etc. The action of the high concentration region 12 when it is in the on state will be explained.
かかる寄生トランジスタのオン状態への移行により、ウ
ェル２の電位は上昇し、高疾度領域１２の電位も上昇す
る。しかしながら、高鹸度領域１２の抵抗率は小きいの
で、高濃度領域１２に入った電荷は直ちに電極８に排出
さｎ１高磯度領域１２とソース領域３との電位差はその
障壁電位差を超えることがない。したかって、相補型Ｍ
ＯＳトランジスタにおいてｅユ、本質的に避けられない
寄生サイリスクも点弧もれることがない１、なお、上記
一実施例では、高濃度領域１２を、Ｐウェル２内に形成
されるＮチャンネル型ＭＯＳトランジスタについて設け
たが、Ｐウェル２外のＰチャンネル型ＭＯＳトランジス
タにのみ設けてもよく、その双方に設けてもよい。As the parasitic transistor turns on, the potential of the well 2 increases, and the potential of the high-intensity region 12 also increases. However, since the resistivity of the high-density region 12 is small, the charges that enter the high-concentration region 12 are immediately discharged to the electrode 8, and the potential difference between the n1 high-density region 12 and the source region 3 exceeds the barrier potential difference. There is no. So, complementary type M
In the OS transistor, there is no parasitic noise risk that is essentially unavoidable. In the above embodiment, the high concentration region 12 is formed in the N-channel type MOS formed in the P well 2. Although it is provided for the transistor, it may be provided only for the P channel type MOS transistor outside the P well 2, or it may be provided for both of them.
（効果）
以上説明してきたように、本発明によれば、ソース領域
のチャンネル側端部を除く部分を高濃度領域に接合させ
ると共に、これらを導体で接続したので、高濃度領域の
電位が不所望の変動を起しても、ソース領域と高濃度領
域との電位差が接合の障壁電位差を超えることができず
、寄生サイリスタの点弧が防止でき、う、チアツブ現象
を回避できるという効果を得られる。(Effects) As explained above, according to the present invention, the portion of the source region excluding the end on the channel side is joined to the high concentration region, and these are connected by a conductor, so that the potential of the high concentration region is reduced. Even if a desired fluctuation occurs, the potential difference between the source region and the high-concentration region cannot exceed the barrier potential difference of the junction, which prevents the parasitic thyristor from igniting and avoids the chirp phenomenon. It will be done.
第１図は本発明の一実施例を示す断面図、第２図は従来
例を示す断面図、第３図（ａ） （ｂ）は一実施例の製
造工程を示す断面図でるる。
１・・・・・・半導体基板、２・・・・・・フェル、３
・・・・・・ソース領域、４・・・・−ドレイン領域、
１２・・−・・・高濃度領域。
代理人 弁理士 内 原 晋
ｙＦＪ１図
筋２図
ｔ（１）
（ｂン
筋３図FIG. 1 is a sectional view showing one embodiment of the present invention, FIG. 2 is a sectional view showing a conventional example, and FIGS. 3(a) and 3(b) are sectional views showing the manufacturing process of one embodiment. 1...Semiconductor substrate, 2...Fel, 3
......source region, 4...-drain region,
12...High concentration area. Agent Patent Attorney Susumu UchiharaFJ1 Figure 2 Figure t(1) (B Figure 3
Claims (1)
画成され、該ウェル内に第１導伝型のソース領域と第１
導伝型のドレイン領域と該ソース領域およびドレイン領
域間に狭まれたチャンネル領域とが形成され、前記ウェ
ル外に第２導伝型のソース領域と第２導伝型のドレイン
領域と該ソース領域およびドレイン領域間に狭まれたチ
ャンネル領域とが形成された相補型ＭＯＳ半導体装置に
おいて、前記ウェル内およびウェル外の半導体基板のい
ずれか一方または双方にウェルと同一導伝型または逆導
伝型の不純物を導入して高濃度領域を形成し、該高濃度
領域をいずれか一方または双方のソース領域のチャンネ
ル側端部を除く部分に接合させると共に、高濃度領域と
該高濃度領域に接合するソース領域とに渡り導体層を設
けたことを特徴とする相補型ＭＯＳ半導体装置。A well of a second conductivity type is defined in the surface portion of the semiconductor substrate of the first conductivity type, and a source region of the first conductivity type and a first conductivity type are defined within the well.
A conductivity type drain region and a channel region narrowed between the source region and the drain region are formed, and a second conductivity type source region, a second conductivity type drain region and the source region are formed outside the well. and a channel region narrowed between the drain regions, in which one or both of the semiconductor substrates inside the well and outside the well has a conductivity type of the same or opposite conductivity as that of the well. A high concentration region is formed by introducing an impurity, and the high concentration region is bonded to a portion of one or both of the source regions excluding the channel side end, and the high concentration region and the source bonded to the high concentration region are bonded to the high concentration region. A complementary MOS semiconductor device characterized in that a conductor layer is provided across the region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60224411A JPS6284547A (en) | 1985-10-07 | 1985-10-07 | Complementary type mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60224411A JPS6284547A (en) | 1985-10-07 | 1985-10-07 | Complementary type mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284547A true JPS6284547A (en) | 1987-04-18 |
Family
ID=16813344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60224411A Pending JPS6284547A (en) | 1985-10-07 | 1985-10-07 | Complementary type mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284547A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008085082A (en) * | 2006-09-27 | 2008-04-10 | Sony Corp | Power mosfet, semiconductor device equipped with the same, and manufacturing method of power mosfet |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223154A (en) * | 1984-04-20 | 1985-11-07 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-10-07 JP JP60224411A patent/JPS6284547A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60223154A (en) * | 1984-04-20 | 1985-11-07 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008085082A (en) * | 2006-09-27 | 2008-04-10 | Sony Corp | Power mosfet, semiconductor device equipped with the same, and manufacturing method of power mosfet |
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