JPS6282596A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the occupying rate of a bit line selecting circuit on the surface area of a semiconductor chip by providing a charge discharging transistor between the output node of an address circuit and the gate of the 1st transfer gate set between a bit line and an input/output line and decreasing the threshold value of said transistor compared with that of the 1st transfer gate and therefore grounding the stray capacity of this transfer gate. CONSTITUTION:The output signal of a non-selected decoder 12 is inserted to a low level and therefore a NMOS transistor TRO1 is turned off. In this case, the output signal of the decoder 12 is approximately equal to the level of an earth potential. Therefore, the potential of the source of the TRO1, i.e., the gate of a NMOS TRQ3 is higher than the earth potential by a degree equal to the threshold value of the TRO3. Here the threshold voltage of the TRO3 is set lower than those of NMOS TRs O2 and O'2. This can avoid such a case where both TRs O2 and O'2 have malfunction and are turned on.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a semiconductor memory device, in particular, a flip-flop circuit for eliminating parasitic effects when connecting a bit line and an input/output path with a diode. The present invention relates to a semiconductor memory device that reduces the area occupied by a chip surface per unit memory capacity.

[Conventional technology]

As a conventional semiconductor memory device, for example, one shown in FIG. 2 is known. Note that the circuit constituent elements in FIG. 2 are referred to as N-channel MO8 elements (hereinafter referred to as "MO8" elements) to simplify the following explanation.

The explanation will be given assuming that it is composed of NMO8).

In the figure, 01) is semiconductor memory! It represents the entire bit line selection circuit of fi, and the semiconductor memory device t has a plurality of bit line selection circuits (]1). The bit line selection circuit (11) uses an address signal α*) (At)...CAn
) <hereinafter represented by the symbol A)) and an NOR type transistor (12) whose gate is connected to the decoder (12) and whose drain is connected to a control signal generation circuit (not shown). 1 NMO3 transistor) (Of) and this NM, O8) transistor (01
), the gate is connected to the source of the source/drain open bit m (B) (B) and the input/output bus (1
0) (10) A pair of NMO8) transistors (corresponding to the second M0S transistor) (α) <
o't) and a flip-flop circuit (I3) connected to the source of the NMOS transistor (01). Decoder (12) i, a plurality of NMOS transistors (Mt) (Mt) -- (Mo) (hereinafter referred to as M
These NMO8 transistors (■ν1
) is connected to the power supply voltage (V) via an NMOS transistor (R1), and the common node (N) of

It is connected to the gate of the NMOS transistor (OX) via the NMO8 transistor (R1). Multiple NMO8) transistors (Ml) <yb)...
(Mn) is a central processing g (not shown) at its gate, respectively.
Corresponding address No. 1d (Al) (A2) from e11.
... (An) is input, and the precharge signal (φ, ) is input to the gate of the NMOS transistor (R1) from the control signal generation circuit described above. The NMOS transistor (Ol) receives a high potential (
When a HIGH) signal is input to the gate, it transitions to the ON state, and in this ON state, the control signal output by the control signal generation circuit is
1 signal (φA) is connected to an NMOS transistor (Qt) (Q'
t). NMO8 transistor (Qt
) (Q't) are tq,l:'y when the control signal (φm) input to each gate is HIGH.
h 1m CB) CB) Input/output lotus (IO) (
IO) respectively. 7 flip-flop circuit (
13) consists of an NMOS transistor (Sl) whose drain is connected to the source of the NMOS transistor (0+) and whose source is grounded, and an NMOS transistor (Sl) whose drain is connected to the source of the NMOS transistor (0+) and whose source is grounded.
NMOS transistors (S,) whose sources are grounded and whose drains are connected to the supply voltage (V) through the gates of each cross-connected to .NMOS
The precharge signal (φp) is input to the base of the transistor (Ss) n, and the precharge No. 16 (φ, ) is H.
When it is at IGH level, it shifts to ON state. Note that the bit line (B) (b) is connected to a differential amplifier (SA) and a memory cell. Such a semiconductor memory device has two
56 of the dynamic RAM, one of the 512 bits m (B) (13) is selected and connected to the input/output bus (0) (■0), as detailed below.
Data is written into and read from memory cells connected to bit lines (B) (fi). That is, under the precharge state, the control signal generation circuit outputs HIGH.
A precharge signal (φ,) is output, and each address 1
No. 6 (A) maintains the LOW level, and the decoder (]2)
is the HIGH level signal to the NMO8) transistor (0+
) is applied to the gate of Therefore, the NMOS transistor (Ol) is in the ON state, but since the control signal (φ) output from the control No. 1E output circuit is at the LOW level, each NMOS transistor (Ol) is in the ON state.
maintains the OFF state to cut off the bit lines (B) (n) and the input/output bus (10) (■0).

Here, when all but one of the address signals (A) are inverted to HIGH level, only one decoder (12) specified by the address signal (A) that continues to be at LOW level becomes HIGH. While maintaining the output of the level signal, the output No. 100 of the other decoder (12) is inverted to the LOW level, and after a predetermined time elapses, the control signal [φ person]
is inverted to HIGH level.

The output signal of the one decoder (12) is applied to the base of this control signal (φA) and passes through nine NMOS transistors (Ol) to each NMOS transistor (0,8).
) (to the gate of o'J, these NMOS transistors (0*) (0't) '1r transition to the ON state. As a result, these NMOS transistors (Ox)
(0'x) and bit line (B) (a)n are connected to input/output buses (lo) and (rO), respectively, and the bit line (
B) Data is read/written to the memory cell connected to (n).

On the other hand, since the output signal of the unselected decoder (12) is inverted to LOW level, the output signal of this decoder (12) is applied to the gate of the NMO8) transistor (
0, ) transitions to the OFF state, but a flip-flop circuit (
In other words, the flip-flop circuit (13) is grounded by the NMO8 transistor (13), which is turned on by inputting the precharge signal (φp) to the gate
Ss) applies the power supply voltage (V) to the gate of the NMO8) transistor (S,), which turns on the NMOS transistor (S,) and turns the NMO8) transistor (S,) on.
0,). Therefore, the NMO8) transistor (Ot) (0'J) remains in the OFF state, and the parasitic effects between its gate and the source of the NMO8 transistor (O7) are eliminated and malfunctions are prevented.

[Problem that the invention seeks to solve]

In such a semiconductor memory device, N! l/IQs) transistor (0
1) The flip-flop circuit (13) for keeping the source t [grounded] is connected to three NMOS transistors (
This flip-flop circuit (13) must be provided in each bit line selection circuit (11), so the flip-flop circuit (13) occupies a large amount of the chip surface area. That's the problem, my friend.

On the other hand, in order to prevent malfunction of the NMO8) transistor (Oρ(0'2)) by eliminating parasitic effects without providing such a flip-flop circuit (13)', each NMO8
It is possible to set the threshold voltage of the transistor (Oz) (0't) large, but when selected,
(B) (B) (IO) (IO) The time required to connect to (IO) increases, resulting in a problem that the access time (information transmission speed) becomes slow.

[Means for solving problems]

In view of the above problems, the present invention provides a charge discharge transistor between the gate of the first transfer gate interposed between the pit line and the input/output line and the output node of the address circuit, and the charge discharge transistor By making the threshold value smaller than the threshold value of the first transfer gate, the stray capacitance applied to the gate of the first transfer gate can be grounded via the charge draining transistor, and the first transfer gate in the off state can be undesirably grounded. This is intended to prevent the switch from transitioning to the on state.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. 1st
FIG. 1 is an electrical circuit diagram showing a bit line selection circuit of an embodiment of the semiconductor memory device according to the present invention. Note that the same reference numerals are given to the parts having the same configuration as those of the conventional one described above, and the explanation thereof will be omitted.

In this embodiment, is the conventional flip-flop circuit (13) of FIG. 2 mentioned above? It is replaced with a diode. That is, in FIG. 1, (Os) is an NMO8) transistor that functions as a diode, and this NMO3)
The transistor (03) has NMOS between the source and drain.
An NMOS transistor (
The gate of the NMOS transistor (Oz) (0'J) is connected to the output terminal of the decoder (12), and the gate is connected to the gate of the NMOS transistor (02) (0'y). Os) is 1 sea bream value cage pressure is NMO
It is set to a value smaller than the threshold voltage of 8 transistors (Ot) (0'*).

The bit line selection circuit (11) of the semiconductor memory device of this embodiment
) works as follows. First, as mentioned above, under the precharge state, the NMOS transistor (01
) is in the ON state, but the control signal (φ) is at the LOW level, so each NMO8) transistor (Ox) (0't
) remains in the OFF state, and the cold tOs transistor (03) is also in the OFF state. here.

The decoder (12) is selected by the address signal (A), and after a predetermined time has elapsed, the control signal (φA)
0 therefore flips to HIGH level.

In the above (DLI), each NMOS transistor l (ol)
(0'2) transitions to the ON state, and the bit line (B) (
n) and the input/output bus (IO). At this time, since the gate of each NMO8) transistor (0*) (0'J is at HIGH level, the NMO3) transistor (Os) transitions to the ON state, but the output signal of the decoder (12) is also approximately the power supply voltage ( V) K equal HIG) (at level).

There is no problem in the operation of the NMOS transistor (0*) (0't).

On the other hand, as mentioned above, for the unselected decoder (12), when the output signal is inverted to LOW level, this signal is applied to the gate of the NMOS transistor (0,
) transitions to the OFF state. At this time, the decoder (12)
Since the output signal of is approximately equal to ground potential (zero), NMOS
The potential of the source of the transistor (0,), that is, the gate of the NMOS transistor (03), is higher than the ground potential (zero) by the threshold voltage of the NMOS transistor (Os). However, since the threshold voltage of the NMOS transistor (03) is set to a smaller value than the threshold voltage of the NMOS transistor (02) (0'), these NMOS transistors (0,) (0'2) malfunction and turn on. There will be no condition.

That is, the source of NMOS) transistor (01) and N
Parasitic effects such as wiring between the gate of the MOS transistor (0□) (0't) can be eliminated, and bootstrap effects etc. [! N′MOS transistor (0,)(
0'2) can be prevented from malfunctioning.

In this way, the bit line selection circuit (
11), in order to replace the conventional 7-lip 70-tub circuit with a diode and prevent malfunctions due to parasitic effects, the bit line selection circuit (1
The ratio of 1) can be reduced.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the ratio t of the bit line selection circuit to the surface type of the semiconductor chip. Therefore, manufacturing yield can be improved and the operating margin can be expanded.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 2 is an electric circuit diagram showing a conventional semiconductor memory device. ]1...Bit line selection circuit, 12...
Decoder, 01...First MOS transistor, O,, Q/,...Second MOS transistor s03...Diode, A, AI, A2
・・・・・・+An・・・Address signal, φ^・
·····Control signal. Agent Patent Attorney Uchihara 20゛“・艷2−
grip

Claims (1)

[Claims] an address circuit having an output node, the output node being at a reference potential when selected and being grounded when not selected; a first transfer gate interposed between the bit line and the input/output line; and an output node of the address circuit. When the output node is at the reference potential, a bit line selection activation signal is applied to the gate of the first transfer gate, and when the output node is grounded, the bit line selection activation signal is cut off. a second transfer gate, a charge discharging transistor is interposed between the output node and the gate of the first transfer gate, and the threshold of the charge discharging transistor is set to be lower than the threshold of the first transfer gate. A semiconductor memory device characterized by being small.