JPS628075B2 - - Google Patents

Info

Publication number
JPS628075B2
JPS628075B2 JP53097081A JP9708178A JPS628075B2 JP S628075 B2 JPS628075 B2 JP S628075B2 JP 53097081 A JP53097081 A JP 53097081A JP 9708178 A JP9708178 A JP 9708178A JP S628075 B2 JPS628075 B2 JP S628075B2
Authority
JP
Japan
Prior art keywords
transistor
collector
current
circuit
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53097081A
Other languages
Japanese (ja)
Other versions
JPS5523684A (en
Inventor
Tetsuo Yoshino
Isatake Sawano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9708178A priority Critical patent/JPS5523684A/en
Publication of JPS5523684A publication Critical patent/JPS5523684A/en
Publication of JPS628075B2 publication Critical patent/JPS628075B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/52Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements
    • H04Q3/521Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker using static devices in switching stages, e.g. electronic switching arrangements using semiconductors in the switching stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Thyristor Switches And Gates (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Description

【発明の詳細な説明】 本発明は4端子サイリスタを用いた半導体通話
路スイツチの駆動回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a semiconductor communication path switch using a four-terminal thyristor.

一般に、自動電話交換機における通話路スイツ
チを4端子サイリスタで構成した場合、このサイ
リスタを導通状態に維持するには定電流源によつ
て4端子サイリスタのアノードゲートおよびカソ
ードゲートの少なくとも一方に電流を流し続ける
必要がある。
Generally, when a communication path switch in an automatic telephone exchange is configured with a four-terminal thyristor, in order to maintain the thyristor in a conductive state, a constant current source is used to flow current through at least one of the anode gate and cathode gate of the four-terminal thyristor. I need to continue.

そのため、従来は第1図に示すような構成の半
導体スイツチ駆動回路が用いられている。より詳
細に述べると、第1図の駆動回路は、半導体通話
路スイツチ(4端子サイリスタ)SWに電流吸収
端子1を介して定電流を吸収するように接続され
たトランジスタQ1とこのトランジスタQ1のベ
ースエミツタ間に直列に接続された抵抗R1およ
び基準電圧発生用ダイオードD1とを含む定電流
吸収部と、半導体通話路スイツチSWに電流供給
端子2を介して定電流を供給するように接続され
たトランジスタQ2とこのトランジスタQ2のベ
ースエミツタ間に直列に接続された抵抗R2およ
び基準電圧発生用ダイオードD2とを含む定電流
供給部とから構成される。この駆動回路は、制御
端子3および4を介して接続される制御回路5の
トランジスタQ3の導通・非導通状態によつて制
御される。なお、半導体通話路スイツチSWの端
子AおよびBはそれぞれ通話線に接続される。こ
の駆動回路に用いられる基準電圧発生用ダイオー
ドD1およびD2は理想的な特性を有する訳では
ないのでその端子電圧は電流値により変化する。
したがつて、電源Eの電圧が変動すると、基準電
圧発生用ダイオードD1およびD2の端子電圧が
変動し、その結果半導体通話路スイツチSWに対
する吸収電流値、出力電流値ともに変動する。こ
れを防止するためには制御回路5に定電流回路を
用い、基準電圧発生用ダイオードD1およびD2
に流れる電流を電源電圧の変動に拘らず一定とす
ればよいが、制御回路5の複雑化は免れない。
For this reason, a semiconductor switch drive circuit having a configuration as shown in FIG. 1 has conventionally been used. More specifically, the drive circuit shown in FIG. 1 includes a transistor Q1 connected to a semiconductor communication path switch (four-terminal thyristor) SW through a current absorption terminal 1 so as to absorb a constant current, and a base emitter of this transistor Q1. A constant current absorbing section including a resistor R1 and a reference voltage generating diode D1 connected in series therebetween, and a transistor Q2 connected to supply a constant current to the semiconductor channel switch SW via a current supply terminal 2. and a constant current supply section including a resistor R2 and a reference voltage generating diode D2 connected in series between the base and emitter of the transistor Q2. This drive circuit is controlled by the conduction/non-conduction state of transistor Q3 of control circuit 5 connected via control terminals 3 and 4. Note that terminals A and B of the semiconductor communication path switch SW are each connected to a communication line. Since the reference voltage generating diodes D1 and D2 used in this drive circuit do not have ideal characteristics, their terminal voltages vary depending on the current value.
Therefore, when the voltage of the power supply E fluctuates, the terminal voltages of the reference voltage generating diodes D1 and D2 fluctuate, and as a result, both the absorption current value and the output current value for the semiconductor channel switch SW fluctuate. In order to prevent this, a constant current circuit is used in the control circuit 5, and reference voltage generation diodes D1 and D2 are used.
Although it is possible to keep the current flowing through the circuit constant regardless of fluctuations in the power supply voltage, the control circuit 5 is inevitably complicated.

一方、電源電圧の変動に影響されることなく負
荷に定電流を供給する回路として第2図aに示す
ような2端子形のものが用いられている。この駆
動回路は基準電圧発生用ダイオードD11への電
流をトランジスタQ12によつて定電流化し、且
つ基準電圧発生用ダイオードD12への電流をト
ランジスタQ11によつて定電流化することによ
り負荷6への電流を電源電圧の変動に関係なく一
定にしている。しかし、この駆動回路は2端子形
であるので、4端子サイリスタを用いた半導体通
話路スイツチSWの少なくとも一方のゲートに定
電流を印加してこのスイツチSWを駆動するため
には第2図bに示すように、同じ回路が2個必要
となり経済的でない。
On the other hand, a two-terminal type circuit as shown in FIG. 2a is used as a circuit that supplies a constant current to a load without being affected by fluctuations in power supply voltage. This drive circuit makes the current to the reference voltage generating diode D11 a constant current by the transistor Q12, and also makes the current to the reference voltage generating diode D12 a constant current by the transistor Q11, thereby controlling the current to the load 6. is kept constant regardless of fluctuations in the power supply voltage. However, since this drive circuit is of a two-terminal type, in order to drive the switch SW by applying a constant current to at least one gate of the semiconductor communication path switch SW using a four-terminal thyristor, the circuit shown in Fig. 2b is used. As shown, two identical circuits are required, which is not economical.

したがつて、本発明は、電源電圧の変動に影響
されることなく半導体通話路スイツチを定電流駆
動することができ、且つ半導体集積回路化を容易
にする半導体スイツチ駆動回路を提供することを
目的とする。
Therefore, an object of the present invention is to provide a semiconductor switch drive circuit that can drive a semiconductor communication path switch at a constant current without being affected by fluctuations in power supply voltage, and that facilitates integration into a semiconductor integrated circuit. shall be.

本発明の半導体スイツチ駆動回路は、第1およ
び第2のコレクタとベースとエミツタとを有する
PNPマルチコレクタトランジスタと、該マルチコ
レクタトランジスタの前記ベース、エミツタ間に
接続した第1の抵抗および第1のダイオードの直
列回路とを有する電流供給形定電流回路と;前記
マルチコレクタトランジスタの前記第2のコレク
タ、ベース間に接続した抵抗と;ベースおよびエ
ミツタを互いに共通接続した第1および第2の
NPNトランジスタと、前記共通接続したベー
ス、エミツタ間に接続した第2の抵抗および第2
のダイオードの直列回路とを有する電流吸収形定
電流回路と;を備え、前記マルチコレクタトラン
ジスタの前記第2のコレクタと前記第1および第
2のNPNトランジスタの前記ベースとを接続
し;前記マルチコレクタトランジスタの前記ベー
スと前記第1のNPNトランジスタのコレクタと
を接続し;前記第1の抵抗と前記第1のダイオー
ドとの接続点と、前記第2の抵抗と前記第2のダ
イオードとの接続点とに電圧を印加し;前記マル
チコレクタトランジスタの前記第1のコレクタを
半導体スイツチへの電流供給端子とし、前記第2
のNPNトランジスタのコレクタを前記半導体ス
イツチからの電流吸収端子として、前記半導体ス
イツチを定電流駆動することを特徴とする。
The semiconductor switch driving circuit of the present invention has first and second collectors, a base, and an emitter.
a current supply type constant current circuit comprising a PNP multi-collector transistor; a series circuit of a first resistor and a first diode connected between the base and emitter of the multi-collector transistor; a resistor connected between the collector and the base; first and second resistors whose bases and emitters are commonly connected to each other;
an NPN transistor, a second resistor connected between the commonly connected base and emitter, and a second
a current absorbing constant current circuit having a series circuit of diodes; connecting the second collector of the multi-collector transistor and the bases of the first and second NPN transistors; connecting the base of the transistor and the collector of the first NPN transistor; a connection point between the first resistor and the first diode; and a connection point between the second resistor and the second diode. a voltage is applied to; the first collector of the multi-collector transistor is used as a current supply terminal to the semiconductor switch;
The semiconductor switch is characterized in that the collector of the NPN transistor is used as a current absorption terminal from the semiconductor switch, and the semiconductor switch is driven with a constant current.

以下、図面を参照して本発明の実施例について
説明する。
Embodiments of the present invention will be described below with reference to the drawings.

第3図は本発明による半導体スイツチ駆動回路
の一実施例を示す回路図である。
FIG. 3 is a circuit diagram showing an embodiment of a semiconductor switch driving circuit according to the present invention.

図に示すように、電流供給端子21および電流
吸収端子22を介して半導体通話路スイツチSW
に接続されたこの発明の駆動回路は、電流供給端
子21に第1のコレクタを接続したマルチコレク
タトランジスタQ21と、このトランジスタQ2
1のエミツタに直列に接続した電流値設定用抵抗
R21と、前記トランジスタQ21のベースと前
記抵抗R21を経て前記トランジスタQ21のエ
ミツタとに接続した基準電圧発生用ダイオードD
21とを含み、前記抵抗R21と前記ダイオード
D21との接続点を制御端子23を介して制御回
路25に接続した電流供給形定電流回路と、コレ
クタを電流吸収端子22に且つベースを前記トラ
ンジスタQ21の第2のコレクタに接続したペア
トランジスタQ22aと、このトランジスタQ2
2aのベースおよびエミツタと共通接続したベー
スおよびエミツタを有し前記トランジスタQ21
のベースにコレクタを接続したペアトランジスタ
Q22bと、前記トランジスタQ22aおよびQ
22bの共通エミツタに直列に接続した電流値設
定用抵抗R22と、前記トランジスタQ22aお
よびQ22bの共通ベースと前記抵抗R22を経
て前記トランジスタQ22aおよびQ22bの共
通エミツタとに接続した基準電圧発生用ダイオー
ドD22とを含み、前記抵抗R22と前記ダイオ
ードD22との接続点を制御端子24を介して制
御回路25に接続した電流吸収形定電流回路と、
前記トランジスタQ21のベースと第2のコレク
タ間に接続した起動抵抗R23とから構成され
る。
As shown in the figure, the semiconductor communication path switch SW is connected via the current supply terminal 21 and the current absorption terminal 22.
The drive circuit of this invention connected to the current supply terminal 21 includes a multi-collector transistor Q21 whose first collector is connected to the current supply terminal 21,
a current value setting resistor R21 connected in series to the emitter of transistor Q1, and a reference voltage generating diode D connected to the base of the transistor Q21 and the emitter of the transistor Q21 via the resistor R21.
21, a current supply type constant current circuit in which the connection point between the resistor R21 and the diode D21 is connected to the control circuit 25 via the control terminal 23, and the collector is connected to the current absorption terminal 22 and the base is connected to the transistor Q21. A pair of transistors Q22a connected to the second collector of
The transistor Q21 has a base and an emitter commonly connected to the base and emitter of the transistor Q2a.
A pair of transistors Q22b whose collector is connected to the base of the transistor Q22b and the transistors Q22a and Q
22b, a current value setting resistor R22 connected in series to the common emitter of the transistors Q22b, and a reference voltage generating diode D22 connected to the common base of the transistors Q22a and Q22b and the common emitter of the transistors Q22a and Q22b via the resistor R22. a current absorption type constant current circuit including a connection point between the resistor R22 and the diode D22 and connected to a control circuit 25 via a control terminal 24;
It consists of a starting resistor R23 connected between the base and second collector of the transistor Q21.

以上のように構成されるこの駆動回路において
マルチコレクタトランジスタQ21の一対のコレ
クタよりそれぞれ流出する電流は互いに等しく、
マルチコレクタトランジスタQ21のベースエミ
ツタ電圧によつて規定される値になる。また、ペ
アトランジスタQ22aのコレクタに流入する電
流値は、ペアトランジスタQ22bのコレクタに
流入する電流値に等しく、これらの電流値はペア
トランジスタQ22aおよびQ22bのベースエ
ミツタ間電圧により規定される。そして、マルチ
コレクタトランジスタQ21、ペアトランジスタ
Q22aおよびQ22bのそれぞれのベースエミ
ツタ間電圧は基準電圧発生用ダイオードD21も
しくはD22の両端の電圧から電流値設定用抵抗
R21もしくはR22の両端の電圧を減じた値に
なる。ここで基準電圧発生用ダイオードD21に
流れる電流はペアトランジスタQ22bによつて
定電流化され、基準電圧発生用ダイオードD22
にはマルチコレクタトランジスタQ21によつて
定電流化された電流が流れることになる。このた
め、これら基準電圧発生用ダイオードD21およ
びD22のそれぞれの両端に生じる電圧は電源電
圧の変動に関係なく一定となる。したがつて、半
導体通話路スイツチSWに電流供給端子21から
供給される電流値と電流吸収端子22から吸収す
る電流値とは、共に一定の大きさに保つことがで
きる。
In this drive circuit configured as described above, the currents flowing out from the pair of collectors of the multi-collector transistor Q21 are equal to each other,
The value is determined by the base-emitter voltage of multi-collector transistor Q21. Further, the current value flowing into the collector of paired transistor Q22a is equal to the current value flowing into the collector of paired transistor Q22b, and these current values are defined by the base-emitter voltages of paired transistors Q22a and Q22b. The base-emitter voltage of each of the multi-collector transistor Q21 and the paired transistors Q22a and Q22b is the value obtained by subtracting the voltage across the current value setting resistor R21 or R22 from the voltage across the reference voltage generating diode D21 or D22. . Here, the current flowing through the reference voltage generating diode D21 is made constant by the paired transistor Q22b, and the current flowing through the reference voltage generating diode D22 is made constant by the pair transistor Q22b.
A current made constant by the multi-collector transistor Q21 flows through the transistor Q21. Therefore, the voltage generated across each of these reference voltage generating diodes D21 and D22 remains constant regardless of fluctuations in the power supply voltage. Therefore, both the current value supplied to the semiconductor communication path switch SW from the current supply terminal 21 and the current value absorbed from the current absorption terminal 22 can be kept constant.

なお、25は前述した駆動回路の動作を制御す
る制御回路である。つまり、この制御回路25に
おけるトランジスタQ23を導通・非導通状態に
制御することにより、前記駆動回路の動作制御を
行なうものである。また、半導体通話路スイツチ
SWの端子AおよびBはそれぞれ通話線に接続さ
れる。
Note that 25 is a control circuit that controls the operation of the drive circuit described above. That is, the operation of the drive circuit is controlled by controlling the transistor Q23 in the control circuit 25 to be conductive or non-conductive. In addition, semiconductor communication path switches
Terminals A and B of SW are each connected to a communication line.

以上説明した如く本発明によれば、電源電圧の
変動に影響されることなく半導体通話路スイツチ
を定電流駆動することができ、且つ半導体集積回
路化を容易にする半導体スイツチ駆動回路が得ら
れる。
As described above, according to the present invention, a semiconductor switch drive circuit is provided which can drive a semiconductor communication path switch at a constant current without being affected by fluctuations in power supply voltage and which facilitates integration into a semiconductor integrated circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の半導体スイツチ駆動回路の一例
を示す回路図、第2図aおよびbは負荷を定電流
駆動する回路の他の例を示す回路図、第3図は本
発明による半導体スイツチ駆動回路の一実施例を
示す回路図である。 21……電流供給端子、22……電流吸収端
子、23,24……制御端子、Q21……マルチ
コレクタトランジスタ、Q22a,Q22b……
ペアトランジスタ、D21,D22……基準電圧
発生用ダイオード、R21,R22……電流値設
定用抵抗、R23……起動抵抗。
FIG. 1 is a circuit diagram showing an example of a conventional semiconductor switch drive circuit, FIGS. 2a and b are circuit diagrams showing another example of a circuit for driving a load with constant current, and FIG. 3 is a circuit diagram showing an example of a semiconductor switch drive circuit according to the present invention. FIG. 1 is a circuit diagram showing an example of a circuit. 21...Current supply terminal, 22...Current absorption terminal, 23, 24...Control terminal, Q21...Multi-collector transistor, Q22a, Q22b...
Pair transistor, D21, D22...Reference voltage generation diode, R21, R22...Resistor for current value setting, R23...Starting resistor.

Claims (1)

【特許請求の範囲】 1 第1および第2のコレクタとベースとエミツ
タとを有するPNPマルチコレクタトランジスタ
と、該マルチコレクタトランジスタの前記ベー
ス、エミツタ間に接続した第1の抵抗および第1
のダイオードの直列回路とを有する電流供給形定
電流回路と; 前記マルチコレクタトランジスタの前記第2の
コレクタ、ベース間に接続した抵抗と; ベースおよびエミツタを互いに共通接続した第
1および第2のNPNトランジスタと、前記共通
接続したベース、エミツタ間に接続した第2の抵
抗および第2のダイオードの直列回路とを有する
電流吸収形定電流回路と; を備え、 前記マルチコレクタトランジスタの前記第2の
コレクタと前記第1および第2のNPNトランジ
スタの前記ベースとを接続し; 前記マルチコレクタトランジスタの前記ベース
と前記第1のNPNトランジスタのコレクタとを
接続し; 前記第1の抵抗と前記第1のダイオードとの接
続点と、前記第2の抵抗と前記第2のダイオード
との接続点とに電圧を印加し; 前記マルチコレクタトランジスタの前記第1の
コレクタを半導体スイツチへの電流供給端子と
し、前記第2のNPNトランジスタのコレクタを
前記半導体スイツチからの電流吸収端子として、
前記半導体スイツチを定電流駆動することを特徴
とする半導体スイツチ駆動回路。
[Scope of Claims] 1. A PNP multi-collector transistor having first and second collectors, a base, and an emitter; a first resistor connected between the base and the emitter of the multi-collector transistor;
a current supply constant current circuit having a series circuit of diodes; a resistor connected between the second collector and the base of the multi-collector transistor; first and second NPNs whose bases and emitters are commonly connected to each other; a current absorbing constant current circuit comprising a transistor and a series circuit of a second resistor and a second diode connected between the commonly connected base and emitter; the second collector of the multi-collector transistor; and the bases of the first and second NPN transistors; the base of the multi-collector transistor and the collector of the first NPN transistor; the first resistor and the first diode; applying a voltage to a connection point between the second resistor and the second diode; using the first collector of the multi-collector transistor as a current supply terminal to the semiconductor switch; The collector of the second NPN transistor is used as a current absorption terminal from the semiconductor switch,
A semiconductor switch driving circuit characterized in that the semiconductor switch is driven with a constant current.
JP9708178A 1978-08-08 1978-08-08 Semiconductor switch drive circuit Granted JPS5523684A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9708178A JPS5523684A (en) 1978-08-08 1978-08-08 Semiconductor switch drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9708178A JPS5523684A (en) 1978-08-08 1978-08-08 Semiconductor switch drive circuit

Publications (2)

Publication Number Publication Date
JPS5523684A JPS5523684A (en) 1980-02-20
JPS628075B2 true JPS628075B2 (en) 1987-02-20

Family

ID=14182685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9708178A Granted JPS5523684A (en) 1978-08-08 1978-08-08 Semiconductor switch drive circuit

Country Status (1)

Country Link
JP (1) JPS5523684A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5986290A (en) * 1997-12-19 1999-11-16 Advanced Micro Devices, Inc. Silicon controlled rectifier with reduced substrate current

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210012A (en) * 1975-07-14 1977-01-26 Hitachi Ltd Pnpn switch driving circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210012A (en) * 1975-07-14 1977-01-26 Hitachi Ltd Pnpn switch driving circuit

Also Published As

Publication number Publication date
JPS5523684A (en) 1980-02-20

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