JPH03135220A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To attain high speed level conversion by turning on/off a second parabollic transistor in correspondence with H and L of the input of a CMOS or BiCMOS level, short circuiting and releasing a part of resistance elements in a voltage-dividing circuit and generating the H and L outputs of an ECL level in the output terminal of an emitter follower. CONSTITUTION:When an input Vin is in an H level, a base current control circuit 4 turns off a transistor 4. Thus, a current by a constant current source 5 flows in resistance elements 1 and 2, a voltage drops and the output voltage of the voltage-dividing circuit becomes low. When the input Vin is in an L level, the base current control circuit 4 turns on a transistor 3. Consequently, the resistance element 1 is short circuited and the voltage drop by the current of the constant current source 5 only comes to the voltage drop by almost the resistance element 2 and the output of the voltage-dividing circuit rises. Thus, the bipolar transistor of a current switch 6 is prevented from being saturated and the level conversion of high speed is realized.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a level conversion circuit in a semiconductor integrated circuit in which bipolar transistors and P/N channel MOS transistors are mixed on the same chip, high-speed level conversion is performed by preventing current switches from being saturated. For the purpose of making it possible, a voltage divider circuit formed by connecting a resistance element and a first constant current source in series, and a first bipolar transistor and a second constant current source connected in series, An emitter follower whose output terminal is the connection point, a current switch that receives the output of the voltage divider circuit and a reference voltage and generates an output that drives the bipolar transistor, and is connected in parallel with a part of the resistive element of the voltage divider circuit. a second bipolar transistor;
Receives CMOS or B i CMOS level input,
The second bipolar transistor is turned on and off according to the H and L levels to short-circuit and release a part of the resistive element of the voltage divider circuit, producing H and L outputs at the ECL level at the output terminal of the emitter follower. The configuration includes a base current control circuit that controls the current.

[Industrial application field]

The present invention provides a bipolar transistor and a P/N channel M
The present invention relates to a level conversion circuit in a semiconductor integrated circuit in which O3I transistors are mixed on the same chip.

In semiconductor integrated circuits in which bipolar transistors and P/N channel MOS transistors coexist on the same chip,
These transistors constitute an ECL circuit with CMOS or old CMOS circuits and bipolar transistors, which may connect the input/output terminals. In this case, since the input/output levels of these circuits are different,
It is necessary to intervene with a level conversion circuit.

[Conventional technology]

FIG. 4 shows a conventional example of a BtCMO5-E CL level conversion circuit. Input Vin is -0,5 for H and -4,5 for L.
■ Old CMOS level, output Vout is -0,8■
, L is the ECL level of -2,0■. High potential power supply V
cc is OV, low potential power supply VER is -5V, and as with CMOS, if IL/, H is OV and L is -5.0, but Bi
In CMO3, it is about 0.5v higher/lower than this.

This circuit consists of a level converter A and a driver B, and the level converter consists of a P-channel MO3) transistor 21, N-channel MOS transistors 22, 26, bipolar transistors 23, 25, resistors 24, 27, and a plurality of diodes. Clamp circuit 2 (3 in the example) connected in series
8, and the drive section B is a bipolar transistor 8a.
, 8b.

9a, a current switch consisting of resistors 12.10a, 10b, and 9b, and a bipolar transistor 7.11a.
and an emitter follower consisting of a resistor 11b.

Now, when the input Vin is H at the B;cMOS logic level, the transistor 21 is off and the transistors 22 and 26 are on. Therefore, the transistor 23 draws the base current t
The transistor 25 is turned off and the clamp circuit 28 is turned off.
A base current is supplied through the path of the transistor 26 to turn it on. Therefore, current also flows through the path passing through the clamp circuit 28, the resistor 24, and the transistor 25, and the input terminal N1 of the current switch has a voltage drop due to the clamp circuit 28 from the power supply Vcc (approximately 0.8 + 0.8 + 0.4 = 2.0 V). The level becomes lower (-2V). The reference voltage V ref of the current switch is a higher voltage (for example -
1.3V), transistor 8b is turned on, transistor 8a is turned off, and the base of transistor 7 is set at a level (0.2V) equal to the voltage drop across resistor 12 (about 0.2V).
) is given, and the output Vout becomes approximately -1.0■ which is lower by VBE than that. This is the H level of ECL.

Next, when the input Vin is at the BiCMOS logic level of L, the transistor 21 is on, the transistor 22.26 is off,
Transistor 23 is supplied with base current by transistor 21 and turned on. The transistor 25 is connected to the resistor 2
7 pulls the base current and turns off. The clamp circuit 28 is short-circuited by the transistor 23, and the input terminal N1 of the current switch becomes approximately -0.5V, which is lower than the voltage 11Vcc by the collector-emitter voltage VCE of the transistor 23. Since this voltage is higher than the reference voltage V ref, the transistor 8a is turned on and the transistor 8b is turned off, and the base potential of the transistor 7 is lower than the power supply Vcc by the resistors 12 and 1.
The voltage drop of 0a is subtracted to be approximately -0.8■ (this is how the IR is set), and the output Vout is approximately -1.6■, which is lower by VBE.

In this way, with this circuit, H is 10.5 V and L is 4.5 ■.
The BiCMOS output (Vin) of is converted into an ECL input (Vout) with H of -1 and 0.L of -1°6.

Is the input C? The same applies to the IOS level.

Note that the transistors 9a and lla in this circuit are resistors 9b,
constitute a constant current source together with llb and control voltage Vcs,
The current value is determined by the voltage Vcs and/or the values of the resistors 9b and llb. The transistors 23 and 25 also form a totem pole; if one 23 is on, the other 25 is off;
Conversely, if 25 is on, 23 is off. When the transistor 25 is on, the input terminal N1 is set to the L level, and when the transistor 23 is on, the input terminal N1 is set to the H level.

Transistors 21 and 22 forming the CMOS inverter
is for controlling the transistor 23, and the transistor 26
is for controlling the transistor 25. Further, the clamp circuit 28 limits the potential drop of the node N1 when the input Vir+'+<H. That is, when Vin is H, the transistor 25 is on, and if the clamp circuit 28 is a resistor, the node N1 is strongly pulled toward the VBE side, which may interfere with the operation of the current switch. Clamp circuit 28
If this potential drop is limited by , the fear of overheating will disappear.

[Problem to be solved by the invention]

In the circuit shown in FIG. 4, when the input Vin is at the L level, the bipolar transistor 23 is turned on and after raising the input level of the current switch, only the base current is supplied to the transistor 8a, and the bipolar transistor 23 is almost turned off. The collector-emitter voltage vcEO11 of this almost off-state transistor 23 is approximately 0.5■, which causes the node N
The potential of 1 becomes VccO, 5=-0.5V.

This N+=-0.5V is higher than Vref=-1.3V, and as a result, transistor 8a is turned on and resistor 10a
A voltage drop occurs, lowering the base potential of transistor 7. Normally, the output amplitude of ECL is set to about 0.6■, but in this case, the base potential (collector potential of 8a) is 0.8V from the base potential of 0 when the input Vin is I (
As a result, the collector potential of the bipolar transistor 8a becomes lower than the base potential, and becomes saturated. For this reason, the current switch 8a
, 8b switch speed is slow.

The present invention aims to improve this point and enable high-speed level conversion by preventing the current switch from becoming saturated.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the level converter A includes a voltage divider circuit composed of a resistor element 1.2 and a constant current source 5, and a bipolar transistor 3 that short-circuits a part of the resistor element 1 of the voltage divider circuit. and CMO3 or BiCMOS level input Vi
It consists of a base current control circuit 4 that turns on and off the transistor 3 according to the H and L of n.

The output voltage of the voltage divider circuit is applied to the base of the transistor 8a of the current switch 6, but this output voltage is made not to be higher than the collector voltage of the transistor 8a even at H level.

[For production]

In this circuit, the base current control circuit 4 turns off the transistor 4 when the input Vin is at H level.

Therefore, a current from the constant current source 5 flows through the resistance element 1.2, causing a voltage drop, and the output voltage of the voltage dividing circuit is low, for example, -2V. Current switch reference voltage V ref
is higher than this, for example, if you set it to -1,6■,
Transistor 8a is turned off, transistor 8b is turned on, and the collector of transistor 8a has a potential (-) equal to the voltage drop across resistor I2.
0.2V), and the output Vout becomes -1.0■ which is lower by VBE than that. This is the H level of ECL. The transistor 8a has a base of 12cm and a collector of -
Since the voltage is 0.2V, the collector has a higher potential than the base and will not be saturated.

Next, when the input Vin is at L level, the base current control circuit 4 turns on the transistor 3. As a result, the resistive element 1 is short-circuited, and the voltage drop due to the current of the low current source 5 becomes only the voltage drop due to the resistive element 2, and the output of the voltage dividing circuit increases, for example, to -1.2V. Since this is higher than the reference voltage Vref, transistor 8a is turned on and transistor 8b is turned on.
is turned off, and the current from the constant current source 9 flows through the resistors 12 and 10a, causing a voltage drop. This voltage drop is set to about 0.8 V, and this voltage (Vcc-0.8V=-0.8V
) to the emitter of transistor 7 -o, a
v-o.

8V=-1, producing an output Vout of 6V. This is EC
It is the L level of L. Part of transistor 8a is -1
, 2V, and the collector is also -0.8V, so the base will not have a higher potential than the collector, and saturation of the transistor 8a is avoided.

In this way, this circuit can convert the CI'lO5 or BiCMOS level to the ECL level, and can perform high-speed level conversion by preventing saturation of the current switch of the conversion circuit. The circuit configuration is also simpler than conventional circuits. Further, since a voltage dividing circuit is used, the output voltage can be adjusted, and saturation of the current switch can be prevented reliably and easily according to the desired ECL output.

〔Example〕

An embodiment of the present invention is shown in FIGS. 2 and 3. In FIG. 2, the base current control circuit 4 is composed of P-channel MOS transistors 4a, ! : C? consisting of N channel MOS transistor 4b? The resistance element 1.2 is composed of junction diodes la, lb and a Schottky barrier diode 2. The constant current source 5 is composed of a bipolar transistor, a resistor, and a control voltage as in 9.11. 5a, 5b, and Vcs are the transistors, resistances, and control voltages.

When the input Vin is at H level, the transistor 4a is off.
4b is turned on, and bipolar transistor 3 is turned off.

Therefore, the output of the voltage divider circuit is the sum of the voltage drops due to diodes la, lb, and 2: 0.8 + 0.8 +0, 4 = 2
．． The voltage becomes -2V, which is lower than Vcc by 0.

This is lower than the reference voltage Vref = -1.6V, so in the current switch 6, the transistor 8b is turned on and the transistor 8a is turned off, and the base potential of the transistor 7 becomes -0.2V, which is the voltage drop caused by the resistor 12. Vout = VBE lower than that at the emitter
1. Produces OV.

When the input Vi is at L level, transistor 4a is turned on, transistor 4b is turned off, and transistor 3 is turned on. The current of the constant current source 5 comes to flow through the transistor 3 and the diode 2, and the base of the transistor 3 receives the power supply voltage V cc = OV, so the emitter potential becomes 10.8■, and the diode The output of the voltage divider circuit is -1.2■, which is the sum of the voltage drop of 2 and 0.4■. Since this is higher than the reference voltage V ref, transistor 8a is turned on and transistor 8b is turned on.
is turned off and resistors 12 and 10a produce a voltage drop of approximately 0.8V.

Transistor 7 receives this voltage -0.8V at its base and produces an output Vout of -1.6V at its emitter.

In FIG. 3, the resistive element 1.2 is constituted by a resistor.

The rest is the same as in FIG. 2. When a diode is used as a resistive element as shown in Figure 2, the voltage drop is fixed at 0.8 V for a junction type and 0.4 V for a Schottky barrier type, but if it is a resistor, it can vary depending on its resistance value and the flowing current. It is possible to fine-tune the output voltage of the voltage divider circuit. Also, if it is a resistor, even if transistor 3 is turned on, current will flow through resistor 1 (a current determined by the resistance ratio of 1 and 3 will flow), but if it is a diode, transistor 3 will flow.
The difference is that when V is turned on, no current may flow through diode 1 (if the transistor voltage VCE is smaller than the diode voltage vP).

A combination of a resistor and a diode may be used as the voltage divider circuit.

If the bipolar transistor 3 is used as a switching element that serves as a part of the resistance element of the voltage dividing circuit, a stable voltage divided output can be obtained. If this is a MOS transistor, its on-resistance will vary due to the influence of the process, making it difficult to obtain a divided voltage output with good yield and high precision. Note that if the bipolar transistor 3 is used, the output of the voltage dividing circuit will be 10.8V at most. Therefore, it is impossible to directly drive the transistor 7 with this without passing through the current switch, since the H level of Vout will become -1.6V or less, unless it is acceptable.

〔Effect of the invention〕

As described above, according to the present invention, the bipolar transistor of the current switch does not need to be saturated, and high-speed level conversion can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a principle diagram of the present invention, FIGS. 2 and 3 are explanatory diagrams of embodiments 1 and 2 of the present invention, and FIG. 4 is a circuit diagram showing a conventional example. In Figure 1, 1.2 is a resistance element, 3.7 is a bipolar transistor, 4 is a base current control circuit, 511 is a constant current source,
6 is a current switch.

Claims (1)

[Claims] 1. A voltage divider circuit formed by connecting resistive elements (1, 2) and a first constant current source (5) in series; a first bipolar transistor (7) and a second bipolar transistor (7); an emitter follower in which constant current sources (11) are connected in series and whose output terminal is the series connection point; a current switch that receives the output of the voltage divider circuit and a reference voltage and generates an output that drives the bipolar transistor; A second resistor connected in parallel with a part of the resistive element of the voltage divider circuit.
bipolar transistor (3) and CMOS or B
Receives iCMOS level input (Vin) and its H, L
Base current control that turns on and off the second bipolar transistor in response to short-circuiting and releasing a part of the resistive element of the voltage divider circuit to produce H and L outputs at the ECL level at the output terminal of the emitter follower. A level conversion circuit comprising a circuit (4).