JPS6325775Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a clamp circuit, and is particularly intended to provide a clamp circuit with quick response.

Generally, a clamp circuit is provided at the front stage of the AD converter, which clamps input voltages that are above the conversion operating range of the AD converter. Conventional clamp circuits are shown in FIGS. 1 and 2. The clamp circuit shown in FIG. 1 connects Zener diodes 3 and 4 connected in series in opposite directions between the output terminal 2 of an inverting amplifier 1 and the inverting input terminal of the amplifier 1, and applies an input voltage V _i to an input terminal 5. When the output voltage V ₀ exceeds the Zener voltage of the Zener diode 3 or 4, the Zener diodes 3 and 4 become conductive and enter a clamped state. Therefore, when the input voltage V _i exceeds certain positive and negative voltages, a clamp state occurs.

According to this circuit, the voltage drop generated across the Zener diodes 3 and 4 due to the current flowing through them changes according to the forward direction characteristic of one Zener diode and the Zener characteristic of the other Zener diode. As the current increases, the voltage drop across it increases relatively significantly. The increase in voltage drop appears as an increase in the output voltage V ₀ . Therefore, as the input voltage rises, the output voltage gradually rises and eventually the amplifier 1 becomes saturated. Furthermore, since the clamp current is supplied from the amplifier 1, there is a drawback that a wide clamp range cannot be achieved. Furthermore, since the clamp voltage increases in accordance with the voltage drop characteristics of the two diodes, the increase is large and there is also a drawback that the clamp characteristics are poor.

In the example shown in FIG. 2, transistors 6 and 7 are provided that are controlled to turn on and off by the output of the inverting amplifier 1 so as to operate in reverse to each other. The configuration is such that it is connected to an input terminal. According to this configuration, the output voltage of the inverting amplifier 1 is
When the voltage E 1 of the bias voltage source 8 connected between the bases of the transistors 6 and ₇ becomes larger or the voltage E 2 of the bias voltage source 9 becomes smaller than the voltage E ₂ of the
conducts and becomes clamped.

In this circuit, for example, in a clamp state when the input voltage is positive polarity, the transistor 7 becomes conductive, and the input current i ₁ due to the input voltage V _i applied to the input terminal 5
flows into the negative power supply through transistor 7. Further, when the input voltage V _i is clamped in a negative polarity state, the transistor 6 is turned on, and a current i ₂ is supplied to the input terminal 5 through the transistor 6.

In this example, since the clamp current is supplied from the outside, the amplifier 1 does not become saturated. However, before entering the clamp state, both transistors 6 and 7 are off. Therefore, since the device is in a clamped state, it takes a long time to switch from an off state to an on state, resulting in a slow response. Furthermore, there is a drawback that a large overshoot occurs at the output terminal 2 when the transistor 6 or 7 is turned on.

The purpose of this invention is to provide a clamp circuit that has a fast response and can also have a wide clamping range.

In this device, the bias voltage generating transistor is always kept on, and the bias voltage generated by the current flowing through this transistor keeps the diode, whose one end is connected to the inverting input terminal of the inverting amplifier 1, in the off state. and inverting amplifier 1
When the output of the transistor exceeds a predetermined voltage, the current flowing through the transistor is reduced, and the reduction in current lowers the bias voltage to turn on the diode, and conduction of the diode supplies a clamping current to the inverting input terminal of the inverting amplifier.

In this way, in this invention, the bias voltage is changed by changing the current value of the transistor in the conductive state, and the diode is controlled to be turned on by the change in the bias voltage. Therefore, since a diode with a short turn-on time is used, a high-speed response is possible as a whole.

An embodiment of this invention will be explained in detail below using FIG. 3.

In FIG. 3, 1 is an inverting amplifier, 2 is an output terminal, 5 is a voltage input terminal, and 5' is a current input terminal. When the resistance value of the input resistor 13 is R ₁ and the resistance value of the negative feedback resistor 14 is R ₂ , the output voltage V ₀ is V ₀
= R ₂ /R _{1 Vi} . In addition, in the case of current input, V ₀ = R ₂ × Ii.

In this invention, transistors 15 and 16 are provided which are always kept in a conductive state. The transistor 15 is a PNP type transistor whose emitter is connected to the positive power supply +V through the resistor 17, and whose collector is connected to the negative power supply -V. The transistor 16 is an NPN type transistor, and its emitter is connected to a negative power source -V through a resistor 18, and its collector is connected to a positive power source +V.

The bases of these transistors 15 and 16 are connected to a bias voltage source 19 and are normally kept in an on state. The bias voltage source 19 is constituted by a series circuit consisting of a resistor 21, Zener diodes 22-23, and a resistor 24 connected between a positive power supply +V and a negative power supply -V. transistor 15
The base is a Zener diode 23 and a resistor 24
The base of the transistor 16 is connected to the connection point B between the Zener diode 22 and the resistor 21.

On the other hand, the anode of a diode 25 is connected to the emitter of the transistor 15, and the cathode of a diode 26 is connected to the emitter of the transistor 16. The cathodes and anodes of the diodes 25 and 26 are commonly connected to the inverting input terminal of the inverting amplifier 1. The output of inverting amplifier 1 is bias voltage source 1
9 is connected to the connection point of Zener diodes 22 and 23.

In this configuration, under normal operating conditions, the emitter potential of transistor 15 is held at a potential approximately equal to the potential at connection point A. The potential at this connection point A is substantially biased toward the negative potential side by the Zener voltage of the Zener diode 23 from the potential at the common potential point 27. Further, the emitter of the transistor 16 is held at the potential of the connection point B. The potential at this connection point B is biased toward the positive potential side by the Zener voltage of the Zener diode 22 from the potential at the common potential point 27 . On the other hand, since the potential of the inverting input terminal of the inverting amplifier 1 is approximately the potential of the common potential point 27, a reverse bias voltage equivalent to the voltage of the Zener diodes 22 and 23 is supplied to the diodes 25 and 26, and both It is in the off state.

When, for example, a positive input voltage V _i is input to the input terminal 5, the output voltage of the inverting amplifier 1 changes in the negative polarity direction. When the output voltage of the amplifier 1 changes in the negative direction by the voltage of the Zener diode 22 and the potential at the connection point B changes slightly to the negative potential side compared to the potential at the common potential point 27, the diode 26 starts conducting. When the diode 26 becomes conductive, a clamp current flows from the input terminal 5 to the diode 26 through the input resistor 13, and even if the input voltage V _i increases further in the positive direction, the output voltage V ₀ remains in that state and is clamped. state.

On the other hand, when the input voltage V _i changes in the negative direction, the output voltage of the amplifier 1 changes in the positive direction. When the output voltage of the amplifier 1 increases by the voltage of the Zener diode 23, the potential at the connection point A approaches the potential at the common potential point 27. When the potential at the connection point B slightly deviates to the positive side from the potential at the common potential point 27, the anode potential of the diode 25 becomes the common potential point 27.
The potential is slightly biased toward the positive electrode potential. Therefore, the diode 25 conducts, and a clamping current flows from the positive power supply +V to the input resistor 13 through the diode 25, and even if the input voltage V _i applied to the input terminal 5 changes further in the negative direction, the output voltage V ₀ remains unchanged. held in state.

Also in the case of the current input terminal 5', when the input current +Ii flows in the direction of inflow from the input terminal 5', a negative polarity voltage is outputted to the output of the amplifier 1. When this output voltage deviates to the negative potential side by the voltage of the Zener diode 22, the diode 26 is turned on and the clamp state is established as described above. Further, when the current -Ii flows in the direction of flowing out from the input terminal 5', a positive voltage is generated at the output of the amplifier 1. When this output voltage rises by the voltage of the Zener diode 23, the diode 25 is turned on, resulting in a clamped state as described above.

As mentioned above, according to this invention, the diode 25 or 26 is turned on, resulting in a clamped state. Generally, the turn-on time of the diode is shorter than the turn-on time of the transistor, so a high-speed response is possible. be. Furthermore, the clamp current is input to the inverting input terminal of the inverting amplifier 1 through the diode 25 or 26, and the clamp current flowing through the diode 25 or 26 also increases in proportion to the increase in the input voltage or input current. Due to this increase, the voltage drop across the diodes 25 and 26 also increases, and the increase in this voltage drop appears as an increase in the output voltage V ₀ , but according to this invention, the increase in the output voltage V ₀ is due to the forward voltage of one diode. It is the rise of the descent, and the increase is small. Therefore, as shown in Fig. 4, even if the input voltage V _i exceeds +V _i0 and -V _i0 , the output voltage V ₀ is maintained at a substantially constant voltage, and even if a large input voltage is applied, the amplifier 1 is saturated. Never.

Therefore, according to this invention, it is possible to provide a clamp circuit that is capable of high-speed response and has excellent clamping characteristics.

[Brief explanation of the drawing]

1 and 2 are connection diagrams for explaining a conventional clamp circuit, FIG. 3 is a connection diagram for explaining an embodiment of this invention, and FIG. 4 is a graph for explaining its operation. 1: Inverting amplifier, 2: Output terminal, 5: Voltage input terminal, 5': Current input terminal, 15, 16: Bias voltage generation transistor, 25, 26: Clamp diode, 19: Bias voltage source, 22,
23: Setting voltage generation means.

Claims (1)

[Claims for Utility Model Registration] A polarity reversing amplifier, a Zener diode having one end connected to the polarity reversing amplifier, an emitter resistor having one end connected to a constant voltage source, and an emitter resistor having the other end of the emitter resistor. a transistor whose base is connected to the other end of the Zener diode, and a diode connected between the emitter of the transistor and the input end of the polarity inverting amplifier. clamp circuit.