JPS6280570A - Testing circuit for counter - Google Patents

Abstract

PURPOSE:To shorten a test time by allowing a counter which counts a clock signal to hold an output signal which is set to logic '1' and loading it in the counter. CONSTITUTION:A counter testing circuit is provided with FFs 4 (40-43) as a holding means and also provided with a delay circuit 2 and a gate 3 as a loading means. Output signals (q) (q0-q3) of low-order (i) digits of the counter 1 are all set to logic '1' after (i) clock signals CK are inputted to the counter 1, so a clock signal CK consisting of pulses as many as the number of the digits of the counter 1 is only inputted to verify the counting function of the counter 1, thereby shortening its required test time.

Description

[Detailed description of the invention] [(Already required)] A counter that counts a clock signal holds an output signal set to logic "1" and loads it into the counter, thereby shortening the test time of the counting function of the counter. It is something.

[Industrial application field]

The present invention relates to an improvement in a counter test circuit for testing the counting function of a counter.

Counters are widely used as the most basic unit circuit of digital circuits.

There is a strong demand for a means to verify the counting function of such counters in the shortest possible time.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional counter testing method.

In FIG. 4, a 4-digit binary counter l counts clock signals ck of a predetermined period inputted to a clock terminal CP, and outputs output signals qO to q3 representing the counting results in binary form from output terminals 00 to 03. Output.

Therefore, in order to verify the counting function of counter 1, for example, when one clock signal ck is input, the output signal qo
When only the output signal q1 changes from logic "0" to logic "1", and two clock signals ck are input, only the output signal q1 changes from logic "0" to logic "1", and so on. When 8 clock signals ck are input, the output signal q3
The counting function of counter 1 is verified by confirming that the value changes from logic "0" to logic "1".

[Problem to be Solved by the Invention 3] As is clear from the above explanation, in the conventional counter testing method, the clock signal ck is input to the clock terminal CP of the counter to be tested, and the clock signal ck is input from the output terminals 00 to 03. The counting function was verified by output signals qo to q3.

Therefore, for example, in order to verify the counting function of a binary n-digit counter, it is necessary to input 2 n -1 clock signals ck and count them, which poses a problem in that the test requires a large amount of time.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, a counter 1 that counts the output signal ck is connected to a holding means 100 that holds an output signal q set to logic "1", and an output signal q held by the holding means 100 is loaded into the counter 1. Loading means 200 is provided to do so.

[Effect]

That is, according to the present invention, the counter receives i clock signals c.
After k is input, the output signal q of the last digit of the counter
Since all are set to logic "1", the counting function of the counter can be verified by simply inputting the clock signal ck with the number of pulses equal to the number of digits of the counter, and the time required for testing can be significantly shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a counter test circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the signal waveform in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2 as well, the counter 1 to be tested is a four-digit binary counter.

In FIG. 2, flip-flops 40 to 43 are provided as holding means 100, and delay circuit 2 and gate 3 are provided as loading means 200.

Flip-flops 40 to 43 each have an output terminal O.
It receives the output signals QO to q3 outputted from the counters O to 03, outputs the holding signals ho to h3, and transmits them to the input terminals IO to I3 of the counter 1.

On the other hand, the delay circuit 2 applies a predetermined delay time 'F to the clock signal ck input to the clock terminal CP of the counter 1, and then sends the load signal c to the load terminal via the gate 3.
Input as k'.

Prior to testing the counter 1, a reset signal r is input to the counter 1 and each flip-flop 40 to 43,
Counter 1 and each flip-flop 40-43 are reset.

As a result, the output signals qO to q3 output from the output terminals 00 to 03 of the counter 1 are set to logic "0", and the holding signals ho to h3 output from the flip-flops 40 to 43 are also set to logic "0". It is set.

Also, during the test, the test signal t is set to logic "1".

As a result, gate 3 is set to the W pass state during the test.

In this state, when the first clock signal ck is input to the clock terminal CP of the counter 1, the counter 1 counts 1 and updates the output signal qO from logic "0" to logic "1". As a result, flip-flop 40 is set and outputs a hold signal.

is updated from logic "0" to logic "1".

On the other hand, the clock signal ck is supplied with a delay time T by the delay circuit 2.
After passing through, the load signal ck" is inputted to the load terminal of the counter 1 via the gates 1-3 which are in a conductive state.

The counter 1, which receives the load signal ck', sets the holding signals ho to h3, which are transmitted to the input terminals ro to I3, to each digit.

As a result, the output signal QO is subsequently set to logic "1" and the output signals ql to q3 are set to logic '0', resulting in a state in which 1 is counted.

In this state, when the second clock signal ck is input to the clock terminal CP of the counter 1, the counter 1 advances by one step, counts 2, and changes the output signal qo from logic "1" to logic "".
0” and output signal q1 from logic “0” to logic “1”.
Update to. As a result, the flip-flop 41 is switched, and the holding signal h1 to be output changes from logic "0" to logic "L".
Update to. Note that the flip-flop 40 continues to maintain the cent state and continues to hold the holding signal hO at logic "1".

Therefore, when the load signal ck' is input to the load terminal ■ after the delay time T, the counter 1 sets the output signals qO and ql to logic "1", and sets the output signals q2 and q3 to logic "0". Then, it becomes a state where 3 is counted.

In this state, when the third clock signal ck is input to the clock terminal CP of the counter 1, the counter 1 advances by one step, counts 4, and outputs the output signals qo and ql to the logic "l".
The output signal q2 is updated from logic "0" to logic "0" and output signal q2 is updated from logic "0" to logic "1". As a result, the flip-flop 4
2 is set to update the output holding signal h2 from logic "0" to logic "1". Note that the flip-flops 40 and 41 continue to maintain the set state and receive the holding signal ho.
and hl continue to be held at logic "1".

Therefore, when the load signal ck' is input to the load terminal after the delay time T, the counter 1 sets the output signals qO1Ql and q2 to the logic "1", and sets the output signal q3 to the logic "1".
0” and a state where 7 is counted.

In this state, when the fourth clock signal ck is input to the clock terminal CP of the counter 1, the counter 1 counts 8 and changes the output signals qO, ql and q2 from logic "1" to logic "0". Also, the output signal q3 is updated from logic "O" to logic "1".

In the above process, the output signals qO to q3 outputted from the output terminals OO to 03 are monitored, and the first to fourth output signals are monitored.
Every time the clock signal ck is input to the clock terminal CP, the output signals qo to q3 sequentially change from logic "O" to logic "
The counting function of counter 1 can be verified depending on whether it is updated to 1''.

As is clear from the above explanation, according to this embodiment, in order to verify the counting function of the 4-digit binary counter 1, only 4 clock signals ck are input, which greatly reduces the time required for testing. be done.

Note that FIGS. 2 and 3 are only one embodiment of the present invention, and for example, the counter 1 to be tested is not limited to four digits, and many other modifications may be considered. In either case, the effects of the present invention remain the same.

〔Effect of the invention〕

As described above, according to the present invention, the counting function of the counter can be verified by simply inputting the clock signal ck with the number of pulses equal to the number of digits of the counter, and the time required for the test can be significantly shortened.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention, Fig. 2 is a diagram showing a counter test circuit according to an embodiment of the invention, Fig. 3 is a diagram showing an example of the signal waveform in Fig. 2, and Fig. 4 is a diagram showing an example of the signal waveform in Fig. 2. FIG. 2 is a diagram showing an example of a conventional counter testing method. In the figure, ■ is a counter, 2 is a delay circuit, 3 is a gate, 40 to 43 are free knob flops, Ck is a clock signal, ck' is a load signal, CP is a clock terminal, and ho
From h3 are hold signals, IO to ■3 are input terminals, 00 to 03 are output terminals, qO to q3 are output signals, r is a reset signal, t is C, X and B are 9 times per month. Force ≧ 艷tsu Each 剟 2 口K CK' ふ 2 し]
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Claims (1)

[Scope of Claims] A counter (1) that counts a clock signal (ck) has a holding means (1) that holds an output signal q set to logic "1".
00); and loading means (200) for loading the output signal q held by the holding means (100) into the counter (1).