JPS6276543A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6276543A JPS6276543A JP21560585A JP21560585A JPS6276543A JP S6276543 A JPS6276543 A JP S6276543A JP 21560585 A JP21560585 A JP 21560585A JP 21560585 A JP21560585 A JP 21560585A JP S6276543 A JPS6276543 A JP S6276543A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- island region
- island
- electrode
- zener diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000009966 trimming Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 101100180053 Danio rerio isl2b gene Proteins 0.000 abstract description 2
- 101100126319 Oncorhynchus tshawytscha isl3 gene Proteins 0.000 abstract description 2
- 101001053263 Homo sapiens Insulin gene enhancer protein ISL-1 Proteins 0.000 abstract 2
- 102100024392 Insulin gene enhancer protein ISL-1 Human genes 0.000 abstract 2
- 101001053270 Homo sapiens Insulin gene enhancer protein ISL-2 Proteins 0.000 abstract 1
- 102100024390 Insulin gene enhancer protein ISL-2 Human genes 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体集積回路の抵抗のツェナー・ザソプ・トリミング
において、トリミングする抵抗の島電位と電源電圧の間
にダイオードを挿入し、トリミング時に、電流漏れが生
じないようにし、ツェナーダイオードの破壊を容易にす
る。[Detailed Description of the Invention] [Summary] In Zener-Zasop trimming of resistors in semiconductor integrated circuits, a diode is inserted between the island potential of the resistor to be trimmed and the power supply voltage to prevent current leakage during trimming. , making it easier to destroy the Zener diode.
この発明は、半導体集積回路の抵抗のトリミングに係り
、特に抵抗に並列接続したツェナーダイオードの破壊で
トリミングを可能とする半導体集積回路の改良に関する
。The present invention relates to trimming of a resistor in a semiconductor integrated circuit, and more particularly to an improvement in a semiconductor integrated circuit that enables trimming by destroying a Zener diode connected in parallel to the resistor.
半導体集積回路内で基準電圧を発生させるような場合、
その電圧を小さな規格範囲に入れるには、抵抗のトリミ
ング、を行なうことが必要になる。When generating a reference voltage within a semiconductor integrated circuit,
Trimming of the resistor is required to bring the voltage within a small specification range.
従来、半導体集積回路の抵抗のトリミングはツェナーダ
イオードの破壊を利用して行なわれている。第４図にそ
の回路図例を示している。Conventionally, trimming of resistors in semiconductor integrated circuits has been carried out using destruction of Zener diodes. FIG. 4 shows an example of the circuit diagram.
トリミングする必要のある抵抗を予めＲ１、Ｒ２等と分
割して形成しておき、そのグランド側の抵抗の一つＲ２
に並列にツェナーダイオードＤ１を接続しておく。半導
体集積回路において抵抗Ｒ２は半導体の島領域ＩＳＬに
形成され、ツェナーダイオードＤ１は他の島領域に形成
される。ツェナーダイオードＤ１と抵抗Ｒ２の接続ノー
ドＮｔは外部端子］゛、スイッチＳＷを介して定電流源
ｒｃに接続し、ツェナーダイオードＤ、が破壊する電流
を印加してり、を破壊し、Ｒ２を短絡して抵抗をトリミ
ングする。The resistor that needs to be trimmed is divided into R1, R2, etc. in advance, and one of the resistors on the ground side, R2, is formed.
A Zener diode D1 is connected in parallel with the . In the semiconductor integrated circuit, the resistor R2 is formed in a semiconductor island region ISL, and the Zener diode D1 is formed in another island region. The connection node Nt between the Zener diode D1 and the resistor R2 is connected to the constant current source rc via the switch SW, and a current that destroys the Zener diode D is applied, which destroys the Zener diode D and shorts R2. to trim the resistor.
第５図にツェナーダイオードＤ、の逆方向電流−電圧特
性を示してあり、ツェナーの接合を破壊するに足る定電
流を印加する場合、成る高電圧■、を通過して接合破壊
に到る。FIG. 5 shows the reverse current-voltage characteristics of the Zener diode D, and when a constant current sufficient to destroy the Zener junction is applied, the high voltage (2) passes through and the junction is destroyed.
ところで、通常、トリミングする抵抗の島領域ｌ５ＬＯ
島電位の取り方としては、回路で最も高い電位Ｖｃｃに
つりあげている。第６図にトリミングすべき抵抗の島領
域ＩＳＬの部分の断面図を示してあり、ｎ型エピタキシ
ャル層をｐ＋拡散で分離し島領域ＩＳＬを形成し、ベー
ス拡散でｐ型拡散抵抗Ｒ２を形成している。、第４図の
ように、Ｒ２の電極１はツェナーダイオードＤ１との接
続ノードＮｔ、定電流源１ｃに接続し、他方の電極２は
抵抗Ｒ２に接続している。そして島領域ｌ５ＬＯｎ型領
域にコンタクトする島電極３は回路で最も高い電位の電
源Ｖｃｃに接続する。このように構成されているので、
通常の回路動作時にはｐ型拡散抵抗層と島領域ｌ５ＬＯ
ｎ型層で形成されるｐ−ｎ接合は逆バイアスされ、拡散
抵抗層から島領域ＩＳＬに電流が漏れることが防止され
るようになっている。By the way, usually the resistor island region l5LO to be trimmed
The island potential is raised to the highest potential in the circuit, Vcc. FIG. 6 shows a cross-sectional view of the resistor island region ISL to be trimmed. The n-type epitaxial layer is separated by p+ diffusion to form the island region ISL, and the base diffusion is used to form the p-type diffused resistor R2. ing. , as shown in FIG. 4, the electrode 1 of R2 is connected to the connection node Nt with the Zener diode D1 and the constant current source 1c, and the other electrode 2 is connected to the resistor R2. The island electrode 3 in contact with the island region 15LOn type region is connected to the power supply Vcc having the highest potential in the circuit. Since it is configured like this,
During normal circuit operation, the p-type diffused resistance layer and the island region l5LO
The pn junction formed by the n-type layer is reverse biased to prevent current from leaking from the diffused resistance layer to the island region ISL.
ところが、トリミング時に定電流源１ｅから電流を印加
すると、第５図のように高電圧Ｖ、を経てツェナー接合
破壊に到るが、その時、■１が条件によっては高くなる
ことがある。例えば、ＴＴＬの場合Ｖｃｃは５ｖ程度で
あるが、ツェナーダイオードＤ、の破壊電圧■１はプロ
セスによっては３０Ｖ程度になることもある。その場合
、第６図の拡散抵抗層と島領域ＩＳＬ間に形成されてい
るｐ−ｎ接合が順バイアスになり、図示の破線のように
順方向ダイオードでＶｃｃに接続されるかたちになり、
電流がＶＣＣに漏れてしまう。その結果、ツェナーダイ
オードＤ１が破壊しにくくなるという問題が生じる。However, when a current is applied from the constant current source 1e during trimming, Zener junction breakdown occurs through a high voltage V as shown in FIG. 5, but at that time, (1) may become high depending on the conditions. For example, in the case of TTL, Vcc is about 5V, but the breakdown voltage (1) of the Zener diode D may be about 30V depending on the process. In that case, the p-n junction formed between the diffused resistance layer and the island region ISL in FIG. 6 becomes forward biased, and is connected to Vcc by a forward diode as shown by the broken line in the figure.
Current leaks to VCC. As a result, a problem arises in that the Zener diode D1 becomes difficult to break down.
本発明は、上記従来のツェナーダイオード破壊による抵
抗のトリミングでは、漏れ電流によりツェナーダイオー
ドが破壊しにくくなるという欠点を解決しようとするも
のである。The present invention aims to solve the drawback that in the conventional trimming of a resistor by breaking down the Zener diode, the Zener diode becomes difficult to break down due to leakage current.
本発明においては、上記問題点を解決するために、トリ
ミングする抵抗の島電位と電源電圧の間にダイオードを
挿入するようにする。すなわち、本発明は、第１の島領
域内にトリミングすべき抵抗を有し、また第２の島領域
に該抵抗の１つに並列に接続した第１のダイオード（ツ
ェナーダイオード）を有する半導体集積回路において、
第３の島領域に第２のダイオードを有し、該第２のダイ
オードは、一端を前記第１の島領域の島電極に接続し他
端を電源端子に接続し、前記第１のダイオードに電流を
印加しその接合を破壊して抵抗のトリミングを行なう際
に電流が該電源端子側に漏れるのを防止するようにした
半導体集積回路を提供する。In the present invention, in order to solve the above problems, a diode is inserted between the island potential of the resistor to be trimmed and the power supply voltage. That is, the present invention provides a semiconductor integrated circuit having a resistor to be trimmed in a first island region and a first diode (Zener diode) connected in parallel to one of the resistors in a second island region. In the circuit,
A second diode is provided in the third island region, and the second diode has one end connected to the island electrode of the first island region, the other end connected to the power supply terminal, and the second diode connected to the first diode. Provided is a semiconductor integrated circuit which prevents current from leaking to the power supply terminal side when trimming a resistor by applying current and breaking the junction.
第１図を採って説明すると、図は先に示したツェナーダ
イオードＤ１を含む従来の回路と同じ部分をあられして
おり、各部の符号は統一しである。Ｄ２と指示するのが
ＶｃｃとＲ２の島領域ＩＳＬとの間に介在するダイオー
ドであり、そのアノードをＶｃｃに接続し、カソードを
島領域ＩＳＬの島電極に接続している。Referring to FIG. 1, the figure shows the same parts as the conventional circuit including the Zener diode D1 shown above, and the reference numerals of each part are the same. A diode designated as D2 is interposed between Vcc and the island region ISL of R2, and its anode is connected to Vcc, and its cathode is connected to the island electrode of the island region ISL.
以上の構成によれば、ツェナーダイオードＤ１を破壊す
る際ツェナーダイオードの接合破壊に要する電圧Ｖ、が
Ｖｃｃより高くなるときダイオードＤ２は逆バイアスに
なり、定電流源１ｃの印加電流はＶｃｃに漏れることが
防止される。According to the above configuration, when the voltage V required to destroy the junction of the Zener diode D1 becomes higher than Vcc, the diode D2 becomes reverse biased, and the current applied by the constant current source 1c leaks to Vcc. is prevented.
一方、通常の回路動作時には、ダイオードＤ２は順方向
に接続しているから同等障害にならず、島領域ＩＳＬの
島電位を高電位につりあげ、拡散抵抗層からの電流漏れ
を通常のように防止する。On the other hand, during normal circuit operation, diode D2 is connected in the forward direction, so it does not cause the same failure, raises the island potential of island region ISL to a high potential, and prevents current leakage from the diffused resistance layer as usual. do.
第２図に本発明の実施例の要部の平面構成を表している
。第２図において、各部に付した符号は第１図と統一し
である。ただし、この場合第１図と異なり、トリミング
する抵抗Ｒ２のみでなく抵抗Ｒ，も同一の島領域ＩＳＬ
＋に形成している。ツェナーダイオードＤ、は島領域
ｌ５Ｌ２に形成し、ダイオードＤ２は島領域ＩＳＬ ３
に形成している。FIG. 2 shows a planar configuration of essential parts of an embodiment of the present invention. In FIG. 2, the symbols assigned to each part are the same as in FIG. 1. However, in this case, unlike in FIG. 1, not only the resistor R2 to be trimmed but also the resistor R is in the same island region ISL.
+ is formed. Zener diode D is formed in island region l5L2, and diode D2 is formed in island region ISL3.
is formed.
抵抗Ｒ２の電極１２は接地し、他の電極１１はツェナー
ダイオードの電極２１と外部端子Ｔに接続している。島
領域ＩＳＬ、の島電極１３はダイオードＤ２のカソード
電極３１に接続し、Ｄ２のアノード電極３２は高位の電
源電圧Ｖｃｃに接続している。The electrode 12 of the resistor R2 is grounded, and the other electrode 11 is connected to the electrode 21 of the Zener diode and the external terminal T. The island electrode 13 of the island region ISL is connected to the cathode electrode 31 of the diode D2, and the anode electrode 32 of D2 is connected to the higher power supply voltage Vcc.
ツェナーダイオードＤ、及びダイオードＤ２はそれぞれ
半導体集積回路のベース拡散やエミッタ拡散を利用して
形成される。或いは、これらを、バイポーラトランジス
タをダイオード接続して用いることもできる。The Zener diode D and the diode D2 are each formed using base diffusion and emitter diffusion of a semiconductor integrated circuit. Alternatively, these can also be used with bipolar transistors connected in a diode manner.
例えばダイオードＤ２の場合は逆方向に比較的高電圧が
かかっても破壊されないことが要求され、例えば、第３
図（Ａ）のようにエミッターベースを短絡したダイオー
ド接続のトランジスタを用いる。また、第３図（Ｂ）の
ｐｎｐラテラルバイポーラトランジスタの場合はコレク
ターベース短絡のダイオード接続で十分高耐圧を得るこ
とができる。For example, in the case of diode D2, it is required that it not be destroyed even if a relatively high voltage is applied in the reverse direction.
As shown in Figure (A), a diode-connected transistor with its emitter and base shorted is used. Further, in the case of the pnp lateral bipolar transistor shown in FIG. 3(B), a sufficiently high breakdown voltage can be obtained by connecting the collector base with a short-circuited diode.
以上、本発明に関して抵抗が形成される島領域がｎ型で
、ｐ型拡散抵抗をトリミングする例で説明したが、本発
明はｐ型島領域のｎ型拡散抵抗のトリミングに通用する
こともできる。その場合、ｐ型島領域は漏れ電流をなく
すため最も低い電位に接続され前記例と各部の極性が逆
になる。The present invention has been explained above using an example in which the island region where the resistor is formed is n-type and the p-type diffused resistor is trimmed, but the present invention can also be applied to trimming the n-type diffused resistor in the p-type island region. . In that case, the p-type island region is connected to the lowest potential to eliminate leakage current, and the polarity of each part is reversed from the above example.
以上のように本発明によれば、抵抗のトリミングをする
ために、外部から定電流を供給してツェナーダイオ−１
’Ｄ、を破壊する際、ツェナーダイオードの接合破壊に
要する電圧Ｖ、が鳥電極に接続する電源電圧よりより大
きくなっても、抵抗の島電位と電源の間に挿入されてい
るダイオードＤ２が逆バイアスになり、定電流源ｒｃの
電流が電源に漏れることが防止され、したがって、ツェ
ナーダイオードＤ、の破壊を容易に行なうことができる
。As described above, according to the present invention, in order to trim the resistor, a constant current is supplied from the outside to the Zener diode.
'D, even if the voltage V required to break the junction of the Zener diode becomes larger than the power supply voltage connected to the bird electrode, the diode D2 inserted between the island potential of the resistor and the power supply is reversed. The current from the constant current source rc is prevented from leaking to the power supply, and therefore the Zener diode D can be easily destroyed.
第１図は本発明を説明するための回路図、第２図は本発
明の実施例の平面構成図、第３図（Ａ）（Ｂ）はトラン
ジスタのダイオード接続例の説明図、第４図は従来例の
回路図、第５図はツェナーダイオードＤ１の破壊を示す
電流電圧特性図、第６図はトリミングする抵抗の島領域
ＩＳＬの部分を示す断面図である。
主な符号
Ｒ，ｌ？！２・・・Ｉ・リミングする抵抗Ｄ１ ・
・・ツェナーダイオード（第１のダイオード
Ｄ２ ・・・ダイオード（第２のダイオード）ＩＳ
Ｌ ・・・島領域
Ｉｃ ・・・定電流源FIG. 1 is a circuit diagram for explaining the present invention, FIG. 2 is a plan configuration diagram of an embodiment of the present invention, FIG. 3 (A) and (B) are explanatory diagrams of an example of diode connection of transistors, and FIG. 4 5 is a current-voltage characteristic diagram showing breakdown of the Zener diode D1, and FIG. 6 is a sectional view showing a portion of the island region ISL of the resistor to be trimmed. Main code R, l? ! 2...I Rimming resistance D1 ・
... Zener diode (first diode D2 ... diode (second diode) IS
L...Island region Ic...Constant current source
Claims (1)
体層で形成した少なくとも１つの抵抗を有し、また第２
の島領域に該抵抗の１つに並列に接続したツェナーダイ
オードを有する半導体集積回路において、 第３の島領域に第２のダイオードを有し、該第２のダイ
オードは、一端を前記第１の島領域の島電極に接続し他
端を電源端子に接続し、前記ツェナーダイオードを電流
の印加で破壊して短絡することにより抵抗のトリミング
を行なう際に電流が該電源端子側に漏れるのを防止する
ことを特徴とする半導体集積回路。[Scope of Claims] At least one resistor formed of a semiconductor layer of a conductivity type different from that of the first island region, and a second resistor formed of a semiconductor layer of a conductivity type different from that of the first island region;
A semiconductor integrated circuit having a Zener diode connected in parallel to one of the resistors in an island region, a second diode in a third island region, the second diode having one end connected to the first resistor. Connect to the island electrode of the island region, connect the other end to the power supply terminal, and destroy the Zener diode by applying current to short-circuit it to prevent current from leaking to the power supply terminal side when trimming the resistor. A semiconductor integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60215605A JPH0693488B2 (en) | 1985-09-28 | 1985-09-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60215605A JPH0693488B2 (en) | 1985-09-28 | 1985-09-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276543A true JPS6276543A (en) | 1987-04-08 |
| JPH0693488B2 JPH0693488B2 (en) | 1994-11-16 |
Family
ID=16675196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60215605A Expired - Fee Related JPH0693488B2 (en) | 1985-09-28 | 1985-09-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693488B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277622A (en) * | 1999-01-18 | 2000-10-06 | Sony Corp | Semiconductor device and its manufacture |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54158885A (en) * | 1978-06-06 | 1979-12-15 | Nec Corp | Semiconductor integrated circuit |
| JPS55127053A (en) * | 1979-03-08 | 1980-10-01 | Nat Semiconductor Corp | Onnchip trimming integrated circuit |
-
1985
- 1985-09-28 JP JP60215605A patent/JPH0693488B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54158885A (en) * | 1978-06-06 | 1979-12-15 | Nec Corp | Semiconductor integrated circuit |
| JPS55127053A (en) * | 1979-03-08 | 1980-10-01 | Nat Semiconductor Corp | Onnchip trimming integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000277622A (en) * | 1999-01-18 | 2000-10-06 | Sony Corp | Semiconductor device and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0693488B2 (en) | 1994-11-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |