JPS6275842A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce the load of a programmer by adding newly a clear setting mode where the inside of a certain area is entirely set at 1 or 0 and then skipping the action sequence for reading source data after detecting said clear setting mode. CONSTITUTION:The destination data is usually read out via a date circuit 15 according to an action sequence indicated by a sequence control circuit 14 and supplied to a logical operation circuit 11. Then the destination data undergoes the logical operation with the source data that is already supplied to the input terminal at the other side of the circuit 11 in accordance with a designated function. Then a destination bus is rewritten via the circuit 15 to finish a cycle. In a clear setting mode a function code is set to a function register 12 and a decoder 13 analyzes this function code to send a clear setting mode signal to the circuit 14. Receiving this signal, the circuit 14 is set under a clear setting mode. In such a clear setting mode the source reading action is not carried out any more. Then the action sequence includes only a destination reading action.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic device that performs operation transfer.

[Technical background of the invention and seven problems]

In recent years, high-performance workstations, which are different from conventional personal computers, intelligent terminals, or graphic terminals, have been attracting attention. For workstations, the man-machine interface is the most important design element.
3 degrees of 1 practice is required. In addition to the conventional character display.

Bitmap control technology that can fuse solid images into eyelids is essential.

In order to realize the above bitmap control, we need hardware for operation transfer.

A single computing device is required. Operation transfer means source address and destination address,
By specifying three functions, a logical operation is performed on the source data and destination data according to the function code, and the result of the logical operation is written to the destination address location. As a result, this operation can be performed on data within a certain range, for example, data within an arbitrary rectangular area in the case of a display, and dot development of characters, figures, and images can be realized at high speed.

FIG. 3 shows the hardware for carrying out the transport operation, and FIG. 4 shows its basic operation sequence. The operation transfer hardware has a logic operation circuit (ALU3z) as its main component, and one transfer cycle consists of source data read-destination write (incorporating operation results), and the data is stored in the common memory 32. Information such as written characters, figures, images, etc. is developed in 33 heads using a pit map method. In addition, 34 is pass control goo),,? 5 is a function line, 36 is a memory path, and 37 is a source data line 1. t8 is the destination data line. Also, in the basic operation sequence shown in Figure 4, the source, destination, and function have already been set.

By the way, according to the above-mentioned operation transfer hardware, it is necessary to repeat the above-mentioned basic operation sequence even if all areas in a certain area are set to @1' or "0".Therefore, the programmer needs to repeat each I? It was a huge burden to have to set the parameters.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and only when it becomes necessary to set all areas in a certain area to '1' or 'Om', the source address is set to '1' or 'Om'. Eliminates the need to set parameters, and allows you to clear everything by just setting the destination.
The purpose of this invention is to provide an arithmetic device that reduces the burden of program hoaxes by realizing all sets.

[Summary of the invention]

In order to achieve the above object, the present invention newly establishes a clear set mode that sets everything in a certain area to 11# or 10'', and by detecting this, skips the source data read operation sequence and executes operation transfer. For this reason, a decoder for detecting the above mode and a sequence control circuit for making the above operation sequence variable when the clear set mode is detected by the decoder are added.

This reduces the burden on the programmer (firmware) and improves the processing speed during clear set mode 1.

[Embodiments of the invention]

The present invention will be explained in detail below using the drawings. 1st
The figure is a block diagram showing an embodiment of the present invention. In the figure, 11 is an arithmetic logic unit (ALU) that executes a specified operation. As the fourth ration mode,
In addition to the conventional logical operation modes such as OR, AND, and INVERT, a new clear mode set is added.

This mode is set in the funxilan register 12. 13 is a decoder. Decoder 13 is funxy 1
The mode set in the mode resolver 12 is analyzed and the sequence control circuit 14 is notified. Sequence control circuit 1
4 follows the analyzed mode, follows a predetermined sequence, and all kinds of control signals such as memory REM, ITE, etc. 5 is a dirt circuit that controls destination data, and 16 is a memory path. .

FIG. 2 is a diagram showing the operation sequence at the time of clear setting in the present invention. In this figure, it is assumed that parameters such as functions have already been set.

The operation of one embodiment of the present invention will be explained in detail below. Normally, the destination data is read out via the dart circuit 15 according to the operation sequence instructed by the sequence control circuit 14, and is supplied to one input terminal of the logic operation circuit 11, and the source data that has already been supplied to the other input terminal is Performs logical operations according to data and specified faction,
One cycle is completed via the f-to circuit 15 and a destination path WR device (not shown). This basic operation sequence is as shown in FIG.

Next, the operation in clear set mode will be explained. First, a funk code is set in the funk code 12. The decoder 13 analyzes the function code set in the funk-n-run register 12VC, and when recognizing that it is all set or all clear, sends a mode signal called clear set mode to the sequence control circuit 14. The sequence control circuit 14 enters the clear set mode by receiving this signal.

In the clear set mode, as shown in FIG. 2, there is no source read operation and only the destination read is present, and the sequence control circuit 14 generates a control signal in accordance with the operation sequence.

Although the internal configuration of the sequence control circuit 14 will not be described in detail, the sequence skip control and the like can be performed using a conventional conventional circuit configuration, so the explanation is intentionally omitted here.

〔Effect of the invention〕

As explained above, according to the present invention, in the clear set mode, there is no need to read the source, so it is sufficient to read the destination code, and the number of operations for setting the A parameter is halved, reducing the burden on the programmer. be done. or,
This frees up the path on the source side, which can be used for other purposes, increasing path usage efficiency, or eliminating the need for source read operations, resulting in additional effects such as improved processing speed. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing its operation sequence, FIG. 3 is a block diagram showing the internal configuration of a conventional arithmetic device of this type, and FIG. 4 is its basic operation. FIG. 3 is a diagram showing a sequence. 11...Logic operation circuit (ALU), 12...Function register, 1j-...Decoder, 14-...
Sequence control circuit, 15・-1'-) circuit, 16...
・Memory path. Applicant's agent Patent attorney Takeshi Suzue Figure 1 and Figure 2

Claims (1)

[Claims] By specifying a source address, a destination address, and a function, a logical operation according to the function is performed on the source data and destination data, and the result is placed within the range of the destination address position. In an arithmetic unit that executes operation transfer for data, the function register in which the code of the above function is set and the function code set in the register are decoded, and the contents of a certain area are set to all "1" or "0". ”, and when the decoder detects the clear set mode, controls the execution sequence of operation transfer by skipping the source data READ operation specified by the source address. An arithmetic device comprising a sequence control circuit.