JPS6275705A - Digital controller - Google Patents

Digital controller

Info

Publication number
JPS6275705A
JPS6275705A JP21490985A JP21490985A JPS6275705A JP S6275705 A JPS6275705 A JP S6275705A JP 21490985 A JP21490985 A JP 21490985A JP 21490985 A JP21490985 A JP 21490985A JP S6275705 A JPS6275705 A JP S6275705A
Authority
JP
Japan
Prior art keywords
logic
signal
series
output signal
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21490985A
Other languages
Japanese (ja)
Inventor
Shinji Sakakibara
榊原 伸二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP21490985A priority Critical patent/JPS6275705A/en
Publication of JPS6275705A publication Critical patent/JPS6275705A/en
Pending legal-status Critical Current

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  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To cause each sequence to make independent operation confirming tests, by artificially making the output signals of optional one sequence of logical operation circuits to be tested to the output signal of a 2/3 logic circuit. CONSTITUTION:If all signals 51a-51c are 'OFF', values of the output signals 41a-41c of a selected logic circuit 4 respectively coincide with values of signals 11a-11c. Moreover, when the signal 51a is 'ON' and the other signals 51b and 51c are 'OFF', the value of the signal 41a is equal to the value of the signal 11a and the value of the signal 41b becomes 'ON' regardless of the value of the signal 11b, and then, the value of the signal 41c becomes 'OFF' regardless of the value of the signal 11c, when the test of a logical operation circuit 1a is executed. Therefore, the output signal of a 2/3-logic circuit 2 becomes equal to the output signal 41a, namely, the value of the output signal 11a of the logical operation circuit 1a. The very same phenomena are obtained when logical operation circuits 1b and 1c are tested. Therefore, the operation confirmation of an optional one sequence can easily be tested without receiving any influences from the output signals of the other two sequences, since the sequence to be tested is independently connected with a mimic device for testing.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は同一の論理演算回路を3系列有する多重化ディ
ジタル制御装置の改良技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improved technique for a multiplexed digital control device having three series of the same logic operation circuit.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

発電プラントのように大規模で高信頼性が要求されるシ
ステムでは多重化された制御装置がしはしは用いられる
。特にオン、オフ等の二値信号を取扱うディジタル制御
装置では論理演算回路を3重化し各系列の出力信号の%
論理をとって、制御対象への出力信号とする構成をとる
ことが多い。
Multiplexed control devices are often used in large-scale systems that require high reliability, such as power plants. In particular, in digital control equipment that handles binary signals such as on and off, logic operation circuits are tripled, and % of the output signal of each series is
It is often configured to take logic and output signals to the controlled object.

このような装置では、実際の機器と組合せる前には慎重
に論理演算回路の動作を確認しなければならず、このた
めには実システムの特性を似せた模擬装置を用意し、こ
れを使って予め動作確認を行なっておく方法がおる。特
にプロセス規模が大きく制御装置で行なら論理演算が複
雑になる程、このようなシミュレーション試験の必要性
が高くなる。
In such devices, it is necessary to carefully check the operation of the logical operation circuits before combining them with actual equipment. To do this, a simulation device that resembles the characteristics of the actual system is prepared and used. There is a way to check the operation in advance. In particular, the larger the scale of the process and the more complex the logical operations performed by the control device, the greater the need for such simulation tests.

第゛3図は、かかる多重化ディジタル制御装置における
シミニレ−ジョン試験の一般的な構成例を示すものでら
る。第3図で論理演算回路1a、lb。
FIG. 3 shows an example of a general configuration for a stain resistance test in such a multiplexed digital control device. In FIG. 3, logic operation circuits 1a and lb.

1c  はそれぞれ全く同一の論理演算を行なうもので
ろフ3重化されている。各論理演算回路の出力信号11
a、llb、llcは2/3論理回路2に入力され、そ
の結果、三入力信号の多数決によって定まる出力信号2
1を得る。制御装置の最終的な出力信号21は制御対象
となるべき実際のプロセスの動作を模擬装置3に入力さ
れこれに応じてプロセス模擬装置の出力が定まシ、これ
はまた論理演算回路1a、lb。
1c each performs exactly the same logical operation and is triplexed. Output signal 11 of each logic operation circuit
a, llb, llc are input to the 2/3 logic circuit 2, and as a result, the output signal 2 is determined by majority decision of the three input signals.
Get 1. The final output signal 21 of the control device is inputted to the simulator 3 to indicate the operation of the actual process to be controlled, and the output of the process simulator is determined accordingly. .

1c  へのフィードバック信号31となシ全体として
閉ループ系を構成することとなる。
The feedback signal 31 to 1c constitutes a closed loop system as a whole.

ところでこのような試験を実施して論理演算回路の動作
を確認する場合、論理演算回路は3系列とも全く同じ論
理演算を行なうものであるから、そのうちのいずれか1
系列について動作確認ができれば充分でらる。しかし第
3図に示す構成では各系列の出力信号は2/3論理回路
2を経由してプロセス模擬装置と接続されるため最終的
な出力信号は%論理によって自動的に決定され、特定の
いずれか1系列の出力信号を直接プロセス模擬装置に入
力することができない。そこで、いずれか1系列を試験
中には、七の系列の出力信号が2/3論理回路の出力信
号となるようにできれば、他の2系列の出力信号の値に
妨害されることなく、その系列単独での機能確認が可能
となるので、3系列同時に試験が容易となる。
By the way, when carrying out such a test to check the operation of a logic operation circuit, since all three series of logic operation circuits perform exactly the same logic operation, it is necessary to check the operation of any one of them.
It is sufficient to confirm the operation of the series. However, in the configuration shown in Figure 3, the output signals of each series are connected to the process simulator via the 2/3 logic circuit 2, so the final output signal is automatically determined by the % logic, and the output signal of each series is automatically determined by the % logic. However, it is not possible to directly input one series of output signals to the process simulator. Therefore, while testing any one series, if it is possible to make the output signal of the seventh series the output signal of the 2/3 logic circuit, the output signal of the other two series will not be interfered with. Since it is possible to check the function of each series alone, it becomes easy to test three series at the same time.

たとえば、論理演算回路をコンピュータのソフトウェア
等で実現した場合、−f:ネぞれのコンピュータでの演
算実行同期に同期がとられていない限シ、各系列の出力
信号には時間的なずれが生じており、これが3系列同時
の試験を一層繁舵なものとする。通常多重化された各系
列については相互の独立性を保つため、上記のような同
期はとらないのが普通である。
For example, if a logic operation circuit is implemented using computer software, there will be a time lag in the output signals of each series unless synchronization is achieved with the execution synchronization of each computer. This makes testing of three trains at the same time even more difficult. Normally, the multiplexed streams are not synchronized as described above in order to maintain their mutual independence.

またl系列のみを活かすために他の2系列の論理演算回
路の電源等をオフにすれば、その2系列の論理出力はと
もにオフまたはオンとなるので、2/3論理回路の出力
は常にオフまたはオンとなり、所定の目的が達成できな
い。
In addition, if you turn off the power supplies of the logic operation circuits of the other two series in order to make use of only the l series, the logic outputs of those two series will both be turned off or on, so the output of the 2/3 logic circuit will always be off. Otherwise, the specified purpose cannot be achieved.

また単純に考えれば、論理演算回路単独でプラント模擬
装置と組合せて試験ができれば、上記の様な問題はない
が、論理演算回路と2/3論理回路とが組み立てられ製
品として完成してから試験工程に入る場合が多い。この
ような場合に論理演算回路単独で試験をするには一度行
なわれた配線を外し、その後再配線をしなければならな
い。さらに論理演算回路の出力信号は制御装置の内部イ
ご号として外部と直接インターフェイスできない場合も
らる。
Also, if you think about it simply, if you can test the logic operation circuit alone in combination with a plant simulation device, there will be no problem like the above, but if you test it after the logic operation circuit and the 2/3 logic circuit are assembled and completed as a product, you will not be able to test it. Often included in the process. In such a case, in order to test the logical operation circuit alone, it is necessary to remove the wiring that has been done once and then rewire it. Furthermore, the output signal of the logic operation circuit is used as an internal signal of the control device when it cannot directly interface with the outside.

〔発明の目的〕[Purpose of the invention]

本発明は3重化した論理演算回路と2/3論理回路とか
らなるディジタル制御装置で、その動作確認を行なう場
合、試験対象となる任意の1系列の論理演算回路の出力
信号を人為的に2/3論理回路の出力信号とし、各系列
単独での動作確認試験を可能とするディジタル制御装置
を提供することを目的とする。
The present invention is a digital control device consisting of a triple logic operation circuit and a 2/3 logic circuit, and when checking its operation, the output signal of any one series of logic operation circuits to be tested is artificially changed. It is an object of the present invention to provide a digital control device that uses the output signal of a 2/3 logic circuit and enables an operation confirmation test of each series independently.

〔発明の概要〕[Summary of the invention]

本発明は3系列るる論理演算回路の出力信号を2/3論
理回路に入力する際、通常時すなわち試験を実施しない
場合にはそのまま入力し、またいずれか1系列の試験を
実施する場合には、残りの2系列のうち1系列の出力を
オン、もう1系列の出力をオフとして入力し2/3論理
回路にて試験対象回路の出力信号が選択される様に構成
し所定の目的を達成するものである。
In the present invention, when inputting the output signal of the three-series ruru logic operation circuit to the 2/3 logic circuit, it is inputted as is in normal times, that is, when no test is performed, and when any one series of tests is performed, the output signal is inputted as is. The output of one of the remaining two series is turned on and the output of the other series is inputted as off, and the output signal of the circuit under test is selected by the 2/3 logic circuit to achieve the specified purpose. It is something to do.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第1図を参照して説明する。 An embodiment of the present invention will be described below with reference to FIG.

第1図において第3図との相違点は、試験信号発生回路
5と選択論理回路4を設けたことである。試験信号発生
回路5は3系列らる論理演算回路のうち試験対象とする
べきいずれか任意の1系列を選択するもので、いずれを
選択するかの決定は人為的に行なう。試験信号発生回路
5の出力信号51a、、51b、51cは、それぞれ論
理演算回路11a、llb、llcが試験対象となって
いる時オンする。
The difference between FIG. 1 and FIG. 3 is that a test signal generation circuit 5 and a selection logic circuit 4 are provided. The test signal generating circuit 5 selects any one of the three series of logical operation circuits to be tested, and the selection is made manually. The output signals 51a, 51b, and 51c of the test signal generation circuit 5 are turned on when the logic operation circuits 11a, llb, and llc are the test targets, respectively.

通常時たとえば実際のプロセスと組合せて使用する時に
は信号51a、51b、51cはオフである。
Normally, for example, when used in combination with an actual process, the signals 51a, 51b, and 51c are off.

選択論理回路は論理演算回路の各出力信号11a。The selection logic circuit is each output signal 11a of the logic operation circuit.

11b、llcを値に応じて論理演算を行ない2/3論
理回路2へ伝達するものでらる。
11b and llc according to their values and transmits them to the 2/3 logic circuit 2.

bま信号51a、51b 、51cがすべてオフとすれ
ば、選択論理回路の出力信号41a、41b、41Cの
値はそれぞれ信号11a、llb、1lcO値に一致す
る。また例えば信号51rをオン、51b、51cをそ
れぞれオフとすれば、すなわち論理演算回路1aの試験
を実施している場合には、信号41aの値は信号11a
の値に等しく、また信号41bの値は信号11bの値に
かかわらずオンとなplさらに信号41cの値は信号1
1Cの値にかかわらず、オフとなる。したがって2/3
論理回路の出力信号41a1すなわち論理演算回路1a
の出力信号11aの値と等しくなる。論理演算回路11
b、 llcを試験対象とする場合も全く同様でろる。
If all the b signals 51a, 51b and 51c are turned off, the values of the output signals 41a, 41b and 41C of the selection logic circuit correspond to the values of the signals 11a, llb and 1lcO, respectively. Further, for example, if the signal 51r is turned on and the signals 51b and 51c are turned off, that is, when the logic operation circuit 1a is being tested, the value of the signal 41a will be the same as that of the signal 11a.
pl, and the value of signal 41b is on regardless of the value of signal 11b, and the value of signal 41c is equal to signal 1.
It turns off regardless of the value of 1C. Therefore 2/3
Logic circuit output signal 41a1, that is, logic operation circuit 1a
is equal to the value of the output signal 11a. Logical operation circuit 11
The same applies when testing B.ILC.

以上のように通常時は、3重化された各系列の出力の%
論理出力が得られ、またいずれか1系列の機能確認を実
施する場合にはその系列の論理出力がそれぞれ制御装置
としての最終出力として与えられる。これによって、任
意のいずれか1系列の動作確認は、その系列単独で試験
用の模擬装置と接続されることになるので、他の2系列
の出力信号に攪乱されることなく容易に試験が可能とな
る。実際のプロセスと組合せて使用する場合には選択論
理回路は各系列の出力信号に何ら影響を与えず、また選
択論理回路の構成要素も論理演算回路に比べて極めて単
純でろるので、3重化による高信頼性稼動状態を維持で
きる。
As mentioned above, under normal conditions, the percentage of the output of each triplexed series is
Logic outputs are obtained, and when the function of any one series is to be verified, the logic outputs of that series are given as the final outputs of the respective control devices. As a result, when checking the operation of any one system, that system alone is connected to the test simulation device, making it easy to test without being disturbed by the output signals of the other two systems. becomes. When used in combination with an actual process, the selection logic circuit has no effect on the output signals of each series, and the components of the selection logic circuit are also extremely simple compared to logic operation circuits, so triplexing is possible. Highly reliable operating conditions can be maintained.

第1図に示す選択論理回路4はOR論理とA N D論
理の順序を入れ替えて第2図の様に構成しても全く同じ
機能が得られる。ところで本発明による選択論理回路は
多重化した論理演算回路の試験を容易にする目的で設け
られているが、実際のプロセスと組合せて使用している
場合でも2系列が同時故障となって運転継続できなくな
った場合にも活用できる。すなわち残りの正常な1系列
を試験信号発生回路5で指定することにょシ、その系列
だけでの仮運転が実施でき、その間に故障の復旧を待つ
ことができる。
Even if the selection logic circuit 4 shown in FIG. 1 is configured as shown in FIG. 2 by changing the order of the OR logic and the AND logic, exactly the same function can be obtained. By the way, the selection logic circuit according to the present invention is provided for the purpose of facilitating testing of multiplexed logic operation circuits, but even when used in combination with an actual process, two series may fail simultaneously and continue operation. It can be used even if you are unable to do so. That is, by specifying the remaining normal series in the test signal generation circuit 5, a temporary operation can be performed using only that series, and during this time it is possible to wait for recovery from the failure.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば3重化ディジタル制御装置
において人為的にいずれか任意の1系列のみを活かすこ
とができるため複雑な論理演算を行なう回路のシミュレ
ーション試験の省力化に効果が大きい。またそれを実現
する選択論理回路の構成も単純でろり、3重化による高
信頼性を損う第1図は本発明によるディジタル制御装置
の一実施例を示すブロック構成図、第2図は選択論理回
路の他の一例を示すブロック構成図、第3図は一般的な
3重化ディジタル制御装置のシミュレーション試験構成
図である。
As described above, according to the present invention, since it is possible to artificially utilize only one arbitrary series in a triplex digital control device, it is highly effective in saving labor in simulation tests of circuits that perform complex logical operations. In addition, the configuration of the selection logic circuit that realizes this is simple, impairing the high reliability achieved by triplexing. Figure 1 is a block configuration diagram showing an embodiment of the digital control device according to the present invention, and Figure 2 is a selection logic circuit. FIG. 3 is a block configuration diagram showing another example of a logic circuit. FIG. 3 is a simulation test configuration diagram of a general triplex digital control device.

la、lb、lc・・・論理演算回路、2・・・2/3
論理回路、3・・・プロセス模擬装置、4・・・選択論
理回路、5・・・試験信号発生回路、lla、11b、
11c・・・論理演算回路出力信号、51a、51b、
51c・・・論理演算回路の試験信号、21・・・%論
理出力信号、41a 、41b、41c・・・選択論理
回路の出力信号。
la, lb, lc...logic operation circuit, 2...2/3
Logic circuit, 3... Process simulation device, 4... Selection logic circuit, 5... Test signal generation circuit, lla, 11b,
11c...Logic operation circuit output signal, 51a, 51b,
51c... Test signal of logic operation circuit, 21...% logic output signal, 41a, 41b, 41c... Output signal of selection logic circuit.

代理人 弁理士 則 近 憲 佑 同  三俣弘文 第2fflAgent: Patent Attorney Noriyuki Chika Same as Hirofumi Mitsumata 2nd ffl

Claims (1)

【特許請求の範囲】[Claims] 同一の演算機能を有し、同一の入力信号を受けて動作す
る3系列の論理演算回路と、3つの論理信号を入力して
、その多数決論理で出力信号を決定する2/3論理回路
とからなるディジタル制御装置において、通常時は各系
列の論理演算回路の出力をそのまま2/3論理回路に伝
達し、また3系列の論理演算回路のうち、いずれか1系
列を指定した場合には、指定された系列の出力信号は変
化させず、残りの2系列のうち片系の出力信号は強制的
にオンとし、もう片系の出力信号は強制的にオフとして
2/3論理回路に伝達する選択論理回路を具備して指定
された系列の論理出力信号が2/3論理回路の出力信号
となる様に構成したことを特徴とするディジタル制御装
置。
Three series of logic operation circuits that have the same operation function and operate in response to the same input signal, and a 2/3 logic circuit that receives three logic signals and determines the output signal based on majority logic. In a digital control device, normally the output of each series of logical operation circuits is transmitted as is to the 2/3 logic circuits, and when any one of the three series of logic operation circuits is designated, the specified The output signal of the selected series remains unchanged, the output signal of one of the remaining two series is forcibly turned on, and the output signal of the other series is forcibly turned off and transmitted to the 2/3 logic circuit. 1. A digital control device comprising a logic circuit and configured such that a specified series of logic output signals becomes an output signal of a 2/3 logic circuit.
JP21490985A 1985-09-30 1985-09-30 Digital controller Pending JPS6275705A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21490985A JPS6275705A (en) 1985-09-30 1985-09-30 Digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21490985A JPS6275705A (en) 1985-09-30 1985-09-30 Digital controller

Publications (1)

Publication Number Publication Date
JPS6275705A true JPS6275705A (en) 1987-04-07

Family

ID=16663575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21490985A Pending JPS6275705A (en) 1985-09-30 1985-09-30 Digital controller

Country Status (1)

Country Link
JP (1) JPS6275705A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0911138A (en) * 1995-06-29 1997-01-14 Maeda Kinzoku Kogyo Kk Bolt/nut fastening device
US8799707B2 (en) 2011-06-28 2014-08-05 Mitsubishi Heavy Industries, Ltd. Redundant system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0911138A (en) * 1995-06-29 1997-01-14 Maeda Kinzoku Kogyo Kk Bolt/nut fastening device
US8799707B2 (en) 2011-06-28 2014-08-05 Mitsubishi Heavy Industries, Ltd. Redundant system

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