JPS6275522U - - Google Patents

Info

Publication number
JPS6275522U
JPS6275522U JP16634885U JP16634885U JPS6275522U JP S6275522 U JPS6275522 U JP S6275522U JP 16634885 U JP16634885 U JP 16634885U JP 16634885 U JP16634885 U JP 16634885U JP S6275522 U JPS6275522 U JP S6275522U
Authority
JP
Japan
Prior art keywords
power outage
level
cpu
circuit
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16634885U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16634885U priority Critical patent/JPS6275522U/ja
Publication of JPS6275522U publication Critical patent/JPS6275522U/ja
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の停電処理回路のブロツク図、
第2図は本考案の停電処略回路を用いた場合の動
作フローチヤート図、第3図は従来の停電処理回
路のブロツク図、第4図は従来の停電処理回路を
用いた場合の動作タイミング図、第5図は従来の
停電処理回路を用いた場合の動作フローチヤート
図。 はCPU、はメモリ、はバツクアツプ回
路、は直流電源回路、は停電検出回路、,
,は入力端子、はリセツト回路。
Figure 1 is a block diagram of the power outage processing circuit of the present invention.
Fig. 2 is an operational flowchart when using the power outage processing circuit of the present invention, Fig. 3 is a block diagram of a conventional power outage processing circuit, and Fig. 4 is an operation timing when using the conventional power outage processing circuit. FIG. 5 is an operation flowchart when a conventional power outage processing circuit is used. is the CPU, is the memory, is the backup circuit, is the DC power supply circuit, is the power failure detection circuit,
, is an input terminal, and is a reset circuit.

Claims (1)

【実用新案登録請求の範囲】 電気信号の「H」レベルから「L」レベルへの
変化を検知できる入力端子と、電気信号の「H
」レベルか「L」レベルかを検知できる入力端子
と、リセツト端子とを具備した比較判断機能
を有するCPUと、 該CPUのデータを記憶するメモリと、停
電時にメモリの内容を保持するためのバツクア
ツプ回路と、商用電源の停電を検出し、入力端
子,へ信号を発する停電検出回路と、停電
回復時にCPUの動作を開始せしめるべくCP
Uのリセツト端子にリセツト信号を発するリ
セツト回路およびこれらの回路に電圧、電流を
供給する直流電源回路より構成されており、 停電の期間が電源周波数の数サイクル分である
瞬時停電と、それ以上に長時間である通常の停電
とをCPUで判断し、瞬時停電の場合はあたか
も停電がなかつたかのように動作し、通常の停電
の場合は停電前の仕事の内容をメモリにて保持
し、停電回復時に期定のシーケンス通り動作せし
めるべく構成された停電処理回路。
[Claims for Utility Model Registration] An input terminal capable of detecting a change from the "H" level of the electrical signal to the "L" level, and the "H" level of the electrical signal.
” level or “L” level, a CPU with a comparative judgment function equipped with a reset terminal, a memory to store the data of the CPU, and a backup to retain the contents of the memory in the event of a power outage. circuit, a power outage detection circuit that detects a power outage in the commercial power supply and issues a signal to the input terminal, and a CPU that starts operating the CPU when the power outage is restored.
It consists of a reset circuit that issues a reset signal to the reset terminal of the U, and a DC power supply circuit that supplies voltage and current to these circuits. The CPU determines whether it is a normal power outage that is a long period of time, and in the case of a momentary power outage, it operates as if there had been no power outage, and in the case of a normal power outage, the content of the work before the power outage is retained in memory and the power outage is recovered. A power outage processing circuit configured to operate according to a regular sequence.
JP16634885U 1985-10-28 1985-10-28 Pending JPS6275522U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16634885U JPS6275522U (en) 1985-10-28 1985-10-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16634885U JPS6275522U (en) 1985-10-28 1985-10-28

Publications (1)

Publication Number Publication Date
JPS6275522U true JPS6275522U (en) 1987-05-14

Family

ID=31097232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16634885U Pending JPS6275522U (en) 1985-10-28 1985-10-28

Country Status (1)

Country Link
JP (1) JPS6275522U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486244A (en) * 1977-12-21 1979-07-09 Nec Corp Information processor
JPS58101348A (en) * 1981-12-11 1983-06-16 Fujitsu Ltd Forced interruption processing system
JPS6025002B2 (en) * 1980-04-14 1985-06-15 松下電器産業株式会社 Porcelain substrate for forming glazed resistors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5486244A (en) * 1977-12-21 1979-07-09 Nec Corp Information processor
JPS6025002B2 (en) * 1980-04-14 1985-06-15 松下電器産業株式会社 Porcelain substrate for forming glazed resistors
JPS58101348A (en) * 1981-12-11 1983-06-16 Fujitsu Ltd Forced interruption processing system

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