JPS6273497A - Nonvolatile memory circuit - Google Patents

Abstract

PURPOSE:To make unnecessary the usage of a high pressure resistant transistor in a read out system by separating a write system and the read out system. CONSTITUTION:B1-Bn have functions to switch high voltages impressed from a terminal W by every line unit. The fundamental cells A(1,1)-A(m,n) of a nonvolatile memory are constituted with four cells and pull-down transistors E1-Em are inserted to a VSS side as resistors because a read signal from a fundamental cell is a binary signal whether it is at a VDD level or at a floating level. When a data is written, a line selection is performed at C1-Cn and a row selection at P1-Pm. When reading, the line selection is performed at r1-rn. Lines on which the high voltages are applied are F1-Fn, separating the read out system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Confectionery] The present invention relates to the wiring and configuration of a nonvolatile memory included in an integrated circuit for an electronic watch.

[Conventional technology]

IPR using FAMO date as conventional non-volatile memory
The cell configuration of the OM was two transistors (FAMO8+write control transistor connected in series to FAMO8) as shown in FIG.

These cells are arranged in a matrix, and the gates of transistors connected in series with IPAMO8 are connected to each other in the Y fx) direction, and the drains of FAMO8 are connected in the X (Y) direction.
wired in the direction.

[Four points and objectives to be solved by the invention] However, in the conventional technology, the writing thread and the reading system are the same system, so the high pressure 1 for writing is reduced to IJI~Dm in Figure 2, Pull-down transistors and these IJ1~! It was necessary to protect the input system of the sense terminal, which operates in response to the Jm signal, from high voltage. The present invention is intended to solve these problems, and its purpose is to eliminate the use of special high-voltage transistors and provide a more compact peripheral circuit.

[Means for resolving intertemporal points]

The present invention is characterized in that a write system and a read system are separated in a nonvolatile memory cell, and the cell structure and wiring are such that a high voltage for writing is not transmitted to the subsequent system. The basic cell consists of four elements: FAMO6, γ2) 4i integrated control transistor/sister, (3) read transistor, ■ read control transistor l, ■ and (ri are connected in series, and (3) and ■ are They are connected in series, and the gates of (ri and ■) are connected.Furthermore, the basic cells are arranged in a matrix, and each cell is connected to each other.The gate of r2 is connected in the X or Y direction, The drain of is in the Xα) direction, and the gate of ■ is in the Y (X
) direction, and the drain of ■ is connected in the Y ('X) direction.

[Effect]

According to the above configuration of the present invention, two elements are assigned to the four-input system, two elements are applied to the continuation system, and the floating gate of the FAMOS and the gate of the small gate transistor are connected. I tried not to join the series.

〔Example〕

FIG. 1 is a diagram showing the entire wiring configuration of a cell according to the present invention. B1
~Bn has a function of switching the high voltage applied from the W terminal in units of all rows. A(1,1) to A(m,n) are basic cells of a non-volatile memory and are made up of four elements. E1~
Km is a pull-down transistor, which is inserted as a resistor on the Vθ side because the continuous signal from the basic cell is a direct signal of either VDD level or floating level.

When writing bootara in this matrix.

01 to On selects a row, and P1 to Pm selects a column. When reading, row selection is performed using r1 to rn.

The high voltage lines F1 to Fn are separated from the continuous system.

FIG. 5 is an example of the genus 1 diagram. First, basic cell A (1,
1) or 1 (corresponding to Figure 1, the same symbols below indicate correspondence), 5
01 is for read control, 502 is for continuous output, 505 is for write control, and 504 is FAMO8. Also, B1 is 505-5
II is formed by five elements of 07. First, in the case of writing, a high voltage is applied to the W terminal. At this time 505 and 5
06 constitutes an inverter, and when C1 is at the Vl)D level, 5Q7 is ON, and when C1 is at the 78th level, 507
Turn id OFF. When the writing line is selected by C1 to an, the level is changed from PI to P m I) to vnn or V.
Whether or not it is written to the FAMO 8 is determined depending on whether it is SS or not. If A (1, 13 is written as 1) (assuming that C is connected, negative I7) is at a high direct voltage and floats, electrons will be injected into the gate of coil 04 due to avalanche breakdown. At the same time, the gate of S02 is also biased to the same 1 (high), so it becomes 0'N state.

This is the state in which 4 have been inserted. On the other hand, if there is no write 1, 502 is OF? It becomes.

The d-extraction is done like an arrow. T golf T any one
By setting the Vss level, the basic cell's 50
1 is ONL, if written, 1.1+ is 'JDD, 4
If it is not loaded, Dl becomes Vss.

FIG. 4 is another implementation according to the invention. When writing, in Figure 5, data is written in row units, but in Figure 4, data is written in column units.

Also, ('21~On) can be randomly addressed instead of setting one to the VDD level.On the other hand, 7
1 to 71 must be given levels such that only the column to be written is set to V81i level, and the rest are set to 'Vnp. The writing and reading principles are the same as in FIG.

The differences between Figures 5 and 4 depend on the shape of the data output compared to the human data input. That is, the fifth
In the figure, the written data is D! Parallel data up to 1.1m is output. In Fig. 44, for example, if we pay attention to IJ+, the written data is output more realistically from LlI. In a watch integrated circuit, especially an analog quartz IC, the unlucky order memory is about 501) IT at most, so the total area including peripheral circuit elements is smaller than the number of elements in the main cell. Like the 51st. Tilt, 4th
All you have to do is separate all the figures.

〔Effect of the invention〕

According to the invention described above, since the first thread and the continuous thread system are completely separated, there is no need to use a high voltage transistor in the continuous thread system, and the reliability of the circuit is improved. In addition, the basic cell is the conventional 2
70 pieces was increased from 1 piece to 4 pieces, but if you consider the fact that it is a small memory in the Tozuke circuit for watches, the peripheral circuit becomes an intermediate wheel, so the occupied surface + the increase in the number of pieces is It won't happen.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the present invention. Figure 2 is a circuit diagram of a conventional non-volatile memory. Figures 5 and 4 are circuit diagrams of actual cutting examples of the present invention. A(1,I) ~A(m,n)-4 cells B1~B
n...Cells E1 to Cm for direct voltage cut-off...Pull-down transistor or more

Claims (1)

[Claims] FAMOS (Aloating-gate Avala
In a watch integrated circuit having an MOS (injection MOS), it is composed of four elements: (1) FAMOS, (2) a write control transistor, (3) a read transistor, and (4) a read control transistor. 2) are connected in series, (3) and (4) are connected in series, and (
Gates (1) and (3) are connected, and (1) to (
4) are arranged in a matrix as basic cells, and the gates of (2) are connected together, the drains of (1) are connected together, the gates of (4) are connected together, and the drains of (3) are connected together in the X and Y directions, respectively. Characteristic non-volatile memory circuit.