JPS6271904U - - Google Patents
Info
- Publication number
- JPS6271904U JPS6271904U JP1985162726U JP16272685U JPS6271904U JP S6271904 U JPS6271904 U JP S6271904U JP 1985162726 U JP1985162726 U JP 1985162726U JP 16272685 U JP16272685 U JP 16272685U JP S6271904 U JPS6271904 U JP S6271904U
- Authority
- JP
- Japan
- Prior art keywords
- line
- transmission line
- impedance
- matching circuit
- reactance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Waveguides (AREA)
- Microwave Amplifiers (AREA)
Description
第1図はこの考案の一実施例によるインピーダ
ンス整合回路を示す斜視図、第2図はこの考案の
他の実施例を示す上面図、第3図は従来のインピ
ーダンス整合回路を示す斜視図である。 図において、1は半導体素子、2は誘電体基板
、4は伝送線路、5はリアクタンス線路、61は
高インピーダンス伝送線路である。なお図中同一
符号は同一又は相当部分を示す。
ンス整合回路を示す斜視図、第2図はこの考案の
他の実施例を示す上面図、第3図は従来のインピ
ーダンス整合回路を示す斜視図である。 図において、1は半導体素子、2は誘電体基板
、4は伝送線路、5はリアクタンス線路、61は
高インピーダンス伝送線路である。なお図中同一
符号は同一又は相当部分を示す。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 誘電体基板上に形成された伝送線路と、該
伝送線路に接続して形成された並列リアクタンス
線路とを備えた半導体素子のインピーダンス整合
回路において、 対向したリアクタンス線路間を接続するための
、上記伝送線路の線路幅より細く形成され、かつ
線路の特性インピーダンスが伝送線路より2倍以
上高い高インピーダンス線路を備えたことを特徴
とするインピーダンセ整合回路。 (2) 上記伝送線路、リアクタンス線路、及び高
インピーダンス線路はマイクロストリツプ線路か
らなることを特徴とする実用新案登録請求の範囲
第1項記載のインピーダンス整合回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985162726U JPS6271904U (ja) | 1985-10-23 | 1985-10-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985162726U JPS6271904U (ja) | 1985-10-23 | 1985-10-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6271904U true JPS6271904U (ja) | 1987-05-08 |
Family
ID=31090263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985162726U Pending JPS6271904U (ja) | 1985-10-23 | 1985-10-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6271904U (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012512556A (ja) * | 2008-12-16 | 2012-05-31 | フリースケール セミコンダクター インコーポレイテッド | 無線アプリケーション用高出力半導体素子および高出力半導体素子の製造方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368074A (en) * | 1976-11-29 | 1978-06-17 | Nec Corp | Microwave ic device and its manufacture |
JPS5737903A (en) * | 1980-08-14 | 1982-03-02 | Nec Corp | Distribution constant type matching circuit |
-
1985
- 1985-10-23 JP JP1985162726U patent/JPS6271904U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5368074A (en) * | 1976-11-29 | 1978-06-17 | Nec Corp | Microwave ic device and its manufacture |
JPS5737903A (en) * | 1980-08-14 | 1982-03-02 | Nec Corp | Distribution constant type matching circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012512556A (ja) * | 2008-12-16 | 2012-05-31 | フリースケール セミコンダクター インコーポレイテッド | 無線アプリケーション用高出力半導体素子および高出力半導体素子の製造方法 |