JPS6269723A - Sampling clock phase controller for analog/digital converter - Google Patents

Abstract

PURPOSE:To immediately obtain a picture with less ringing without adjustment even if any signals are inputted by automatically setting the sampling phase of an A/D converter to a phase, where ringing is minimum, in accordance with an input signal. CONSTITUTION:A VTR signal and a demodulated satellite broadcast signal are inputted to the fixed terminal of a changeover switch 14. On the other hand, an addition data A21 has a value adjusting the sampling phase of the A/D converter 17 so that the ringing of a picture when the satellite broadcast signal is received can be minimized, while an addition data B22 has a value adjusting the sampling phase of the converter 17 so that the ringing of a picture be minimized when the VTR signal is received. Interlocking with the switch 14, the changeover switch 20 is switched. When the input signal is the satellite broadcast signal, the data A21 is selected. The data B22 is selected when the VTR signal is given. Thus even any signals are inputted, the picture with less ringing can be obtained immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for controlling the sampling phase of an A/D converter of a television receiver.

Conventional technology Compared to the current standard television system, MUSE (Multiple Multiplex) is used to compress the band of a high-definition television signal in order to transmit the high-definition television signal, which can provide images with higher definition, over a single channel of satellite broadcasting. Sub-Nyquist sampling encoder Multipul 5ub
-Nyquist Sampling Encoding
) method has been proposed by NHK. References Tasuku Nininomiya et al., “High Definition Television Satellite Single Channel Transmission System (MUSE) J Televisier Society Technical Report System Circuit Study Group, TEBS 95-2. March 22, 1980,
Television Science and Technology Report VOL, 7. y1644゜An outline of this transmission method is shown in FIG. On the transmitting side, a high-definition camera 31
The video signal obtained is converted into a digital signal by an A/D converter 32, subjected to subsampling processing by a subsampling circuit, returned to an analog signal by a D/A converter 34, and converted into an FM signal by an FM modulator 35. Transmit with modulation. On the receiving side, the FM demodulator 36 performs FM demodulation into a baseband signal, and the A/D converter 17 converts it into a digital signal.
A two-dimensional interpolation processing circuit 38 reproduces the signal dropped by the subsampling process, and a D/A converter 39 converts the signal back into an analog signal to display a video signal on a high-quality display 40. 32 and 36 are analog-to-digital converters (hereinafter referred to as A/D converters). 34. 39 are digital-to-analog converters (hereinafter referred to as D/A converters). 35 and 36 are FM modulators and FM demodulators, respectively. 33 is a subsampling processing circuit, and 38 is a two-dimensional interpolation processing circuit.

Here, in order to synchronize the receiver side and the transmitter side, the horizontal synchronization signal shown in FIG. 4 is added to the video signal on the transmitter side. As shown in FIG. 4, the horizontal synchronizing signal is added on the transmitting side so that when the phase of the sampling clock 42 is matched to point a of the horizontal synchronizing signal, the sampling position of the video signal is matched. On the receiving side, the A/D converted synchronization signal "(b
If the result of this calculation is zero, the sampling clock phase is correct. If positive, the phase is ahead, and if negative, the phase is delayed. It is determined that there is.

However, even if the sampling clocks are matched as described above, the sampling position of the video signal may shift.

First, the video signal has a different frequency component from the synchronization signal. In addition, the A/D converter 37
It is difficult to flatten the group delay of the transmission line and signal processing circuit until the signal is input to the signal. If the group delay is not very high, the amount of delay will be different between the synchronization signal and the video signal, and the relative position of the synchronization signal and the video signal will change. There may be cases where sampling cannot be performed at certain positions.

Second, if overshoot or undershoot 43 occurs in the horizontal synchronization signal 41, point a cannot be detected correctly, and the video signal may not be sampled at the correct position.

As shown in FIG. 3, when recording a signal on a VTR, the synchronization signal may be added or changed. It is difficult to add a synchronization signal accurately to the position of the original synchronization signal of a video signal during reproduction. Then, the relative position between the synchronization signal and the video signal changes, and the video signal may not be sampled at the correct position using the clock synchronized with the horizontal synchronization signal described above.

If the sampling position of the video signal shifts, the signal 2a obtained by subsampling the video signal on the transmitting side and the A/D signal on the receiving side
The converted signal 2b is equally lost, and the signals lost due to the subsampling described above cannot be correctly reproduced by full two-dimensional interpolation, resulting in ringing in the image.

Therefore, it is necessary to adjust the phase of the A/D sampling clock from point a of the horizontal synchronization signal to the optimum phase point where ringing is minimized.

FIG. 3 shows the basic configuration of a conventional sampling clock phase control circuit. The transmitted signal is input to the input terminal 11, and the SHF receiver 12 performs FM demodulation and returns it to the Hess band. The de-emphasis circuit 13 removes emphasis, the LPFla performs band limiting, and the A/D converter 17 converts the signal into a digital signal. The phase detection circuit 18 outputs the result of the above calculation as a phase error of the synchronization signal, and the adder 19 adds the phase error of the synchronization signal and the addition data 26, and outputs the phase error of the video signal.

It integrates the phase error of the video signal and absorbs sudden changes. Voltage controlled optical oscillator (hereinafter abbreviated as VCD). 24 is A/D
Generates a sampling clock for converter 17 and integrator 2
The output of 3 controls the phase of the sampling clock.

25 is a terminal for outputting the video signal converted into a digital signal to a signal processing circuit for two-dimensional interpolation or the like. Addition data 21
is data for adjusting the phase of the sampling clock of the A/D converter 17.

Problems to be Solved by the Invention However, with the above-mentioned configuration, as described in the prior art, there is a problem of group delay between satellite broadcasting signals and VTR signals, and a problem of synchronization change when recording VTR signals. Therefore, the relative positions of the video signal and the synchronization signal are different, and the value for adjusting the A/D sampling clock phase to the optimum phase point that minimizes ringing ((added data 21 in Figure 3) may be different. In the conventional sampling clock phase control circuit, it is necessary to readjust the sampling clock phase of the A/D converter to the optimum phase point in the case of satellite broadcast reception and the case of VTR signal reception.

In addition, it is extremely troublesome to make adjustments every time.

The present invention improves this so that even if the input signal is changed, the A/D
An object of the present invention is to provide a sampling clock phase control circuit for an A/D converter that can obtain an image with less ringing without adjusting the sampling clock phase of the converter.

Means for Solving the Problems The present invention provides an A/D converter that receives a subsampled input signal, and a synchronization signal added to the input signal to control the sampling clock of the A/D converter. means for obtaining a phase error; an adder that adds addition data to the phase error and outputs the result; an integrator that integrates and outputs the output of the adder; and an A/D converter using the output of the integrator. a VCO that controls the sampling clock phase of the
an A/D converter having a first switch that selects the input signal from a plurality of input signals; and a second switch that selects the addition data from the plurality of addition data in conjunction with the first switch. This is a sampling clock phase control device.

Effect: With the above-described configuration, the present invention sets the sampling clock of the A/D converter to the optimum phase point where ringing is minimized corresponding to each input signal, no matter which one of the plurality of input signals is input. Since the addition/subtraction data to be adjusted is selected by the second switch linked to the first switch for switching the input signal, an image with minimum ringing can be obtained corresponding to the input signal.

Example Embodiments of the present invention will be described below with reference to FIG.

In FIG. 1, the same parts as those in FIGS. 2 and 3 will be described with the same reference numerals. A satellite broadcast signal is input to the first input terminal 11, and a VT signal is input to the second input terminal 15.
R signal is input. The satellite broadcast signal is input to the SHF receiver 12, FM demodulated, and then sent to the de-emphasis circuit 1.
3 and is input to the changeover switch 14. VT
The R signal is directly input to the changeover switch 13.

The input signal selected by the changeover switch 14 is LPF
Bandwidth limitation is performed at l6, and the signal is converted into a digital signal by an A/D converter 17. The phase detection circuit 18 detects and outputs the phase error of the digitally converted horizontal synchronization signal.

The adder 19 adds the phase error of the synchronization signal and the addition data selected by the switch 2o, which is switched in conjunction with the first switch, and outputs the phase error of the video signal. The control signal obtained by integrating the phase error of the video signal by the integrator 23 is used to control the VCO.
24 controls the phase of the sampling clock of the A/D converter output.

Here, the addition data A21 has a value for adjusting the subsampling phase of the A/D converter so that the ringing of the image is minimized when a satellite broadcasting signal is received, and the addition data B22 has a value that adjusts the subsampling phase of the A/D converter so that the ringing of the image is minimized when a satellite broadcasting signal is received. It has a value that adjusts the subsampling phase of the A/D converter so that the ringing of the A/D converter is minimized.

The second switch 2o is switched in conjunction with the first switch 14 to select addition data A21 when the input signal is a satellite broadcasting signal, and select addition data B22 when it is a VTR signal. Even if this signal is used as an input signal, an image with less ringing can be obtained immediately.

As described in detail, according to the present invention, the sampling phase of the A/D converter is automatically set to the minimum phase of IJ ringing according to the input signal. It is very convenient because there is no need to make adjustments each time.
Since the circuit configuration is also very simple, its practical effects are great.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a sampling phase control device for an analog-to-digital converter in one embodiment of the present invention, and FIG.
FIG. 3 is a block diagram of a conventional analog-to-digital converter sampling phase control device, and FIG. 4 is a waveform diagram of a horizontal synchronizing signal and a clock signal. 12...SHF receiver, 14, 20...
...Selector switch, 18...Phase detection circuit, 1
9... Adder, 21.22, 26...
Addition data, 23...Integrator, 24...
・VCO117...A/D converter. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4

Claims (1)

[Claims] a first switch that selects one of a plurality of subsampled input signals; an analog-to-digital converter that receives the signal selected by the first switch; and a synchronization signal added to the input signal. means for obtaining a phase error of a sampling clock of the analog-to-digital converter; an adder that adds added data to the phase error and outputs the result; and a second switch that selects the added data from a plurality of pieces of added data. an integrator that integrates and outputs the output of the adder; and a voltage-controlled oscillator that controls the sampling clock phase of the analog-to-digital converter using the output of the integrator; A sampling clock phase control device for an analog-to-digital converter, characterized in that a second switch is interlocked.