JPS6269320A - Latch circuit for data priority - Google Patents

Abstract

PURPOSE:To prevent the malfunctions produced in an interruption mode and a bus acquisition mode by holding the input data stored in a latch circuit until it is deleted. CONSTITUTION:A priority circuit A which decides the priority of the input data is provided together with a latch circuit B for the output given from the circuit A, a status circuit C which informs the latch contents of the circuit B to an external device and a control circuit E which controls both circuits A and B to hold the input data stored in the circuit B until it is deleted. A certain interruption request signal is produced and latched by the circuit B. Thus the interruption request signal is once restored although the interruption requests of the same level are produced by clearing the preceding factor after the preceding interruption processing is over. Therefore the interruption processing is carried out again because the edge of the interruption request signal can be viewed with interruptions of the same level. Thus an interruption action is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Priority processing and latch processing are performed on input data, and the output thereof is held until the processing on the data is completed to prevent malfunction of the circuit.

[Industrial application field]

The present invention relates to a data priority launch circuit used in digital transmission equipment and the like.

[Conventional technology]

According to the conventional technology, as a method of processing interrupt request signals, a level indicating the priority is determined for each interrupt request signal, and each interrupt request signal is once input to a priority circuit, and then Usually, a method is adopted in which the order is assigned according to a predetermined priority order, and interrupt request signals of the same level are processed starting from the earliest one in terms of time.

[Problem that the invention seeks to solve]

However, in the conventional method described above, when there are multiple factors that generate the interrupt request signal, if an interrupt from another factor occurs at the same level during interrupt processing, the processing for the previous factor ends. However, even if a factor is cleared, the interrupt request signal will not be restored unless other factors are cleared, so the edge of the interrupt request signal cannot be seen at the same level, and an interrupt request will no longer be generated. There were drawbacks.

[Means for solving problems]

As shown in Figure 1, the above problems include a priority circuit A that determines the priority of input data, a latch circuit B that latches the output from the priority circuit A, and a latch circuit B that latches the output of the priority circuit A. This problem is solved by consisting of a status circuit C1 for notification, a control circuit E that controls the priority circuit A and the launch circuit B, and controls the input data held in the latch circuit B to continue holding it until it is withdrawn. be done.

[Effect]

Interrupt request No. 15 according to the present invention), '7
,, - Since the interrupt request signal is launched by the child circuit, the same i
- Even if a bell interrupt request occurs, if the previous cause is cleared after the previous interrupt processing is completed, the interrupt request signal will be restored once, and the interrupt request signal will be generated again with another request, so the same level interrupt will be generated. Since the edge of the interrupt request signal can be seen during interrupt processing, the interrupt processing is performed again, resulting in the advantage that the interrupt operation is guaranteed.

〔Example〕

The data priority launch circuit referred to here is applied with a large number of interrupt request signals, and if only the interrupt request signal that becomes the data priority launch circuit is applied, it produces an output and continues to maintain this state. In this way, once an interrupt request signal is held, it will continue to be held until that signal becomes invalid, even if a higher priority interrupt occurs in the meantime?・It refers to a circuit.

FIG. 1 is a principle diagram of a data priority latch circuit according to the present invention.

In the figure, 8 is a target order circuit, B is a crawl/7ch circuit, C is a status circuit, D is a timing circuit, and E is a control circuit.The same symbols represent the same objects throughout the figures below.

The present invention is composed of a priority circuit A, a launch circuit B, a status circuit C, a timing circuit D, and a control circuit E, as shown in FIG. 1, and makes it possible to extract necessary signals from input data. It is something.

The input data is selected by the priority circuit A,
It is held in the launch circuit B under the control of the control circuit E via the timing circuit.

Even if this Shisen's high-priority data is input, the retained data will continue to be retained until it is withdrawn, and will not be affected.

Incidentally, the status circuit C is provided so that the external processor MPU can know which data is being held.

FIG. 2 is a detailed circuit diagram of one embodiment of a data priority launch circuit according to the present invention.

In the figure, 1 is an encoder, 2 is a decoder, 3 is an 8-bit branch circuit, 4 and 5 are Nant gate circuits, 6 is a three-state buffer, 7 is a Nant gate circuit, 8 is a counter, 9 is a D-type flip-flop, and 10 is a NAND gate circuit, 11 is a resistor circuit, 12 and 13 are inverters, 14
The gate circuits 15 and 16 are OR gate circuits.

*IR1 to *IR8 are interrupt request lines and negative logic signal input lines.

*IACK1 to *TACK8 are negative logic interrupt enable signal output lines for interrupt causes.

*rNTR is a negative logic interrupt request output line through which this circuit requests an interrupt to the interrupt controller.

*INTA is a negative logic interrupt permission signal input line through which the microcomputer MPU grants interrupt permission to this circuit.

Also, the output terminals of the three-state buffer 6, 71 to 1'/
4,! Y+""Zr2 is a data output.

Note that a clock is constantly supplied to this circuit.

If there is no interrupt request, *■R1 to *IR8 are all “H”.
”, so the inverter 12 output is 2.4
．． 6,ll,I. Terminals 1 and 2, and inverter 13 output. , the 12th terminal becomes "L", each of the 2nd, 6th, 8th, and 11th terminals of the Nant gate circuits 4 and 5 becomes "H", and the layer terminal of the Nant gate circuit 11 output becomes "L".

As a result, the counter 8 is cleared and the output of the D-type flip-flop 9 becomes "H".

Therefore, *lNTR is "H".

In this state, for example, if an interrupt factor occurs in *IR5, *IR5 becomes L''.

As a result, the output of encoder 1 is as follows. The A2 terminal on the output side of encoder 1 is “L”, A. ,. stomach,.

The terminal becomes "H".

Therefore, the 11th terminal of the decoder 2 becomes "L" and all other terminals become H'.

Since the STB terminal of the 8-bit latch circuit 3 is H,
That glue. The 4th terminal becomes "H", the 3rd terminal of the Nant gate circuit 5 becomes "L", therefore the 8th terminal of the Nant gate circuit 10 becomes "H", and the counter 8 generates a ripple carry after counting the clock. The output of the D-type flip-flop 9 becomes "L", closing the Nant gate circuit 7 and stopping the clock. Therefore, the STB terminal of the 8-bit latch circuit 3 becomes "L", and the interrupt request signal is also held.
*lNTR is also held at "L".

At this time, if an interrupt with a lower priority than *lNTR occurs, it is ignored before the KOG 1, and if an interrupt with a higher priority occurs, it is ignored before the 8-bit latch circuit 3.

This state remains as long as *lNTR is valid, and when *INTA returns from the microcomputer MPU side, *IA
When CK5 becomes "L" and *IR5 becomes invalid, the No. 3 terminal of the Nant gate circuit 5 becomes "H", the No. 8 terminal of the Nant gate circuit 10 becomes "L", and the counter 8 is cleared. -d- output of D-type flip-flop 9
As a result, the interrupt request that had been ignored appears at the output of the 8-bit branch circuit 3, and at the same time *lNTR
becomes “H”.

Next, the No. 8 terminal of the Nant gate circuit 10 becomes "I", and after the counter 8 counts the clock 16 times, a ripple carry is generated, and the output of the D-type flip-flop 9 becomes "L", and the interrupt request becomes 8. *lNTR is held in the bit latch circuit 3 and also via the Nant gate circuit 14.
becomes "L" and requests an interrupt to the interrupt controller.

The interrupt request signal once held in this manner continues to be held even if a higher priority interrupt occurs until that signal becomes invalid.

FIG. 3 shows an example of application of FIG.

In the figure, 20.21 is an inverter, 22 is an encoder, 2
3 is a decoder, 24.25 is an inverter, 26 is an 8-bit latch circuit, 27, 28, and 29 are AND gate circuits, 30 is a bus arbiter, 31 is a resistor, 32 is an inverter, 33.34 is a Nant gate circuit, 35. 36 are inverters, respectively.

The example shown in FIG. 3 is also a circuit that operates almost the same as in FIG. 2, and BREQI to 8 are bus request lines, and BACK1
8 is a bus acknowledge line.

In this case, when a bus request is input, encoder 2
2. "11" is output from the 8-bit latch circuit 26 via the decoder 23, the EN terminal becomes "L", the data is held, and the data is continuously output until the bus request is canceled.

In that case, even if a low-priority bus request is input or a high-priority bus request is input, it will not be output to the output side, so the device that outputs the bus request first will not be acknowledged unless it cancels the bus request itself. is output continuously, so malfunctions due to the influence of other bus requests do not occur.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of being able to prevent malfunctions during interrupt operations and malfunctions during lotus acquisition operations.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of a data priority latch circuit according to the present invention. FIG. 2 is a detailed circuit diagram of one embodiment of a data priority latch circuit according to the present invention. FIG. 3 shows an example of application of FIG. In the figure, A is a priority circuit, B is a launch circuit, C is a status circuit, D is a timing circuit, E is a control circuit, 1 is an encoder, 2 is a decoder, 3 is an 8-bit latch circuit, 4
and 5 is a Nant gate circuit, 6 is a three-state buffer, 7 is a Nant gate circuit, 8 is a counter, 9 is a D-type flip-flop, 10 is a Nant gate circuit, 11 is a resistor circuit, 12 and 13 are inverters, and 14 is a Nant circuit Gate circuits, 15 and 16 are OR gate circuits, 20.21 is an inverter, 22 is an encoder, 23 is a decoder, 24.
25 is an inverter, 26 is an 8-bit latch circuit, 27.
28 and 29 are AND gate circuits, 30 is a hash arbiter, 31 is a resistor, 32 is an inverter, 33 and 34 are NAND gate circuits, and 35 and 36 are inverters. Not ≦? Shi month 1 = J: 5 ten two μ? Lahirannaro length, R1 healing n cow 1 prisoner

Claims (1)

[Claims] A priority circuit that determines the priority of input data (
A), a latch circuit (B) that latches the output from the priority circuit (A), a status circuit (C) that notifies an external device of the latched contents of the latch circuit (B), and the priority circuit ( A) and the latch circuit (B), and control the input data held in the latch circuit (B) to continue holding it until it is withdrawn.
E) A data priority latch circuit comprising: