JPS6268379A - Video signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processor according to the preambles of claims 1, 5 and 6.

PRIOR TECHNOLOGY When reproducing a video signal, especially a color television signal, from a record carrier, various errors occur in the signal, which must be compensated considerably in order to achieve as perfect a reproduction as possible. It won't happen. Firstly, there are time and speed errors, and then there are signal loss (dropouts) caused by defective locations on the information carrier.

Furthermore, it is known to store the signals of an image, which are extracted section by section from a magnetic tape as an information carrier, in an image memory so that they can then be read out repeatedly for the reproduction of still images. be.

To meet these challenges, different devices are known that operate on an analog or digital basis.

A known method for compensating for time errors in a color television signal retrieved from an information carrier, in which the color television signal is converted into a digital signal and stored in digital form, is as follows. That is, a first clock signal (C1) is generated. The phase of this clock signal is influenced by a horizontal synchronization signal contained in the color television signal extracted from the information carrier and its frequency is controlled by a first control voltage. The first clock signal (C1) is then used for AD conversion and writing of the digital signal to the first temporary memory. The digital signal is then read from the first temporary memory using the second clock signal (C2). The frequency of the second clock signal is an integer multiple of the horizontal frequency reference signal. Furthermore, the deviation of the scan line period of the digital signal read from the first temporary memory with respect to the scan line period of the reference signal is measured in order to derive the first control voltage. The horizontal pulses of the reference signal are compared in phase with the horizontal frequency pulses of the signal read from the first temporary memory. As a function of the phase difference, the writing of the digital signal into or reading from the memory is controlled in such a way that the time between writing and reading corresponds to the phase difference. Writing the signal read from the memory into a second temporary memory. A digital signal is read from the second temporary memory using a third clock signal (C3) derived from the second clock signal by a controllable phase shift. then performing a phase comparison between the color synchronization signal of the signal read from the second temporary memory and the reference color synchronization signal;
The results of this phase comparison are then stored over one scanning line each time, and a second control voltage used for phase shifting the second clock signal is extracted (see German Patent Application No. 3,026,473).

A digital image memory for still or slow-motion image reproduction can be downstream connected to the circuit arrangement implementing this known time error compensation method.

Problem to be Solved by the Invention The object of the invention is to improve the known method described above in such a way that, on the one hand, the compensation for the above-mentioned errors is carried out in as optimal a manner as possible.

Means for Solving the Problems The video signal processor of the present invention has the following features. That is, a digital image memory is further connected to the circuit for compensating for signal dropout points, and the output side of this digital image memory processes separately the color and luminance components of the digital signal taken out from the image memory. connected to the circuit.

Significant improvements are achieved as follows. That is, the digital signal is supplied to a circuit for determining the speed error, and the output signal of this circuit for determining the speed error is connected to the first and second clock signals provided for generating the first and third clock signals. clock light emitter, the first and third
is supplied to control the frequency of the clock signal.

Advantageous embodiments and refinements of the video signal processor according to the invention are possible by means of the embodiments described in the appended claims.

Embodiments Next, the present invention will be explained in detail with reference to the drawings, with reference to the illustrated embodiments.

Identical elements are provided with the same reference numerals in each figure.

A color television signal (FB
AS) is the output signal of the video magnetic tape device. These signals have inter alia speed and time errors and signal loss (120 tubes out). Compensating for or correcting these errors is the task of the video signal processor illustrated in FIG. In addition, the video signal processor is also provided with an image memory that allows playback at a different speed than during recording. This memory is particularly important in magnetic tape devices in which the signals of each field are distributed and recorded on a plurality of tracks.

Most of the signal processing is then carried out using digital circuits, so that the color television signal supplied to 1 is converted into a digital signal using an AD converter 2.

However, before the color television signals reach the AD converter 2, these signals are processed, as explained below, in order to create more favorable preconditions for the subsequent processing steps.

First, the values are set using a circuit 3 for adjusting the amplification and black level settings, which is known per se. In the circuitry described in more detail in connection with FIG. 2, a predetermined function, hereinafter referred to as ramp, is inserted in the region of the horizontal synchronization signal of a color television signal. This function is later used to accurately detect the phase of the color television signal relative to the clock signal. Then there is the per se known phase switching (Ph
Asenruckschultung) is carried out. This phase switching facilitates later evaluation of the color synchronization signal to detect speed errors. Finally, the color television signal FBAS is routed through a lock filter to prevent aliasing noise.

In order to avoid visually perceptible quantization noise, quantization is performed in an AD converter with a precision of 9 bits. A clock signal C1 is supplied to the AD converter 2, and this signal is combined with the color television signal supplied to the AD converter 2. The frequency of the clock signal is approximately 13.
5 MHz and thus about 3 of the PAL color subcarrier frequency.
Worth twice as much.

The video signal processor shown in FIG. 1 takes into consideration the special characteristics of a magnetic tape device in which one field is distributed and recorded on a plurality of trunks, respectively, as will be explained later. That is, in a magnetic tape device that performs so-called segmented scanning, switching from one magnetic head to another magnetic head is performed multiple times in one field P. This is normally done within a horizontal blanking period. In that case, the horizontal synchronization pulse is lost due to switching. Therefore, the color television signal supplied at point 1 has a synchronization error which is disturbed in each case before the first scan line of the so-called scan line packet. This in itself is not a problem since a new synchronization signal is later added to the color television signal for later reproduction of the signal on a monitor or for radiating the signal via a broadcast transmitter. However, in order to detect time errors, evaluation of the horizontal synchronization pulse is necessary.

Therefore, in known recording and reproducing devices, an extrapolation of the values determined for the subsequent scanning lines is made for the first scanning line of each ξkerat.

However, the video signal processor of FIG.
and 58, the carrier frequency output signal of the magnetic spatula P is supplied directly from the magnetic tape device after corresponding amplification and frequency characteristic correction.

The channel switches 59 connected to the inputs 57 and 58 are controlled in such a way that the switching takes place in each case in the scanning line before the horizontal synchronization pulse in which the signal applied at 1 is switched. The output signal of channel switch 59 is demodulated at demodulator 60 and supplied to pulse separation circuit 61 . This pulse separation circuit is known per se and separates the signals H, V, 2V from the supplied video signal. Signal H is a circuit 4 that forms a ramp signal.
used in

The output signal of the AD converter 2 is supplied to the input sides of a lamp evaluation circuit 12 and a FIFO circuit 13. The lamp evaluation circuit 12 is detailed in FIG. 2 and generates a digital signal indicating the deviation from the predetermined phase relationship between the first clock signal C1 and the horizontal synchronization pulse of the color television signal. Occur. This signal is fed to the control input of the first clock generator 14, which is used to control the phase. The clock signal C1, the phase of which can thus be varied, is supplied on the one hand to the AD converter as a sampling clock, and on the other hand to the logic circuit 15.
The clock signal is supplied to the FIFO circuit 13 as a write clock via the FIFO circuit 13. Using the conditioning circuit formed by circuits 2, 11, 12 and 14, the color television signal and the first
A very precise phase relationship with the clock signal C1 results.

The first clock generator 14 is supplied with a clock signal C2 generated by a crystal oscillator (not shown).

The circuit of the clock generator 14, which will be explained in detail with reference to FIG. as well as ensuring impeccable frequency stability.

In order to compensate for the speed error, it is necessary to control the frequency of the first clock signal C1, for which purpose the circuit 14 is supplied with a corresponding digital signal from a circuit 16 for determining the speed error.

The circuit 16 will be explained in detail with reference to FIG.

The clock signal C1 is transferred from the first clock generator 14 via the logic circuit 15 to the FIFO circuit 13 and thus controls the write clock from the FI-FO circuit 13. In a time error compensator, in a manner known per se, in the logic circuit 15 write and read notes +)
(RAM) 17 is generated.

The RAM 17 has a capacity of approximately two scan lines, so that a time error of up to approximately one scan line can be compensated for by corresponding adressing.

At the output of the RAM 17, a digital signal is then retrieved, the time and speed errors of which have been approximately compensated.

Then the digital signal will have a signal loss (drop-up)
is supplied to a circuit that compensates for the Suitable circuits are known per se and need not be described in detail in the context of the present invention. A particularly advantageous circuit suitable for the video signal processor of the invention is described in German Patent Application No. 35 33 699, co-filed by the applicant.

A circuit 11 is connected downstream of the signal loss compensation circuit 18, in which a signal identifying the switching phase of the color subcarrier and the respective first or second field is inserted into the digital signal. The identification signal of the switching phase is required for later processing.

This is because the color synchronization signal switched using circuit 5 no longer contains this information. Identification of the field r is necessary when reading the color television signal from the image memory for correct scan line interpolation.

Since high precision requirements should be placed on the phase of the color signal in a color television system in which quadrature modulation is carried out, the first stage of the known time error compensator is equipped with an additional stage (also called a precision time error compensator). ) are connected.

The time position of the color television signal is then shifted so that it coincides as precisely as possible with the reference color subcarrier on which the color synchronization signal is supplied.

In the video signal processor shown in FIGS. 1a and 1b, this is solved by the circuit parts described below, in which case correction of speed errors that still remain is carried out.

For this purpose, the digital signal is fed via a DA converter 19 to a phase comparison circuit 20, where the phase of the color synchronization signal is compared with the reference color subcarrier. The output voltage of the phase comparison voltage 20 is supplied via the AD converter 21 to the phase control input side of the second digital clock generator 25 .

After the delay time compensation circuits 19, 20 and 21, the digital signals reach the FIFO circuit 27, where they are written by the highly accurate clock C2. FI
Reading from the FO circuit 27 is performed using the clock C3 sent from the digital clock generator 25. The phase deviation of this clock with respect to clock C2 corresponds to the time error that must be further corrected. The digital signal read out from the FIFO circuit 27 in this way then reaches the DA converter 28, from the output of which the video signal is passed through a low-noise filter which is used to suppress any clock noise still remaining in the signal. 49.

This filter is connected to a blanking circuit 59' for updating the blanking, for which purpose a blanking signal A is supplied to the circuit 59'. 55 in the adder circuit 50
The color synchronization and synchronization signals (black, S-st) supplied at the point are inserted. The color television signal is then passed through switch 47.48 to output amplifier 51.5.
Reach 2. Then the output side 5 of the output amplifier 51.52
3 and 54, the corrected color television signal is extracted for subsequent use.

The output signal of the signal loss compensation circuit 18 is written into the image memory 31 in order to reproduce the television signal at a different speed than at the time of recording, i.e. in a still image, slow motion, quick manner. [Technology] To save cost, digital signals are only written to the image memory 31 with a width of 8 bits. This type of image memory is described in detail in the above-mentioned specification in connection with a magnetic tape device in which scanning of the already mentioned type, in particular segmented scanning, is carried out, and will therefore be described in detail in connection with the present invention. do not have to. The digital color television signal read from the image memory 31 is sent to the signal switch 3 via two one-scan line delay circuits 33 and 34 and an adder circuit 35.
6.

To avoid flicker noise, the added signal is transferred using the signal switch 36 as follows. That is, in the first field period, the color television signal read from the image memory 31 is transferred, and in the second field period, the luminance signals of two consecutive scanning lines are interpolated, and the black color signal is the color of the first field. It is extracted by repeating the signal. A circuit of this type has already been described in German Patent No. 2,264,0759. The evaluation circuit 37 is used to evaluate the information supplied by the circuit 11 regarding the switching times of the respective field P and color subcarriers. The field information is provided to a signal switch 36 for control.

The digital signals appearing at the output of the signal switch 36 for the formation of the luminance signal Y and the color signal C are respectively DA
It is fed to converters 38,39. The analog luminance signal is
Low gas filter 40 with a cutoff frequency of 3MHz
is taken out via the equalizer 41 and added to the adder circuit 42 via the equalizer 41.
supplied to The equalizer 41 is used to increase the sharpness of the edges and can be, for example, an equalizer constructed in a known manner.

The signal sent out by the DA converter 38 is ζnd ξ
The color signal reaches the circuit 44 via the filter 43 as a color signal. This circuit switches the polarity of the color difference signal U, which is changed depending on the operating state when reading out the digital signal from the image memo 'J 31, and adjusts the color difference to match the phase of the reference color subcarrier. Adjust the phase of the signal. This eliminates the 900 error caused by repeatedly reading fields from image memory 31 without phase adjustment. Furthermore, this compensates for any remaining time errors. A circuit suitable for this purpose is described in West German Patent Application No. 3517697.0 "Phase shifter capable of high-speed follow-up control"("5channel l nachsteu") by the present applicant.
erbarer phasenschieber'
)It is described in.

The output signal of the summing circuit 42 is blanked according to specifications in a blanking circuit 45 and a sync signal and a color sync signal are added in another summing circuit 46. By means of the changeover switches 47, 48, a color television signal appears at the outputs 53 and 54, independently of one another, either a color television signal that is read out from the picture memory 31,32, or a color television signal that is routed to the output circuit without picture memory. You can do it like this.

For the video signal processor of the present invention, accurate coupling of the clock signal C1 and the differential video signal is required. The second section describes a circuit for realizing this type of coupling.
This will be explained in detail based on Figs. FIG. 2 shows the circuits 2, 4, 12 and 14 of the device of FIG.

In circuit 3, switch 65 is used to connect pulse former 6.
3 is inserted into the analog video signal.

A pulse former, which can advantageously be realized using a phase-linear low-gust filter, forms the signal R shown in FIGS. 3 and 4.

The important part of the signal R is a gradually rising ramp that starts at the lower control limit of the AD converter 2 and runs symmetrically up to the 50% line of the control limit;
The rise time of this side edge has a value between one and two periods of the clock signal. The signal B thus produced is illustrated in FIG. 3 and is fed to an AD converter 2.

To control the changeover switch 65, from the horizontal synchronization pulse supplied from 61 (FIG. 1),
Using this, a rectangular pulse indicated by D in FIG. 2 is derived. - The gurus former 64 comprises a monostable multi-9ibrator in a manner known per se.

The AD converter 2 is supplied with a clock signal C1. A
From the output of the D-converter 2, a digital color television signal with an accuracy of nine binary digits is derived via circuit point 9 for further processing.

The digital color television signal is also stored in register 68 with nine digit binary precision or nine bit width.
supplied to Register 68 is clocked by clock signal C and further controlled by pulse D generated by pulse former 64.

In FIG. 4, the part of the digital color television signal corresponding to the signal R in the line marked E on an enlarged time scale compared to FIG. 3 is shown as an analog signal for clarity. - A plurality of pulses of the clock signal C occur in the region of the virus D. The corresponding sample value is transferred from the register 68 and reaches another lenostaff0 and window comparator 71. The output signal of the window converter ξlator controls register 70. The window converter ξ-lator, known per se, indicates at its output that the value of the input signal supplied from the register 68 is between the two values input to 72 and 73 (for example 1
0ch and 90ch), it sends out a signal.

Before the start of the ramp, the sample value is very small, so that register 70 is not activated by window comparator 71. The first value greater than 10 times the total amplitude of the signal is written to a register. If a sample value below 90 occurs during subsequent reversion, that value is written in place of the value previously written to register 70. - By using one sample value for adjusting the phase of the sampling clock as explained above, the signal is A phase is generated that is sampled.

Using a programmable read-only memory (FROM) 75 in which the shape of the ramp of signal R is input, the deviation from the ramp center point M of the sample instant on which this sample value is based is determined from the sample value. A shift is required. This value is read from FROM 75 and used to control the phase of clock signal C1.

When correcting time and speed errors, color synchronization signals are evaluated in color television signals. For this purpose, effective preconditions can be created by doing the following:

That is, the color synchronization signal follows a predetermined function of the inserted signal and its amplitude value advantageously corresponds to 50% of the amplitude range of the video signal, as shown in FIG. It overlaps with certain parts.

The clock generators 14 and 25 (FIG. 1) must fulfill the following requirements: the phase as well as the frequency relative to the start of the scan line should be controllable by an externally supplied control signal; The stability should be in the region of 10-6, similar to the color subcarrier;
Phase and frequency must follow changes in the control signal with little delay.

These requirements are hardly met by conventional oscillators such as crystal oscillators and start-stop oscillators. Therefore, the digital clock generator shown in FIGS. 5 and 6 is used.

In the device shown in FIG. 5, the output side 102 is indicated by 101.
and a 20-digit adder having a first input 103 and a second input 104.

The 20-digit binary value on the output side 102 is stored in the 20-stage register 1.
It is connected to the input side of 05. The output of this register is connected to a first input 103 of an adder 101.

Register 105 receives clock signal C supplied to 106.
2.

Each time a clock pulse is supplied to adder 10
The values supplied to input 104 of 1 are added each time. When the adder reaches its maximum capacity, the adder starts again from zero.

The eight lower digits of the input 104 are connected via a register 107 to the input 109 of the first eight digits. The second eight-digit input 110 is connected via another register 111 to the eight higher-order digits of the input 104 .

The digits between the four of the 10 hands on the input side are shown as ground symbols in the figure, but a zero is added to them.

Furthermore, a 1 can be applied via the register 107 to the digit on the input side 104 that has the next highest weight.

A clock signal C2 is supplied to the clock inputs of registers 107 and 111 via input 106. Furthermore, the registers can be alternately blocked by a synchronization pulse which can be supplied to the input 112, for which purpose a synchronization pulse is supplied to the register 107 via an interface 113. Thus, by blocking registers 1°7 and 111 alternately with the synchronization signal applied to 112, the high 8th digit of the short-term input side 104 is applied to 110 on the one hand. On the other hand, during the synchronization pulses, the next most significant weight digit is incremented by 1, and the lowest digit on the input side 104 is injected with the signal supplied to 109. , in which case the remaining digits will be set to zero.

By repeatedly adding the 1 added to the next most significant digit and the value supplied to 109, the output signal of adder 101 or register 105 has a value that increases linearly over time. When the capacity of adder 101 is reached, the value returns to zero again and then rises linearly in time again. The frequency is essentially determined by the 1 added to the next most significant digit. By means of the values supplied to 109, the slope of the rise and thus the frequency of the output signal of register 105 can be controlled in very precise steps. In this case, the frequency of the output signal is of course not the clock frequency, but the analog signal represented by the digital signal.

When the value supplied via the input 110 for a short period of time during the synchronization pulse is transferred to the eight high order digits of the input 104, the linearly rising portion of the sawtooth voltage with respect to time initially value and continues to rise from there. The value of the signal applied to 110 therefore allows for setting adjustment of the phase between the output signal of register 105 and the synchronization pulse applied to 112.

The frequency at the output of register 105 corresponds approximately to 1/4 of the frequency of clock signal C2 supplied to 106.

The sawtooth υ wave function is converted to a sine wave function in programmable read only memory (FROM) 114 to facilitate subsequent frequency multiplication. For this purpose, the conversion value of the sawtooth wave function to the sine wave function is FRO
As a result, when the output signal of the register 105 is input to the address input side, a signal representing a sine wave function appears at the data output side.

In order to derive the clock signal to be generated from the output signal of register 105, adder 101 of register 1.5 is used.
If one chooses to carry out the accumulation process using Therefore, PROM 114 is supplied with only the ten highest digits of the output signal of register 105. The output signal of the PROM 114 also has a width of only 10 bits and is sent to the DA converter 11 via the register 118.
Transferred to 5. The output side of this converter is frequency multiplier 1
16.

The clock signal appearing at the output 117 of this frequency multiplier 116 can vary its frequency in the range of the frequency of the clock signal C2 supplied to 106. Additionally, phase shifts over multiple clock periods are possible. In the circuit used as digital clock generator 14 (FIG. 1), the frequency can be changed in very small steps. Therefore, for example, the change in LSB applied to the input side 109 is 0.46n per scan line.
s corresponds to a change in phase position relative to the horizontal synchronization pulse.

adder 101, registers 105, 107 and 111,
In addition, the circuit 114 can be easily realized using a conventional digital monolayer. Series F (fas
t) TTL modules have been adopted. In this case, the register was realized by a module with the type name F374, in which several registers were connected in parallel due to the high bit width. The adder 101, which was realized by five modules with the model name F283, has a similar configuration. The circuit 114 is a PR with type name TBP 2+541.
OM! This can be realized by a FROM with model name TBP28586. Finally, a suitable A converter is commercially available under the model designation TDCIO16.

Although the construction of a frequency multiplier is not at all difficult for those skilled in the art, we would like to explain a simple construction of a frequency multiplier based on the circuit schematically shown in FIG. Two such frequency multipliers are connected in cascade in circuit 116 (FIG. 5).

A sinusoidal signal output from the DA converter 115 (FIG. 1) is fed via a circuit point 120 to two inputs of a multiplier 121. In this way, a signal appears at the output of multiplier 121 consisting of sinusoidal oscillations with twice the frequency and the same DC voltage component. The DC voltage component itself can also be removed by a simple RC connection. However, in the illustrated circuit, in addition to the DC voltage component, the multiplier 121
A P-ξ filter 22, 23, 24 is provided to remove harmonics that may possibly arise due to the non-linearity of the signal. A sinusoidal oscillation with twice the frequency is then extracted at the output 125.

It is also possible to use other circuits as frequency multipliers, for example PLL circuits.

FIG. 7 schematically illustrates the insertion and separation of 2 H pulses and 2 V pulses as performed in circuits 11 and 37 (FIG. 1). Two of the nine parallel data lines have a changeover switch 13 controlled by a pulse former 133.
1,132 are inserted and connected. The pulse former is clocked by the horizontal pulse H and is 500 ns
A width of 6 pulses is sent to the changeover switches 131 and 132. During this time, the 2H-ξ and 2v-ξ pulses supplied by circuit 61 (FIG. 1) are inserted.

During the remainder of the scan line period, the changeover switch 131
and 132 are in the upper position, thus the seventh
and switches the line to the conductive state for the eighth bit.

In circuit 37, the lines for the seventh and eighth bits are connected to the input side of a dual D register 134 clocked by pulse H. Pulses 2H and 2■ are then taken out to the output side of the D register.

FIG. 8 shows in detail the circuit 16 (FIG. 1) for detecting speed errors. Circuits 2.12.13 and 14 and their operation have already been explained in connection with FIG.

Digital color TV, circuit 1 where the Kuyon signal is supplied
26 constitutes a selection circuit which forms selected sample values during the color synchronization signal. In the circuit 136, it is determined whether the sampled values of the digital signal during the color synchronization signal are in a region where the slope of the sinusoidal function is sufficiently large in order to obtain perfectly accurate data regarding the phase position with each sampled value. will be examined as to whether

This occurs in the amplitude range of the color synchronization signal, ie at a phase where the sine wave lies between -0.5 and +0.5.

The output signal of circuit 136 is provided to an arcsizing/shaping circuit 137 for converting the sampled values into phase values. circuit 1
37 essentially consists of a read-only memory (PROM) in which a corresponding function table is written. Since the color synchronization signal may be superimposed with statistical noise that adversely affects the phase measurement, an average value from the manual measurements in the color synchronization signal is formed in circuit 138.

As defined by the phase adjustment using the circuit 12, the clock signal C1 can have a jump in phase at the beginning of a scan line, so that the phase control signal corresponding to this jump in phase is The value of circuit 1 is calculated in subtraction circuit 139.
38 output signals. The previously determined signal characterizing the absolute phase position of the color synchronization signal is retrieved characterizing the scan line length using a D register 140 and a subtraction circuit 141 supplied with the clock signal H. According to the commutator, another order of subtraction can also be chosen.

Using programmable read-only memory 142, this value is compared to a target value for scan line length. This target value is stored in a programmable read-only memory as the phase angle of the color subcarrier.

At the output of the circuit 142, therefore, a value of the speed error appears, which is related to the frequency of the clock signal C1. The frequency of the clock signal C1 is again dependent on the frequency control signal supplied to the clock generator 14. The frequency control signal is therefore added in adder 143 to form the absolute value of the speed error. The signal thus generated is passed through the D register 144 to the clock generator 1.
4 as a frequency control signal for the next scan line.

The velocity error signal may be averaged over multiple scan lines, which is shown in register 145.
and adder circuit 146.

In magnetic tape devices that perform segment scanning,
A separate derivation of the correction signal for each first scan line of a segment may be necessary. This form Ω
The circuit is indicated at 147 and will be described in detail in connection with FIGS. 9 and 10. Switch 1 controlled by Hera P alternation/Gurus K via control circuit 149
48, the output signal of circuit 147 is inserted into the correction signal for another scan line.

The waveform diagram illustrated in FIG. 9 illustrates speed errors as may occur in the signal provided to the video processor of FIG. 1 as a function of time. The curve shows the course of the velocity error in the four segments 1, 2, 3 and during the raw sampling period. At the beginning of each segment there is a sharp change A or day, while the velocity error changes very little within a segment of 52 scan lines. Segments 1 and 3 are reproduced by a first magnetic spatula P and segments 2 and 4 are reproduced by a 4-digit second magnetic spatula r.
played by.

It is thus observed that the abrupt change in velocity error remains substantially constant during the transition from one head to the other spatula P. However, the height of the overall velocity error is subject to other statistical fluctuations.

The method of use starts from the following:

This means that the velocity error within a segment can be determined in a manner known per se by measuring the length of the scanning line and used for correction in subsequent scanning lines. However, for the correction of the first scan line, it is only possible to use similar values from the previous scan line, so that the jump A to Sun height from the previous spatula P alternation in the same direction is The value from the last scan line of a segment is used to be able to predict the correction value for the first scan line of the next next segment.

In many use cases, the values of jumps A and B may actually be the same, so that predicting from one segment alternation to the next is sufficient. In known magnetic tape devices that perform segmented scanning,
During scanning, no signal can be extracted after the last scan line of each segment to determine the length of this scan line. Therefore, in an embodiment of the method of the invention, the velocity error of the previous scan line is used to determine the jumps A and B, as well as for the velocity error of the first scan line of the next segment. be done.

The method of the present invention will be explained in more detail below using numerical examples. It is assumed that a correction value is obtained for the first scanning line of segment 4. For this purpose, the value measured for the 51st scanning line of the preceding segment 3 is added to the quantity A, which is also used as a correction value in the 52nd scanning line. The quantity A is calculated from the difference between the values determined for the first scan line of segment 2 and the 52nd scan line of segment 1, the latter being equal to the length of the 51st scan line of the first segment. It is derived from

The apparatus of FIG. 10, which implements the functions of circuits 147 and 148 (FIG. 8), uses a D register 155 which is clocked by a horizontal pulse to substantially detect the velocity error determined by scan line length measurements. is supplied as a 9-bit wide digital signal. so that the value determined at the end of the 51st scan line can be used not only for correction during the 52nd scan line, but also for determining the jump A or day. At the beginning of the first scan line, no H pulse is provided to the clock input of D register 155.

The digital signal representing the correction value passes through an adder 156, which simply adds the value A each time in the first scan line.
or days will be added.

A limiter 157 is connected to the adder 156, and when an automatic flow or underflow occurs due to addition in the adder 156, a maximum or minimum value given by a 9-digit binary value is transferred to the limiter. I guarantee you that.

The limiter 157 is connected to the output 159 via a register 158 which is clocked by a horizontal pulse. A correction signal can be fed from the output side to a correction circuit known per se.

In addition, the output signal of the limiter 157 is
60. This register stores the correction value for the 52nd scan line of each segment until the formation of the next correction value obtained by measuring the length of the first scan line. The stored signal from register 160 is taken off in inverted form, so that in adder 161 the difference between the correction value of the respective first scan line of the segment and the last correction value of the preceding segment is formed. . This value A and the day are stored separately in registers 162 or 163 for the duration of two segments in each case and one
It is shifted by a segment and fed to the adder 156 at the beginning of the next next segment in each case.

Registers 162 and 163 are clocked by horizontal clock H. These output sides are each oC
Via the inputs, corresponding signals oC1 and OC2 control the adder 156 so that no signals are supplied from the registers 162 and 163 during the 2nd to 52nd scanning lines.

As already mentioned, one of the registers 162 to 163 is sufficient in this case, since under certain preconditions the signal jumps A and B may actually be equal.

[Brief explanation of drawings]

1a and 1b are block circuit diagrams of an embodiment of the video processor of the present invention, FIG. 2 is a block circuit diagram illustrating a portion of the circuit of FIG. 1 in detail, and FIG.
The figure is a voltage-hourly signal waveform diagram of a signal generated in the circuit of FIG. 2, and FIG. 4 is another voltage-hourly signal waveform diagram having a different time scale from that of FIG. Fifth
FIG. 6 is a block circuit diagram of a digital clock generator, FIG. 6 is a circuit diagram showing details of the digital clock generator, and FIG. 7 explains insertion and separation of 2H and 2V-ξ pulses. FIG. 8 is a detailed block circuit diagram of the circuit for determining the speed error, and FIG.
The figure is a diagram illustrating the time course of speed errors as an example, and FIG. 10 is a block circuit diagram showing the portion of FIG. 8 in detail. 16... Speed error detection circuit, 18... Dropout compensation circuit, 31... Image memory, 33.3 Raw...
・1 scanning line delay circuit, 35.42...addition circuit, 36
...Signal switch, 38.39...DA converter, 4
0...Rono ξ filter, 41...Equalization circuit, 4
3...No ζ P/ξ filter L -J -1 + J segment

Claims (1)

Claims: 1. A video signal processor in which a video signal retrieved from an information carrier is converted into a digital signal and stored in digital form, comprising: AD conversion and storage of the digital signal into a first temporary memory; A circuit for compensating for signal dropout points is connected to the output of the first temporary memory, to which a first clock signal is used for writing and a second clock signal is supplied for reading. said signal drop in the form in which a second temporary memory is connected to the output side of the circuit, in which the digital signal is written in by means of a second clock signal and in which the digital signal is read out by means of a third clock signal. A digital image memory (3) is further added to the circuit (18) for compensating for out points.
1) is connected and the digital image memory (31
) is characterized in that the output side of the image memory (31) is connected to a circuit (33, 34, 35, 36) for separately processing the color and luminance components of the signal retrieved from the image memory (31). Video signal processor. 2. The digital signal supplied to the image memory (31) is
AD conversion of video signals supplied as color television signals (■geschlossene Codier)
3. A video signal processor according to claim 1, which is derived by E. ung). 3. On the output side of the image memory, one scanning line delay circuit (33,
34), adder circuit (35) and signal switch (36)
are post-connected as follows, i.e. during the first field the luminance signal and the chrominance signal are taken from the digital signal belonging to one field and during the second field two consecutively following the same field. 3. A video signal processor according to claim 2, further connected downstream in such a way that the luminance signals of the scan lines are interpolated and the chrominance signals are extracted by repeating the chrominance signals of the same field. 4. The output signals of the signal switch (36) are each supplied to the DA converter (38, 39), and the output of the DA converter (39) provided for the color signal is supplied to the band pass filter (43). and a DA converter (38) which is supplied to one input side of the adder circuit (42) via the color subcarrier phase circuit (44) and is provided for the luminance signal.
The output of is passed through a low-pass filter (40) and an equalization circuit (
41) to the other input of said summing circuit (42), and the color subcarrier phase circuit (44) is controllable using a phase comparison between the color synchronization signal and the reference carrier. Claim 3 including a controllable phase shifter
The video signal processor described in Section 1. 5. Supplying said image memory (31) in a video signal processor, wherein the video signal retrieved from the information carrier is converted into a digital signal, which digital signal is written to the digital image memory after time error correction and signal loss compensation; containing information about the temporal relationship of the digital signal to a reference color television signal taking into account the sequence of color subcarriers defined by the field sequence and the respective color television system. An identification signal is added and a circuit for evaluating this information is provided after the image memory, which circuit causes a signal switch (36) provided after the image memory (31) to such that the signal read from the memory is aligned to the reference color television signal with respect to field columns and color subcarrier switching times;
A video signal processor characterized in that it controls. 6. A video signal processor in which the video signal retrieved from the information carrier is converted into a digital signal and stored in digital form, the video signal processor comprising: a first clock signal for AD conversion and writing the digital signal to a first temporary memory; a circuit for compensating for signal dropout locations is connected to the output of the first temporary memory, to which a second clock signal is applied for reading, and a digital signal is supplied at the output of the circuit. in which a second temporary memory is connected, in which the digital signal is written by a second clock signal and the digital signal is read by a third clock signal. The output signal of the circuit (16) supplied to the circuit (16) and for determining said speed error is supplied to a clock generator (14,
25) A video signal processor, characterized in that it is provided to control the frequencies of the first and third clock signals. 7. The first temporary memory is a write-read memory (RA
7. Video signal processor according to claim 6, characterized in that it is formed by a FIFO circuit (13) to which M) (17) is connected. 8. Prior to AD conversion, the color synchronization signal contained in the supplied video signal is derived by a limiter and filter circuit (5) that maintains the amplitude of the color synchronization signal constant. A video signal processor according to scope 6. 9. The video signal processor according to claim 8, wherein the alternating phase for each scanning line in the color synchronization signal corresponding to the PAL color television system is switched before AD conversion. 10. A first clock generator (14) for controlling the phase of the first clock signal from the first value according to a predetermined function inserted into the video signal before AD conversion. 7. A video signal processor as claimed in claim 6, wherein a control signal is provided which is derived by sampling the signal transitioning to a second value. 11. A signal transitioning from a first value to a second value according to a predetermined function is coupled to a horizontal synchronization pulse delivered from a pulse generation circuit, and the pulse generation circuit It includes a switch (59), a demodulator (60), and a pulse separation circuit (61), and video signals can be supplied from two magnetic heads to the input side (57, 58) of the channel switch (59). 11. A video signal processor according to claim 10, wherein the channel switch (59) is switched during a scan line sweep period. 12, first and second clock generators (14, 25)
In addition, a high-precision clock signal (C2) can be supplied, and the phase and frequency deviation of the generated clock signals (C1, C3) with respect to the supplied high-precision clock signal is determined by the supplied digital signal. 7. A video signal processor as claimed in claim 6, which is thus controllable. 13. The output side (102) of the digital adder (101) is connected to the digital adder (10) via the register (105).
1) and further connected to a second input (104) of said digital adder (101).
a short period of time, triggered by a horizontal sync pulse.
Video signal processor, characterized in that at least one digital clock generator (14, 25) is used, which can supply a value of and another value for the remaining scan line period. 14, another register (107, 111) is connected to the second input side (
104) and is connected in advance by means of said register to said second input (104) in each case as a function of the horizontal synchronization pulse.
04) on the input side for the first value (
14. Video signal processor according to claim 13, wherein a plurality of low value digits are connectable to the input (109) for the second value. 15, digital adder (101) and register (10
15. The video signal processor of claim 14, wherein 5) is configured for 20 binary digits. 16. Clock input side (106) of register (105)
is supplied with a clock signal whose frequency is constant and is in the frequency range of the clock signal to be generated;
by corresponding selection of the value range of said register (10
The frequency of the output signal of 5) is a part of the frequency of the supplied clock signal, and a frequency multiplier (
116) is connected to the video signal processor according to claim 13. 17. The video signal processor according to claim 16, wherein a circuit (114) for forming a sine wave vibration is provided between the register (105) and the DA converter (115). 18. The frequency multiplier (116) comprises a plurality of frequency multipliers each including an analog multiplier (121) and a filter (122, 123, 124) set to the output frequency. The video signal processor described in Section 1.