GB2181015A

GB2181015A - Video signal processor

Info

Publication number: GB2181015A
Application number: GB08622623A
Authority: GB
Inventors: Jurgen Heitmann
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1985-09-21
Filing date: 1986-09-19
Publication date: 1987-04-08
Also published as: FR2587868B1; FR2587868A1; DE3533703A1; GB8622623D0; DE3533703C2; GB2181015B; JPS6268379A

Abstract

Video signal processor comprising an analog/digital converter 2 for converting a video signal from an information carrier into digital form under the control of a first clock signal C1, a first temporary store 13 for storing the digital signal under the control of the said first clock signal, a circuit 18 for compensating signal errors connected to the output of the first temporary store, and a second temporary store 27 into which the digital signal from the signal error compensating circuit 18 is written under the control of a second clock signal C2 and from which the digital signal is read under the control of a third clock signal from a clock generator 25, wherein a digital image store 31 is connected to the signal error compensating circuit 18 and wherein the output of digital image store 31 is connected to a circuit (Fig. 1b) for separately processing the luminance and chrominance signals of the digital signal taken from the image store. <IMAGE>

Description

SPECIFICATION Video signal processor This invention relates to a video signal processor.

In the reproduction of video signals from an information carrier such as a magnetic tape, particularly colour television signals, various errors appear in the signals which have to be compensated to obtain optimum reproduction. These are mainly time and velocity errors, as well as drop-outs, which are caused by blemishes on the information carrier.

It is also known to store in an image store the signals of an image reproduced in sections from a magnetic tape, from which they can then be repeatedly read out for reproducing a still picture.

Various arrangements are known for attaining the above requirements, and these either operate in analog or digital manner.

A known process for compensating time errors in a colour television signal taken from an information carrier, in which the colour television signal is converted into digital form and stored, comprises producing a first clock signal whose phase position is controlled by the horizontal frequency sync pulses contained in the colour television signal and whose frequency is controlled by a first control voltage, the first clock signal being used for analog/digital conversion and for writing the digital signal into a first temporary store.The digital signal is read out from the first temporary store with a second clock signal whose frequency is an integral multiple of a horizontal frequency reference signal, the deviation of a line period of the digital signal read out from the first temporary store from the line period of the reference signal being measured for deriving the first control voltage. The horizontal frequency pulses of the reference signal are compared with the horizontal frequency pulses of the signal read out from the first temporary store with respect to the phase position, and as a function of the phase difference the writing in and reading out of the digital signal into or out of the first temporary store is controlled in such a way that the time between writing in and reading out corresponds to the phase difference.The signal read out from the first temporary store is written into a second temporary store, and the digital signal is read out of the second temporary store with a third clock signal which is obtained by a controllable phase shift from the second clock signal. A phase comparison takes place between the colour sync signal of the signal read out from the second temporary store and a reference colour sync signal and the result of the phase comparison is stored for in each case one line period for obtaining a second control voltage which is used for the phase shift of the second clock signal (see DE-Al-30 26 473).

This known process for compensating time errors can be followed by an image store for still or slow motion reproduction.

The problem of the present invention is to improve the known process in such a way that the aforementioned errors are compensated in an optimum manner.

According to the present invention there is provided a video signal processor comprising an analog/digital converter for converting a video signal from an information carrier into digital form under the control of a first clock signal, a first temporary store for storing the digital signal under the control of the said first clock signal, a circuit for compensating signal errors connected to the output of the first temporary store, and second temporary store into which the digital signal from the signal error compensating circuit is written under the control of the said second clock signal and from which the digital signal is read under the control of a third clock signal, wherein a digital image store is connected to the signal error compensating circuit and wherein the output of digital image store is connected to a circuit for separately processing the luminance and chrominance signals of the digital signal taken from the image store.

A video signal processor according to the invention is characterised in that to the circuit for compensating signal errors is also connected a digital image store and that the output of the latter is connected to a circuit for the separate processing of the chrominance and luminance component of the digital signal taken from the image store.

An important improvement is obtained in that the digital signal is supplied to a ci rcuit for determining velocity errors and that the output signal of the circuit for determing velocity errors are supplied to a first and a second clock generator provided for generating a first and a third clock signal for controlling the frequency of the first and the third clock signal.

The measures given in the subclaims permit advantageous further developments and improvements to the video signal processor according to the invention.

An embodiment of the invention is described in greater detail hereinafter with reference to the accompanying drawings, wherein: Figure lisa block circuit diagram of the embodiment; Figure 2 is a detail of part of the arrangement of Figure 1; Figure 3 are voltage-time diagrams of signals occurring in the arrangement of Figure 2; Figure 4 are further voltage-time diagrams with a modified time scale compared with Figure 3; Figure 5 is a block circuit diagram of a digital clock generator; Figure 6 is a detail of the digital clock generator; Figure 7 is a diagrammatic representation of the keying in and separation of 2H and 2V pulses; Figured is a block circuit diagram of a circuit for determining velocity errors; Figure 9 is a diagram showing diagrammatically the time behaviour of the velocity errors; and Figure 10 is a more detailed block circuit diagram of part of Figure 8.

In the various figures of the drawings the same components are given the same reference numerals.

A colour television signal (CCVS) supplied at input 1 to the video signal processor of Figure 1 is assumed to be the output signal of a video tape recorder and, inter alia, has velocity and time errors, as well as drop-outs. It is the function of the video signal processor shown in Figure 1 to compensate or correct these errors. The video signal processor also contains an image store, in order to permit a reproduction with a velocity differing from that used during recording. This is particularly important in magnetic tape recorders in which the information content of each field is recorded over several tracks of the tape. Most of the signal processing takes place with digital circuits and for this purpose the colour television signal supplied at 1 is converted into digital form by an analog/digital converter 2.

However, before the colour television signal reaches the analog/digital converter 2, it is processed in the manner now to be described, in order to provide more favourable conditions for the subsequent processing.

Firstly, the signal is adjusted as regards gain and setup interval with the aid of a known circuit 3. In a circuit 4 described in greater detail in conjunction with Figure 2, a given function, hereinafter called a ramp, is inserted in the vicinity of the horizontal frequency sync pulse of the colour television signal.

This function is subsequently used for the accurate determination ofthe relative phase position ofthe colour television signal to the clock signal C1 to be described. Then, at 5, there is effected in known manner a phase resetting of the colour sync signal whose phase position is switched over every other line in accordance with the PAL colour television process. This phase resetting, which negates the usual line-by-line phase switching facilitates the subsequent evaluation of the colour sync signal for determining velocity errors. Finally, the colour television signals CCVS pass via a low-pass filter 6 for preventing alias disturbances.

In order to avoid visible quantization disturbances, quantization in the analog/digital converter 2 takes place to an accuracy of 9 bits. A first clock signal C1 is supplied to the analog/digital converter 2 and is locked to the colour television signal CCVS supplied at 1, having a frequency of approximately 13.5 MHzwhich is roughly three times the PAL chrominance carrier frequency.

The video signal processor shown in Figure 1 takes account of a special feature of magnetic tape recorders in which the information content of each field is recorded over several tracks at an angle to the longitudinal direction of the tape, so-called segmented scanning. In the case of tape recorders with segmented scanning, during each field switching takes place on a number of occasions from one magnetic head to another. Each switchover normally occurs within a respective horizontal frequency blanking interval, and as a result the horizontal frequency sync pulse is lost at that point. The colour television signal supplied at 1 consequently has a disturbed horizontal sync pulse before the first line of successive line groups (i.e. at each switch over point).This does not constitute a problem for subsequent reproduction of the signal on a monitor or for emission by means of a radio transmitter, because subsequently new sync pulses are added to the colour television signal. However, for determining the time errors, it is necessary to evaluate the existing horizontal frequency sync pulses. Thus, in the known recording and reproduction equipment, it is usual to extrapolate the sync pulse for the first line of a group from the sync pulses of the following lines of the group.

However, by means of respective inputs 57 and 58, the video signal processor of Figure 1 is directly supplied from the tape recorder with the carrier frequency output signals of the two magnetic heads following amplification and frequency response correction. A channel switcher 59 connected to inputs 57, 58 is controlled in such a way that the switching over in each case takes place within the line period before the horizontal frequency sync pulse at which the signal supplied at 1 is switched over. Thus the sync pulses which are disturbed at the input 1 are obtained undisturbed at the output of 59. The output signals of the channel switcher 59 are demodulated at 60 and supplied to a pulse clipping circuit 61. The latter is known per se and separates the signals H, V, 2H and 2V from the video signal supplied.Signal H is used in circuit 4 for forming the ramp signal previously mentioned. The elements 57 to 61 are intended to be diagrammatic only, and the complete circuit represented thereby is described in our copending patent application (P/1155).

The output signal of the analog/digital converter 2 is supplied to the inputs of a ramp evaluation circuit 12 and a FIFO circuit 13. The ramp evaluaton circuit 12 is illustrated in greater detail in Figure 2, and produces a digital control signal which gives the deviation from a given phase relationship between the first clock signal C1 and the horizontal frequency sync pulses of the colour television signal. This control signal is used for controlling the phase position of the clock signal C1 from the first clock signal generator 14. The clock signal Cl, which is consequently variable with respect to its phase position is on the one hand supplied to the analog/ digital converter 2 as a sampling clock signal and on the other hand via a logic circuit 15 to a FIFO circuit 13 as a writing-in clock signal.By means of the control loop formed by circuits 2, 4, 12 and 14 a very accurate phase relationship is obtained between the colour television signal and the first clock signal Cl.

A second clock signal C2 generated by a crystal oscillator (not shown) is supplied to the first clock signal generator 14. The circuit of clock signal generator 14, illustrated in greater detail in Figure 5, ensures that the first clock signal C1 has as good a frequency stability as the supplied second clock signal C2, although it is variable with respect to signal C2 in respect of phase position and frequency.

It is necessary to control the frequency of the first clock signal C1 for compensating velocity errors and for this purpose circuit 14 is supplied with a digital control signal from a circuit 16 for determining the velocity errors. Circuit 16 is further illustrated in Figure 6. Clock signal C1 is supplied from the first clock signal generator 14 via a logic circuit 15to FIFO circuit 13 and consequently controls the writing-in to the FIFO circuit 13. In known manner in connection with time error compensators, address signal for controlling a random access memory (RAM) 17 are produced in logic circuit 15. RAM 17 has a capacity of about two lines, so that time errors of up to roughly one line can be compensated by corresponding addressing.A digital signal is then available at the output of RAM 17 in which the time and velocity errors are compensated to a first approximation.

The digital signals are then supplied to a circuit 18 for compensating drop-outs. Suitable circuits are known in the art and need not be described in further detail in connection with the present invention. A particularly suitable circuit for this purpose is described in our copending patent application (P/1154).

The circuit 18 for compensating drop-outs is followed by a circuit 11, in which signals for identifying the switching phase of the chrominance carrier and the first or second field of each frame are inserted in the digital signal. The identification of the switching phase is necessary for subsequent processing, because the colour sync signal reset by means of circuit 5 no longer contains this information. The identification of a field is required for a correct line interpolation on reading out the colour television signal from the image store as will be described.

As high precision is required for the phase position of the chrominance signals in colour television systems with quadrature modulation, in known time error compensators there is connected to the first stage a further stage, also known as a precision time error compensator. The time position of the colour television signal is displaced in such a way that the colour sync signals coincide as accurately as possible with a reference chrominance carrier supplied.

In the video signal processor shown in Figure 1, this problem is solved by the circuit components described hereinafter, which also correct any remaining velocity errors.

For this purpose, the digital signal is supplied across a digital/analog converter 19 to a phase comparison circuit 20, where the phase position of the colour sync signal is compared with a reference chrominance carrier. The output voltage of the phase comparison circuit 20 is supplied across an analog/digital converter 21 to an input for controlling the phase position of the clock signal C3 generated by a second digital clock signal generator 25.

Following a circuit (not shown) for compensating the transit time ofthe circuits 19, 20 and 21, the digital signal passes into a FIFO circuit 27, into which they are read under the control of the highly stable clock signal C2. Reading out from the FIFO circuit 27 takes place under the control of the clock signal C3 supplied from the digital clock generator 25 and whose phase deviation relative to clock signal C2 corresponds to the time errors still to be corrected. The digital signal read out in this way from the FIFO circuit 27 then passes into a digitai/ analog converter 28, from whose output the video signal is fed to a low-pass filter 49, which is used for suppressing clock disturbances still present in the signal.The latter is connected to a blanking circuit 59 for renewing the blanking and for this purpose a blanking signal A is supplied to circuit 59. A biack burst supplied at 55 is introduced into the signal at an adding network 50, and then the colour television signal passes to switches 47,48 to output amplifiers 51,52 According to the switch settings, the corrected colour television signal is available for further use at one or both of the outputs 53, 54 of the output amplifiers 51, 52.

The output signal of circuit 18 for compensating drop-outs is written into an image store 31 for reproducing the colourtelevison signal with a velocity differing from that at recording, i.e. still, slow motion or time lapse. For reducing technical costs, the digital signal is written into the image store 31 with only a bit width of 8. Such image stores are described in the literature in connection with the aforementioned reproduction type, particularly in connection with magnetic tape recorders with segmented scanning and need not be described in greater detail in the present application. The digital colour television signal read out from the image store 31 is supplied across two single-line period delay circuits 33,34 and an adding network 35 to a signal switch 36 which supplies separate luminance and chrominance signals.

To avoid flickering, signal switch 36 passes on the signals in such a way that during the first of each pair of successive field periods (two field periods equal one frame period) the luminance and chrominance signals are derived from the digital signal corresponding to one actual field of stored information, whereas during the second field period the luminance signal of each line is formed by interpolation of two successive lines of the first actual field and the chrominance signal is obtained by repeating the chrominance signal of the first field. A circuit for doing this is described in DE-C2-26 40 759. By means of an evaluation circuit 37, the information added by circuit 11 is evaluated to identify the particular field (first or second) and the switching phase of the chrominance carrier.The field information is supplied to signal switch 36 for control purposes.

The digital signals at the outputs of signal switch 36 for forming the luminance and chrominance signals Y and C are in each case supplied to a respective digital/analog converter 38, 39. The analog luminance signal is obtained from the digital to analog converter 38, and passes through a lowpass filter 40 with a cut-off frequency of 3 MHz to a deemphasis circuit 41, and thence to an adding network 42. Deemphasis circuit 41 is used for increasing the edge sharpness and can e.g. be a deemphasis circuit connected in known manner.

The analog chrominance signal from the digital/ analog converter 39 passes across a band-pass filter 43 to a circuit 44, which switches back the poiarity of the colour difference signal U inverted as a function of the operating state on reading the digital signals from image store 31 and carries out a phase regulation of the chromaticity signal for adapting to the phase of a reference chrominance carrier. Thus, a 90" error is eliminated which would occur without phase regulation through the repeating of a field from image store 31. In addition, it eliminates residual time errors. A suitable circuit is described in patent application P 35 17 697.0 filed by the present Applicant and entitled "Rapidly controllable phase shifter".

The output signal of adding network 42 is blanked in accordance with the desired standard in a blanking circuit 45 and in a further adding network 46 is provided with black bursts. Switches 47,48 make it possible for outputs 53, 54 to supply independently of one another either one or both of the colour television signal read out from the image stores 31, or the colour television signal fed to the output circuit from 59.

A precise locking of the clock signal C1 to the digital video signal is necessary for the video signal processor according to the embodiment. A circuit for obtaining such a locking is described in greater detail relative to Figures 2 to 4 and is also described in our copending patent application (P/1149). Figure 2 shows circuits 2,4, 12 and 14 of the arrangement according to Figure 1. The signal produced by pulse shaper 63 is keyed into the analog video signal from circuit 3 by means of a switch 65.

In response to each sync pulse from 61 a pulse shaper 63, which is advantageously implemented by a phase-linear low-pass filter, shapes a signal R represented in the second line of Figure 3. The essential part of signal R is a gradually rising fiank (ramp), which starts at the lower operating limit of the analog/digital converter 2 and rises symmetrically to 50% of the operating limit and whose rise time is between 1 and 2 periods of the clock signal Cl. The ramp is followed by a constant amplitude portion corresponding to the 50% level.

Forthe purpose of controlling switch 65, the square-wave pulse D shown in the bottom line of Figure 3 is derived from a horizontal frequency sync pulse supplied from 61 (Figure 1) with the aid of pulse shaper 64. In known manner, pulse shaper 64 contains a monostable switching stage. Thus when D is low the signal R is passed to the A/D converter 2, whereas when it is high the FBAS signal shown at the top of Figure 3 is passed to the converter 2. The resultant signal passed from the switch 65 to the A/D converter 2 is shown at B in the third line of Figure 3 (the reason for the oscillations in B will be described later).

The analog/digital converter 2 is supplied with the clock signal C1. From the output of analog/digital converter 2, the digital colourtelevision signal is passed for further processing with a precision of 9 binary digits.

The digital colour television signal is also supplied with a precision of 9 binary digits (bit width of 9) to a register 68. The latter is also clocked with the signal C1 and is also controlled by the pulse D produced by pulse shaper 64.

Line E of Figure 4 shows to a larger time scale than Figure 3 the ramp portion of R taken from the digital colour television signal at the output of converter 2, and it is shown as an analog signal to make it easier to understand. There are several pulses of clock signal C1 during the pulse D. During the pulse D the sampled values from converter 2 are fed via the register 68 to a further register 70 and to a window comparator 71, whose output controls register 70. The known window comparator supplies at its output a signal if the value of the input signal supplied from register 68 is between two values fed in at 72 and 73, e.g. 10% and 90% of the total amplitude of signal R.

Before the start of the ramp, the sampled values in register 68 are very small, so that register 70 is not released by window comparator 71. The first value exceeding 10% of the total amplitude of signal R is written into the register 70. If subsequently there is a sample value below 90%, it replaces the value previously written into register 70. Since, as will be described hereinafter, the sampled value is used for regulating the phase position of the clock during normal operation, i.e. without any effect of special disturbance variables, such a phase position will be obtained that the signal R is sampled in the vicinity of point M.

By means of a programmable read-only memory (PROM) 75, in which is stored the shape of the ramp of signal R, the difference in time between the position of the sampled value from the centre M of the ramp is determined. This value is read out of PROM 75 and used for controlling the phase position of the clock signal C1.

In the correction of time and velocity errors, there is an evaluation of the colour syne signal in the case of a colour television signal. This can be provided for in that the colour sync signal can be superimposed on the constant amplitude portion of the signal R beyond the initial ramp, as indicated in the third line of Figure 3.

Clock generators 14, 25 (Figure 1) must fulfil the following requirements. Both the phase position at the start of the line and the frequency must be controllable by control signals supplied from the outside. In much the same way as a colour carrier, the stability of the frequency must be in the range 10-6.

The phase and frequency must follow changes in the control signals in a substantially inertialess manner.

These requirements cannot easily be fulfilled with conventional oscillators, such as crystal and startstop oscillators. Therefore the digital clock generator shown in Figures 5 and 6 is used. In the arrangement according to Figure 5, 101 is a 20 position adder with an output 102 and first and second inputs 103, 104. The 20 binary positions of output 102 are connected to the inputs of a 20x register 105, whose outputs are again connected to the first input 103 of adder 101. Register 105 is controlled with the clock signal C2 supplied at 106.

For each clock pulse supplied at 106, there is a circulation of the digital signals, the value supplied to the input 104 of adder 101 being added thereto in each case. When the adder has reached its maximum capacity, it is necessary to start from zero again.

The 8 low-value positions of input 104 are connected across a register 107 to a first 8 position input 109. Asecond 8 position input 110 is connected across a further register 111 to the 8 higher-value positions of input 104. The four intermediate positions of input 104 receive zeros, which is indicated by an earth symbol in the drawing. Furthermore the position of the input 104 with the second highest valency can be supplied with a one via register 107. Clock signal C2 is supplied across input 106 to the clock inputs of registers 107,111. In addition, the registers can be alternately blocked by a horizontal frequency sync pulse supplied to input 112, for which purpose the sync pulse is supplied to register 107 across an inverter 113.The alternating blocking of registers 107, 111 with the aid of the sync pulse supplied at 112 means that on the one hand the 8 higher-value positions of input 104 are temporarily set at the values of the signal supplied at 110 and on the other hand a one is applied to the second highest position and to the lower-value positions of input 104 is applied the signal supplied at 109, the remaining positions being set to zero.

Through the repeated addition of the one in the second highest position and the value supplied at 109, there is a time-linear rising value of the output signal of adder 101 or register 105. On reaching the capacity of adder 101, the value jumps back to zero and then rises again in time-linear manner. The frequency is substantially determined by the ones in the second highest position. By means of the value supplied at 109, the gradient of the rise and therefore the frequency of the output signals of register 105 can be controlled extremely sensitively.

If briefly during the sync pulse, the value supplied across input 110 is fed to the 8 higher-value positions of input 104, the time-linear rising portion of the sawtooth voltage is set to an initial value from which the rise is continued. Thus, with the value of the signals supplied at 110, it is possible to set the phase position between the starting signals of register 105 and the sync pulse supplied at 112. The frequency at the output of register 105 roughly corresponds to quarter of the frequency of the clock signal C2 supplied at 106.

In order to simplify the subsequently occurring frequency multiplication, the sawtooth or ramp function is converted into a sine function in a programmable read-only memory (PROM) 114. For this purpose, the image of ramp function is placed on the sine function in the PROM, so that on inputting the output signals of register 105 into the PROM addressing inputs, signals are obtained at the data outputs which embody a sine function.

For deriving the clock signal to be produced from the output signals of register 105, the high precision which is required for carrying out the accumulation process with the aid of adder 101 of register 105 is not needed. Thus, only the 10 higher-value positions of the output signal of register 105 are supplied to PROM 114. The output signals of the PROM 110 also only have a width of 10 bits and are therefore passed via a register 118 to a digital/analog converter 115, whose output is connected to a frequency multiplier 116. The clock signals at the output 117 of frequency multiplier 116 can undergo frequency modification in the range of the frequency of clock signal C2 supplied at 106. A phase displacement by several clock periods is also possible. In the case of the circuit used as the digital clock generator 14 (Figure 1), the frequency can be changed in extremely small steps.Thus, e.g. the change to the LSB at input 109 corresponds to a change of the phase position with respect to the horizontal frequency sync pulses of 0.48 ns per line.

Adder 101, registers 105,107 and 111, as well as circuit 114 can easily be implemented by conventional digital components. Due to the relatively high frequencies, series F(=fast) TTL components were used in a practical embodiment.

The register was formed from type F 374 components, several registers being connected in parallel due to the high bit width. Adder 101 was produced using five type F 283 components. Circuit 114 can be realised with a PROM of type TBP 24541 and a PROM of type TBP 28 586. Finally, a suitable digital/analog converter can be obtained the type designation TDC 1016.

Even though the construction of a frequency multiplier offers no difficulties to the expert, the construction of a simple frequency doubler will be explained by means of the circuit diagrammatically shown in Figure 6. Two such frequency doublers are connected in series in circuit 116 (Figure 5). The sine-wave signal supplied by the digital/analog converter 115 (Figure 1) is supplied across switching point 120 to the two inputs of a multiplier 121. Thus, at the output of multiplier 121 there is a signal comprising a sine-wave oscillation with double frequency and a d.c. voltage component. The latter could be removed by simple RC coupling. However, in the represented circuit a band-pass filter 22, 23, 24 is provided which, a part from the d.c. voltage component, also removes any harmonics due to nonlinearities of multiplier 121.A sine-wave oscillation with double the frequency is then available at output 125. Other circuits, e.g. PLL circuits could also be used as frequency multipliers.

Figure 7 diagrammatically shows the keying in and separation of 2H and 2V pulses, as occur in circuits 11 and 37 (Figure 1). Switches 131, 132 controlled by a pulse shaper 133, are introduced into two of the nine parallel data lines. The pulse shaper is timed by a horizontal frequency pulse H and supplies a 500 no wide pulse to switches 131,132.

The 2H and 2V pulses supplied by circuit 61 (Figure 1) are keyed in during this time. During the remainder of the line period switches 131, 132 are in the upper position and consequently also switch through the lines for the seventh and eighth bits. In circuit 37, the lines for the seventh and eighth bits are connnectd to the inputs of a double D-register 134, which is timed with pulse H. Pulses 2H and 2V are then available at the outputs of the D-register.

Figure 8 shows in greater detail circuit 16 (Figure 1) for determining the velocity errors, such circuit also being described in our copending patent application (P1150). Circuits 2,12, 13 and 14 and their interaction has already been described in conjunction with Figure 1.

Circuit 136, to which the digital colour television signal is also supplied, constitutes a selection circuit by means of which selected sample values are formed during the colour sync signal.

For converting the sample values into a phase value, the output signals of circuit 136 are supplied to a circuit 137 for forming an inverse sine. Circuit 137 essentially comprises a programmable readonly memory (PROM), into which has been written a corresponding function table.

However, prior to forming the inverse sine, the sampled values ofthe digital signal during the coloursyncsignal are checked in circuit 136 asto whether they are located in a range in which the sine function is sufficiently steep to give adequately precise information on the phase position from the particular sample value. This is the case in roughly half the amplitude range of the colour sync signal, i.e. in the phase positions in which the sine is between -0.5 and +0.5. Only those sample values having the necessary amplitude are used.

As statistical interference can be superimposed on the colour sync signal, leading to a disturbance of the phase measurement, a means value of four measurements within a colour sync signal is formed in a circuit 138.

Since, as a result of the phase regulation by the circuit 12, the clock signal C1 can have a phase jump at the beginning of each line, the phase control signal value corresponding to this phase jump is subtracted in a subtracting network 139 from the output signal of circuit 138. From the signals now characterising the absolute phase position of the colour sync signals, difference values are determined by means of a D-register 140, to which is supplied a clock signal H, and a subtracting network 141, which difference values characterise the length of each line. According to the commutating law rules, it is also possible to choose a different sequence of the subtractions.

By means of a programmable read-only memory 142, these difference values are compared with desired values for the line length, which as phase angles ofthe colour carrier are stored in PROM 142.

Thus, at the output of circuit 142, there is a velocity error value, but this is related to the frequency of the clock signal Cl, which is in turn dependent on the frequency control signal supplied to the clock generator 14. Thus, for obtaining an absolute value of the velocity error, the frequency control signal is added thereto in an adder 143. The resulting signal can be supplied via a D-register 144 to clock generator 14 as a frequency control signal for the following line. Alternatively, there can be an averaging of the velocity error signals over several lines, which is indicated in the drawing by register 145 and adding network 146.

In the case of tape recorders with segmented scanning, in some cases a separate derivation of a correction signal for the in each case first line of a segment is necessary. Such a circuit, which is also described in our copending patent application (P/ 1152), is indicated at 147 and is explained in greater detail relative to Figures 9 and 10. With the aid of switch 148, which is controlled by means of a control circuit 149 from the head switching pulse K, the output signals of circuit 147 are keyed into the correcting signals for the further lines.

The diagram shown in Figure 9 gives velocity errors as a function of time, as can occur in the signals supplied to the video processor according to Figure 1. The curve represents the magnitude of the velocity errors during the scanning of four consecutive segments 1, 2, 3 and 4. At the start of each segment there is a jump A or B, whereas there is little change to the velocity errors within each 52line segment. Segments 1 and 3 are reproduced by a first magnetic head and segments 2 and 4 by a second magnetic head.

It has been found that the jumps A and B of the velocity error remain substantially constant on passing from one head to the other. The overall level of the velocity errors is, however, subject inter alia to statistical fluctuations.

In the process used, it is assumed that within a segment the velocity error is determined in known manner by measuring the length of a line and can be used for correction purposes in the following line.

However, for the correction of the first line of a segment, since no similarvalue is available from a preceding line, the level of the jump A or B from the preceding head change is used, so that with the aid of the value for the final line of a given segment a conclusion can be drawn regarding the correction value for the first line of the next but one segment.

In many applications the amplitude of jumps A and B are substantially the same, so that it is sufficient to draw conclusions concerning the second segment change on the basis of the first.

In some known magnetic tape recorders with segmented scanning, during reproduction after the final line of each segment, no signal is available for determining the length ofthis line. Thus, according to a further development, the velocity error of the penultimate line is used for determining jumps A and B, as well as forthe velocity error of the first line of the following segment The process is explained in greater detail hereinafter relative to a numerical example. A correcting value is to be determined for the first line of segment 4 and for this purpose the measured value for the fifty-first line of the preceding segment 3, also used as a correcting value in the fifty-second line, is added to quantity A.Quantity A is calculated from the difference of the values calculated for the first line of segment 2 and the fifty-second line of segment 1, the latter being derived from the length of the fifty-first line of the first segment.

The arrangement according to Figure 10, which fulfils the function of circuits 147,148 (Figure 8) is supplied with the velocity errors essentially determined by the measurement of the line length in the form of 9 bit wide digital signals by means of a D-register 155 clocked with horizontal frequency pulses H. In order that the value determined at the end of the fifty-first line can not only be used for correction during the fifty-second line, but also for determining jumps A and B, the H-pulse at the beginning of the first line of each segment is not supplied to the clock input of D-register 155.

The digital signals representing the correcting values pass through an adder 156, to which the values A or B are only added in the first line of each segment. To adder 156 there is connected a limiter 157, which ensures that the maximum or minimum value given by the 9-position binary number is passed on if there should be an underflow or overflow through the addition in adder 156.

By means of a register 158, which is clocked with the horizontal frequency pulses H, the correcting signals from the limiter 156 are supplied to output 159.

The output signals of limiter 157 are also supplied to a further register 160, which stores the correcting value for the fifty-second line of each segment until the correcting value obtained by measuring the length of the first line of the next segment is available. The stored signals are removed in inverted form from register 160, so that in an adder 161 there is formed the difference A or B of the correcting values of in each case the first line of a segment and the last line of the preceding segment.

These values A and B are separately stored in registers 162,163 for the duration of two segments and are alternately supplied to the adder 156 at the start of the next but one segment.

Registers 162 and 163 are clocked with the horizontal frequency pulses H. Their outputs are controlled by means of an OC-inputwith corresponding signals OC1, OC2 in such a way that during the second to fifty-second line no signal is supplied from registers 162, 163 to adder 156.

As stated hereinbefore, under certain conditions, the amplitude of signal jumps A and B can be substantially identical and in this case it is only necessary to have one of the registers 162 or 163.

Claims

1. Video signal processor comprising an analog/ digital converter for converting a video signal from an information carrier into digital form under the control of a first clock signal, a first temporary store for storing the digital signal under the controi of the said first clock signal, a circuit for compensating signal errors connected to the output of the first temporary store, and second temporary store into which the digital signal from the signal error compensating circuit is written under the control of the said second clock signal and from which the digital signal is read under the control of a third clock signal, wherein a digital image store is connected to the signal error compensating circuit and wherein the output of digital image store is connected to a circuit for separately processing the luminance and chrominance signals of the digital signal taken from the image store.

2. Video signal processor according to Claim 1, wherein the video signal is a colour television signal.

3. Video signal processor according to Claim 2, wherein the output of the digital image store is connected to two single-line delay circuits, an adding network and a signal switch in such a way that during the first of each two successive field periods the luminance signal and chrominance signal are derived from the digital signal corresponding to one field of stored information and that during the second field period the luminance signal of each line is formed by interpolation of two successive lines of the said one field and the chrominance signal is obtained by repeating the chrominance signal of the said one field.

4. Video signal processor according to Claim 3, wherein the output signals of the signal switch are in each case supplied to a respective digital/analog converter, the output of the digital/analog converter provided for the chrominance signal is supplied via a band-pass filter and a chrominance carrier phase circuit to one input of an adding network, the output of the digital/analog converter provided for the luminance signal is supplied across a low-pass filter and a deemphasis circuit to the other input of the adding network, and the chrominance carrier phase circuit contains a phase shifter which is controllable by a phase comparison between the colour sync signal and a reference carrier.

5. Video signal processor in which a colour television signal taken from an information carrier is converted into digital form and which, following time error correction and drop-out compensation, is written into a digital image store, wherein an identification signal is added to the digital signal supplied to the image store, such identification signal giving information on the relationship of the digital signal to the colour television signal with regard to the field sequence and the switching phase of the chrominance carrier, and wherein following the image store a circuit is provided for evaluating this information and controlling the readout from the image store in such a way that the digital signal read out of the store is correct with respect to the field sequence and the chrominance carrier switching phase.

6. Video signal processor comprising an analog/ digital converter for converting a video signal taken from an information carrier into digital form under the control of a first clock signal, a first temporary store for storing the digital signal under the control of the said first clock signal, a circuit for compensating signal errors connected to the output of the first temporary store and to whose output is connected a second temporary store into which the digital signal is written under the control of the said second clock signal and from which the digital signal is read under the control of a third clock signal, wherein the digital signal is supplied to a circuit for determining velocity errors and wherein the output of the latter circuit is fed to clock signal generators for generating the first and third clock signals, for controlling the frequency of the first and third clock signals.

7. Video signal processor according to Claim 6, wherein the first temporary store is formed by a FIFO circuit with a connected random-access memory.

8. Video signal processor according to Claim 6, wherein prior to analog/digital conversion, a colour sync signal contained in the video signal is passed through a limiting and filtering circuitwhich maintains the amplitude of the coloursyncsignal constant.

9. Video signal processor according to Claim 8, wherein the phase switching of the colour sync signal on a line-by-line basis in accordance with the PAL technique is negated prior to analog/digital conversion.

10. Video signal process according to Claim 6, wherein a control signal is supplied to the first clock signal generator for controlling the phase position of the first clock signal, such control signal being derived by sampling a signal inserted in the video signal prior to analog/digital conversion and which according to a given function passes from a first value to a second value.

11. Video signal process according to Claim 10, wherein the signal passing according to a given function from a first to a second value is locked to a horizontal frequency sync pulse which is supplied by a pulse generating circuit, wherein the pulse generating circuit contains a channel switcher, a demodulator and a pulse clipping circuit and wherein the inputs of the channel switcher can be supplied with video signals from two magnetic heads and is switched over during a line period.

12. Video signal processor according to Claim 6, wherein a highly stable clock signal is supplied to the first and third clock signal generator and that compared with the highly stable clock signal the phase position and frequency of the generated first and third clock signals can be controlled with the digital signal.

13. Video signal processor comprising at least one digital clock generator in which the output of a digital adder is connected via a register to a first input of the digital adder and in which to a second input of the digital adder in response to a horizontal frequency sync pulse, a first value is temporarily supplied, a further value being supplied to the second input during the remaining line period.

14. Video signal processor according to Claim 13, wherein further registers are connected upstream of the second input and to which, as a function of the horizontal frequency sync pulse, can be connected several higher-value positions of the second input with an input for the first value or several lowervalue positions with an input for the second value.

15. Video signal processor according to Claim 14, wherein the digital adder and register are designed for 20 binary positions.

16. Video signal processor according to Claim 13, wherein a clock signal is supplied to the clock input of the register and the frequency thereof is constant, being in the range of the frequency of the clock signal to be generated, that by a corresponding choice of the range of the further value the frequency of the output signal of the register is a fraction of the frequency of the supplied clock signal and that a frequency multiplier is connected to the output of the register across a digital/analog converter.

17. Video signal processor according to Claim 16, wherein a circuitforforming a sine-wave oscillation is positioned between the register and the digital/ analog converter.

18. Video signal processor according to Claim 17, wherein the frequency multiplier comprises several frequency doublers, which in each case contain an analog multiplier and a filter tuned to the output frequency.