JPS6268061A - Phase-shifting system of thyristor gate-pulse generating circuit - Google Patents

Abstract

PURPOSE:To optimize operation at the angle of delay by adding a phase-shifting circuit to a digital system thyristor gate-pulse generating circuit using a PLL and a ROM. CONSTITUTION:When the address assignment of a gate-pulse generating circuit 7 reaches 0, synchronizing with an output reference signal E from a monostable circuit 5, a gate pulse signal is memorized previously to a ROM so that gate pulses reach an alpha limiting angle. Consequently, the angle of delay reaches an alphalimit in a signal read from the gate-pulse generating circuit 7 when a counter 6 is cleared by the reference signal E, and the angle of delay reaches a KIPP angle when the contents of an address setter 12 are loaded by the reference signal E. When a power supply is turned ON and an output signal from a selecting circuit 10 is used as a KIPP-angle command, the angle of delay of an output signal from the gate-pulse generating circuit 7 reaches the KIPP angle when the angle E is outputted. When the output signal from the selecting circuit 10 is employed as an alpha limiting command, the angle of delay reaches the alpha limiting angle at predetermined cycles.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a thyristor that suppresses inrush current when transitioning from braking to electric operation in an inverter that has a regeneration function and uses an iris and a transistor in parallel. Goo 1-
This invention relates to a phase shifting method for a pulse generation circuit.

[Conventional technology and problems]

(Recently, machine spindle drives, etc.) - Some lunge inverters have a regeneration function as shown in Figure 5 to process energy during braking.

The inverter section 10 control circuit with this regeneration function is PLL.
FIG. 6 shows a block diagram of a device constructed using ROM and ROM.

4 is a frequency multiplier circuit using P L, L, 5 is a monostable signal for resetting and covering the counter 6 with a reference signal, and 6 is R, which divides 360 degrees of electrical angle into, for example, 512 equal parts and becomes an angle signal.
A counter specifies the address of OM7, and 7 is a ROM and latch circuit that generates the gate pulse of the thyristor.

Signal B is a power supply frequency signal, and the P]-1- circuit multiplies the frequency of signal B by 512 and outputs signal A. 1, that is, when signal B is 501-1 z, signal A is 25.6K
Hz. This signal A causes counter 6 to make one operation. Convert to a binary signal of 9 bits (BIT).

Correspondingly, the gate pulses of the thyristor of the converter 1 are stored in addresses O to 511 of the ROM 7, and are sequentially read out in accordance with the signal A.

However, in Figure 5, from the time of power on, thyristor goo 1
- When a pulse is outputted from the latch circuit 7 at the α limit angle, the capacitor 2 is rapidly charged, so an excessive charging current flows and blows out the fuse 3 on the input side.

Furthermore, even in the event of a failure, as long as the mode command is the electric mode, the thyristor gate pulse 2 will be at the α limit angle] There is a risk of erroneous electric shock when investigating the inside of the knit.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a phase shifting method for overcoming the drawbacks of conventional means and further improving digital thyristor gate pulse generation circuits.

[Summary of the Invention] In order to achieve the above-mentioned objects, the present invention provides a control circuit for a range inverter with a regeneration function by connecting Pl-1- and R.
In the thyristor gate pulse generation circuit that uses OM to eliminate adjustment, the gate pulse, which is set to the α limit angle during motor operation and the KIPP angle during braking, is changed using a phase detection circuit and a circuit that changes the clock frequency by pulse addition. This is a phase shifting method for the thyristor gate pulse generation circuit that optimizes the control delay angle operation.

[Embodiments of the invention]

A block diagram showing the circuit configuration in one embodiment of the present invention is shown in FIG.

In all drawings, the same reference numerals represent the same or corresponding parts.

8 is a frequency divider, 9 is a clock pulse mixing circuit, 10 is a selection circuit for selecting α limit 1- or kip (KfPP) angle, 11 is an α limit angle attainment detection circuit, 12 is kip (K[PP) angle] Address setting-3 fixed circuit.

First, the basic operation of the phase shift circuit will be explained.

FIG. 2 shows the change over time (1) of the control delay angle (°el: electrical angle) with respect to the phase shift command for one thyristor in the converter 1.

As soon as the N source is turned on, the gate pulse is set to KIPP.
It's on the corner.

Next, when the operating conditions are established and the phase shift command reaches the α limit, the control delay angle decreases at a constant rate, and when the α limit angle is reached, the gate pulse is fixed at the α limit angle.

When the phase shift command becomes kip (KIPP), the gate pulse instantly shifts to the kip (KIPP) angle.

If this operation is performed in response to a phase shift command, the above problem can be solved.

Next, individual functions will be explained using the block diagram shown in FIG.

FIG. 3 is a time chart of output signals corresponding to addresses of the gate pulse generation circuit 7 using the ROM and latch.

In synchronization with the output reference signal F of the monostable circuit 5, a gate pulse signal is stored in the ROM so that when the address designation of the gate pulse generation circuit 7 becomes 0, the gate pulse becomes the α limit angle. put.

Therefore, if the counter 6 is cleared with the reference signal QE, the control delay angle of the signal read out from the gate pulse generation circuit 7 becomes the α limit, and the address setter 12 receives the reference signal E.
If you load the contents of , the position of the dashed line a in Figure 3 will be
Since it becomes the α limit angle, control it! ll delay angle is KIPP
Become a corner.

However, the address settings are as follows.

If the KIPP angle is -170° and the α limit angle is -15'', then (formula 1) becomes 291.55 and 4, so change the address to 2.
Becomes 92.

Next, a method of shifting the phase of the section Ts in FIG. 2 will be explained.

In the time chart of the input/output signals of the pulse mixing circuit 90 shown in FIG.
The frequency is divided by r1/2 and the signal C is obtained. This is a reference signal of 512 times the electric i frequency.

However, during the period TS in FIG. 2, pulses are added to the signal C at a rate of one pulse at the rising edge of the output signal from the frequency divider 8, as shown in Tb in FIG.

As a result, one cycle of the power supply frequency, that is, 360°el
The number of pulses Np of the signal C between (electrical angles) is N if the frequency division ratio of the frequency divider 8 is K, and the advance of the control delay angle during one cycle by 80 is (electrical angles). .

When the above-described operations for each block are combined to form a phase shift circuit, the result is as follows.

After turning on the power, the output signal of the R circuit 10 is KIPP.
Let's call it the angle command. According to this regulation, when No. 13 is output, the counter 9 loads the address 292 (1 (') (') 100100 from M S B in the binary signal). Therefore, the output signal of the gate pulse generation circuit 7 The control v angle becomes the KIPP angle.

Next, when the output signal C of the selection-1 path 10 becomes the α limit command, the output signal C of the pulse mixing circuit 9 is (equation 2)
A pulse shown in is output every 1 recycle of the power supply frequency.

As a result, for every 11 nicles 360°el (electrical angle), 2
．． 81°el' (electrical angle) control delay angle advances, (170
KIPP at °-15°)/2.81°ζ55+J cycle
The α limit angle is reached from the angle.

The α limit angle attainment detection circuit 11 compares the reference signal E and the origin signal G output from the gate pulse generation circuit at address "0", detects that these two signals match, and activates the pulse mixing circuit. At the same time as stopping the pulse addition operation of 9, the counter 9 is cleared with the reference signal E and fixed at the α limit angle.

〔Effect of the invention〕

Thus, according to the present invention, by adding this phase shifting means to the digital thyristor gate pulse generation circuit using PLI- and ROM, the control delay angle operation is optimized, and the charging current of the capacitor 2 is This can prevent the fuse 3 from blowing out, and power can also be cut off by setting the control delay angle to the KIPP angle in the event of a failure.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention, Fig. 2 is its %11@ characteristic diagram, Fig. 3 is a time chart of the gate pulse generation circuit, and Fig. 4 is a diagram of the pulse mixing circuit. A time chart, FIG. 5 is a main circuit configuration diagram of a transistor inverter with regeneration function to which the present invention is applied, and FIG. 6 is a block diagram of a control circuit of the converter section. 1...Converter part, 2...Capacitor, 3...
Fuse, 4... Pl-1-circuit, 5... Monostable circuit, 6... Counter, 7... Gate pulse generation circuit, 8... Minute period 9... Pulse mixing circuit, 10...
- Control near color selection circuit, 11... α limit angle arrival detection circuit, 12... KIPP angle address setter.

Claims (1)

[Claims] In a digital thyristor gate pulse generation circuit using a ROM, the gate pulse phase is shifted at a constant rate from the KIPP angle to the α limit angle by changing the read clock signal of the ROM, and α From the limit angle to the KIPP angle, KIP is added to the address specified counter.
A gate pulse phase shift method characterized by loading a P-angle address and instantaneously transferring it.