JPS6267639A - System and circuit for controlling data flow subroutine - Google Patents

Abstract

PURPOSE:To give program flexibility by defining a part of contents of a table memory, where data destination addresses and instructions are stored, as a subroutine processing to control the data flow. CONSTITUTION:A subroutine start base address C1, an offset OF indicating the position of the corresponding parameter of a subroutine, a subroutine return base address a1, and an address R1 for referring to a memory 2 are stored in a table memory 1. The address a1 is temporarily stored in the memory 2. The input token to the memory 1 has the address a1 stored temporarily in the area of the memory 2 referred by the address R1, and the address C1 obtained by referring to the memory 1 and the offset OF are added and the resultant address is sent together with a data part. The memory 1 is referred to read out the address R1, and the address a1 in the memory 2 is read out and is added to the offset OF in the memory 1, and the resultant address is outputted. Thus, the program flexibility is given.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data flow processing device, and more particularly to subroutine processing.

(Prior Art and its Problems) Conventionally, there has been no data flow processing device equipped with a circuit for subroutine processing. For example, in the image pipeline processor (NEC Pp-D7281) or the "Data Flow Processing Device" disclosed in Japanese Patent Application Laid-open No. 58-70360, there is no instruction such as subroutine call subroutine return, so instructions such as 5AVE are used instead. . This requires the user to fix the return address of the subroutine in advance as an absolute address when assembling, which is complicated when creating a program, and there is no flexibility when changing the program. In addition, it was necessary to determine the corresponding addresses for each input/output parameter of the subroutine.

(Objective of the Invention) An object of the present invention is to eliminate the complexity of setting input/output parameters of subroutines in a data flow processing device as described above, facilitate program development, improve program flexibility, and further improve the flexibility of subroutines. An object of the present invention is to provide a subroutine control method and circuit that can be used to reduce program size.

(Structure of the Invention) According to the first aspect of the present invention, a table memory is provided in which a data destination address and an instruction are stored, and a token that is a set of an address value and a data value is input, and the Refers to the table memory, processes the data according to the instructions in the table memory, generates a new token by pairing the resulting new data with the destination address in the table memory, and further refers to the table memory. By repeating a series of processes,
In a subroutine control system in a data flow processing device that performs data processing, a part of a table memory is defined as subroutine processing, and a token that refers to the table memory in which a subroutine call instruction is stored sets the destination address to the start of the subroutine. A new token is generated by replacing the base address with an address that adds an offset depending on which input parameter of the subroutine the token corresponds to, and the address previously stored in the table memory is stored as the subroutine return base address. , and the token that referred to the table memory in which the subroutine return instruction was stored sets the destination address to the stored subroutine return base address and an offset according to which output parameter of the subroutine processing the token corresponds to. A data flow subroutine control system that controls subroutine calls, returns, and transfers input/output data can be obtained by replacing the address with an address added by t and generating a new token. According to the second aspect of the present invention, a link address and a data value that are data destination address values are input, and a function address that is referenced by the link address and indicates the destination address value and instruction storage address of the next data. a link table that stores the instruction code, a subroutine start address, and a return register number referenced by the function address, a decoder that decodes the instruction code in the function table, and a return register in the function table. Referenced by number,
a return register for storing a subroutine return address; an adder for adding the input link address and the subroutine return address in the return register; and an adder for adding the subroutine start address in the function table and the link address. and an multiplexer that selects one from the link address and the output of the two adders according to the output of the decoder, and is used to change the link address when performing subroutine processing and to change the subroutine return base address. A subroutine control circuit for exchanging storage input/output parameters is obtained.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the first invention of the present invention. Figure (a) shows the case where a subroutine call instruction is executed when a part of the table memory where data destination addresses and instructions are stored is defined as a subroutine, and figure (b) shows the case where a subroutine return instruction is executed. shows.

In FIG. 1(a), the table memory ■ contains a subroutine start base address C1, an offset point OF indicating which parameter of the subroutine corresponds to, a subroutine return base address a1, and an address R1 for referring to the memory ■. Consists of. Memory ■ is a memory for temporarily storing a subroutine return base address. The control method at the time of a subroutine call will be explained using FIG.

The input to memory 2 consists of a data section (not shown) and a memory reference address. By referring to the memory ■ using the memory reference address, the subroutine return base address a1, that is, the data destination address, is temporarily stored in the area of the memory ■ referred to by the address R1, which can also be obtained by referring to the table memory ■. Add the subroutine start base address C1 and the offset OF, and send this as the data destination address together with the data part of the input card. As a result, in the subroutine call, the data destination address a1 is replaced with the parameter input address (CI+F) within the subroutine, and the original destination address (subroutine return base address al) is stored in memory as the subroutine return base address at the end of the subroutine. Store it temporarily.

Next, the control method at the time of subroutine return will be explained using FIG. 1(b). In the same way as in the same figure (a), refer to the table memory ■ in the address field of the input card, read out the address R1 of the memory ■ in this, read the subroutine return address in the memory ■, and add it to the offset OF in the table memory ■. , as the destination address of the data, along with the data part of the input card.

The subroutine call and subroutine return methods have been explained above. Since the table memory ■ stores instructions and data destination addresses, it stores something that can be called a program for a data flow processing device, and subroutine control is possible by changing the data destination addresses in this memory. Become. FIG. 2 is a block diagram showing a second embodiment of the present invention. The components of the embodiment include a link table 0 that is referenced by a link address 99, which is the destination of data, and stores a function address indicating the destination address of the next data and an instruction storage address, and a function address 100 in the link table 0. Referenced by the latch 71 that outputs the function address 101 as input and the function address 101, the instruction code 103, subroutine start base address 104, return register number 1
05, a decoder 2 that decodes the instruction code 103 that is the output of the function table 1, and the output of the function table 1.
A return register 3 that is referenced by the return register pick-up 105 and stores a subroutine return base address 108; an adder 4 that adds the link address 102 and the subroutine start base address 104 in the function table 1; At the output, link address 10 latched in latch 71
2 and the subroutine return base address 108 which is the output of the return register 3, and the output 11 of the adder 4 based on the output signal 107 of the decoder 2.
There is a multiplexer 6 for selecting one from four signals: 0, the output 109 of the booster 5, the link address 102, the output of the function table 1, and the subroutine start base address 104. Latch 72 latches data 113 from the outside. The latch 116 latches the output 111 of the multiplexer 6 and the output 114 of the latch 72, and outputs the destination address of the next data (ie, new link address) and data value to the outside as a signal 116, respectively. The parts corresponding to the table memory in FIG. 1 are the link table O that stores the data destination address a1 in FIG. It is one. (a) in Figure 1,
(b) In order to realize both functions with one table memory, an instruction code is added to the function table 1, and by decoding it, both subroutine call and subroutine return instructions can be executed.

In FIG. 2 there is a decoder 2 for this purpose. Additionally, an address for referencing function table 1 was newly added to link table O. The portion corresponding to memory 3 in FIG. 1 corresponds to return register 3 in FIG. Also, additions S4 and S5 in FIG. 2 correspond to the addition section in FIG. 1.

Next, regarding Fig. 2, the timing chart of Fig. 6, and the timing chart of Fig. 7.
This will be explained in detail using the input/output logic table of the decoder 2 shown in the figure. By inputting the address value and data value 99 for referring to link table 1 from the outside and referring to link table O, the destination address of the next data, that is, the new link address, and the next table memory, that is, function table 1 are obtained. Get the function address to refer to.

Link table 0 is referenced from the outside using link address 99, and a function address and 100, which is the next data destination, are output. At the rising edge of the clock 201, the input data 100 is input to the latch 71 in FIG.
The subroutine start base address 104 and return register number 105 are read. From this instruction code 103 and the control bit 112 in the input latch, the decoder 2 outputs a selection signal 107 to the multiplexer 6 and a read/write signal 115 to the return register 3. When the read/write signal 115 is 1', it is read and when it is 0, it is write. When the input instruction code 103 of the decoder 2 is a subroutine jump (GO8UB) and the control bit 112 is 1', the selection signal 107 is 01' and the read/write signal 115 is read '1'. When the control bit 112 is O', the selection signal 107+t'00' and the read/write signal 115 are undefined. When the instruction code 103 is a subroutine return (RTNSUB), the selection signal 107 is 11' and the read/write signal 115 is a write signal "0" regardless of the control bit 112. For other instruction codes, the selection signal 107 is 10'. The multiplexer 6 selects the selection signals 107 ゞOO',
'01'.

According to '1σ, '11', signal 110.104.108
．． Select 109. Selected link address 111
is inputted and obtained through the latch 72, latched together with the data 114 in the output latch 73, and outputted to the outside as output data 116. This circuit uses two clocks 201.2
02 in a pipeline manner, and input latches 71.
72, the output latch 73 moves in synchronization with the tarlock 201.

Next, we will explain how this corresponds to the description of subroutines in data flow type programs. This method is applied to an image pipeline processor (NEC ppD728
1) function table section or JP-A-58
The processing when incorporated into the parameter table section of Publication No. 70360 (FIG. 23 of the Publication) will be explained. FIG. 5 shows a block diagram of the image pipeline processor. Image pipeline processor (lmPP)
), the link address ID' indicating the next destination of the data is stored in the link table LT22 (corresponding to 0 in FIG. 2).
(corresponding to 102 in FIG. 2), a function address PTA (corresponding to 101 in FIG. 2) indicating an instruction storage address, and a control bit S are stored. Function table FT23 contains instruction codes. When external data and a token with a link address ID are input, it passes through the input controller IC 21, refers to the link table LT 22 with the link address ID, and obtains the next link address ID' and function address P.
After obtaining TA, the function table FT23 is referred to using the function address PTA. An instruction code is obtained here, and processing according to the instruction code is performed in the data memory DM24 and the processing unit PU26. When processing unit PU26 is busy, temporary data is stored in queue Q25. When the processing is completed in the PU 26, the link table LT 22 is further referred to using the previously obtained link address ID', and this process is repeated. Function table FT
When the instruction No. 23 is an output instruction, the instruction is output from the queue Q25 to the outside through the output queue 0Q27 and the output controller 0C28. When the data cannot be output to the outside, it is temporarily stored in the output queue 0Q27.

Therefore, subroutine control in such a data-flow type processor is based on the function table F.
Store the instruction code corresponding to the processing part of the subroutine in T23, change the link address ID so that the FT part is referenced when the subroutine is called, and return it to the link address ID that was originally attached before the call when the subroutine returns. Is required. For this reason, this embodiment uses a return register (FIG. 2, 3) that temporarily stores the link address at the time of return. Furthermore, it is necessary to replace multiple pieces of input data to a subroutine with link addresses indicating the entrances of the respective corresponding subroutines. These are input as consecutive link addresses in order from the start address of the subroutine, and the corresponding input data is stored in advance in the link table LT. Next, the state of the actual link table function table will be explained in association with the description of the lmPP assembler.

FIG. 3 shows an assembler description that calls subroutine (2) from the main program. All are functional descriptions, and from the LINK statement, link table, FUNCT
The contents of the function table are generated from the ION statement. The content generated in each table is called a template. Subroutine S is bl, b2 in the main program.
．． With b3 as input, al, a2. This is a program that outputs a3. In the subroutine description, cl, c2. c3, output el,
e2. e3 is used. By writing the assembler description as shown in FIG. 3, a template as shown in FIG. 4 is generated. In other words, from the LINK statement ■ which describes the instruction to call subroutine S, ID=al, S=1 and ID=1
゜S=0 and ID=2. A template with S=0 is generated. This corresponds to the subroutine call part (2) in FIG. This sets the next destination link address of the template of the data first input to the subroutine among the input data of the subroutine to be al, and sets the control bit S=1. For the destination link address of the template for data that will be input later into the subroutine, the descriptions of link (2) are numbered sequentially starting from 1. The template into which the input data to the subroutine S is input, as shown by the link text ■ in FIG. 3, is the subroutine input section shown by O in FIG. Similarly, the template generated for the link statement ■ in FIG. 3 is the subroutine output portion shown by ■ in FIG. 4. Further, a template shown by ■ in FIG. 4 is generated from the link statement (■) in the part that receives the output data of the subroutine in FIG.

On the other hand, as shown in Figure 4, the function table contains the start address C1 of the subroutine and the command to jump to the subroutine (GO8UB) or the command to return from the subroutine (R
TNSUB), the instruction code (OP), and the return register number (OP) that temporarily stores the return address of the subroutine.
A template containing the RNO) is generated.

Next, an outline of the operation will be explained. As shown by ■ in Figure 4, the input data of the subroutine, that is, the link address I
D=M, b2. Data with b3 are linked to link tables bl, b2. Refer to the address of b3 and set the new link address as Ib' = al,
1.2 Control Afrag 8=1. As O, O, refer to the function table using the function address F1. In the function table, the function table at address F1 contains an instruction GO8UB that jumps to a subroutine as an instruction code, so the next process is performed according to the control bit S. When S=1, return register number (RNO) of function table
The link address al (return address) in the link table is stored in the return register indicated by , and a new subroutine start address C in the function table is stored.
1 as the link address. When S=0, the subroutine start address C1 is added to the link address in the link table (1 or 2 in this case) and replaced as a new link address.

As a result, link addresses bl, b2 . The data with b3 are the link addresses CI, C1+1 . It is replaced with C1+2 and al is stored in the return register. Since the link addresses of the subroutine input data are continuous as described above, 01+1=02. C1+2=03, so the link addresses bl, b2. The data that entered b3 changes to the data that enters link addresses CI, C2, and C3.

On the other hand, when returning from the subroutine, the data to which link addresses el, C2, and C3 are attached refer to the link addresses, as shown by the link statement (■) in FIG. The link table for link addresses el, C2, and C3 contains a function address FIO, and when this is referenced, RINSUB is entered as an instruction code.

In this case, the return link address in the return register is read out using the return register number RNO in the function table FIO, and is added to the link address in the link table. That is, in the example of FIG. 4, the data to which link addresses el, C2, and C3 are attached are al+0.
al+2. It is replaced with the link address of al+2. Since the return link addresses of the output data of the subroutine are also consecutive, al + 1 = a2゜al +
2 = C3, and the link addresses el, C2, C3 of the output data of the subroutine are changed to the return link addresses al, C2°C3.

(Effect of the invention) By incorporating the present invention into a data flow processing device,
Easier to use subroutines in dataflow programs. That is, subroutine calls and return instructions can be set, the start address of the subroutine can be determined arbitrarily, and input and output data of the subroutine can be exchanged automatically without any burden on the user. This eliminates the complexity of conventional program development and the lack of flexibility when changing programs when using subroutines, and the use of subroutines also reduces program size.

[Brief explanation of drawings]

Figures 1 (a) and (b) are basic block diagrams of the present invention, Figure 2 is a block diagram showing an embodiment of the present invention, and Figure 3 is a program using subroutines in a data flow processing device. FIG. 4 is a diagram showing the contents of the link table function table return address generated from the assembler description in FIG. 3. FIG. 5 is a data flow type to which the present invention is applied. FIG. 6 is a block diagram showing the processing device, FIG. 6 is a timing signal diagram of FIG. 2, and FIG. 7 is a diagram showing logical input/output of the decoder 2 of FIG. In the figure, ■ is table memory, ■ is memory, O is link table, 1 is function table, 2 is decoder, 3 is return register, 4゜5 is adder, 6 is multiplexer, 21 is input controller, 22 is link table , 23 is a function table, 24 is a data memory, 25 is a queue, 26 is a processing unit, 27 is an output queue, 2
8 is the patent attorney representing the output controller, 1st floor
jtJ:, N-Imo Z Figure

Claims (2)

[Claims] (1) A table memory in which a data destination address and an instruction are stored is provided, a token that is a pair of an address value and a data value is input, the table memory is referred to by the address, and the instruction in the table memory is Accordingly, data processing is performed by processing the data, generating a new token by pairing the resulting new data with the destination address in the table memory, and repeating a series of processes that refer to the table memory. In a subroutine control method in a data flow processing device, a part of a table memory is defined as subroutine processing, and a token that refers to the table memory in which a subroutine call instruction is stored sets its destination address to the start base address of the subroutine. and generates a new token by adding an offset depending on which input parameter of the subroutine the token corresponds to, and stores the address previously stored in the table memory as a subroutine return base address. , and the token that referred to the table memory in which the subroutine return instruction was stored offsets the destination address from the stored subroutine return base address according to which output parameter of the subroutine processing the token corresponds to. Replace the address with the addition of
A data flow subroutine control method characterized by controlling subroutine calls, returns, and passing input/output parameters by generating new tokens. (2) A link table that receives a link address and a data value that are the destination address value of data, is referenced by the link address, and stores a function address that indicates the destination address value and instruction storage address of the next data, and the function A function table that is referenced by the address and stores instruction codes, subroutine start addresses, and return register numbers, a decoder that decodes the instruction code in the function table, and a subroutine return base address that is referenced by the return register number in the function table. a return register for storing; an adder for adding the input link address and the subroutine return base address in the return register; and an adder for adding the subroutine start base address in the function table and the link address. ,
From the link address and the outputs of the two adders,
The data flow subroutine includes an multiplexer that selects one based on the output of the decoder, and performs reassignment of the link address, storage of a subroutine return base address, and exchange of input/output parameters when performing subroutine processing. control circuit.