JPS60110042A - Address generating circuit of program memory - Google Patents

Abstract

PURPOSE:To attain a high-speed action and also to decrease the number of IC terminals for an address generating circuit of a program memory, by receiving the next address control signal from an external program memory to decide the address of the next clock cycle. CONSTITUTION:The next address control signal NAC contained in an instruction read out of a program memory and the condition signal are supplied to a controller 26 within a sequencer 21. The controller 26 controls the push/pop action of a stack 25 to which the output of an incrementer consisting of an adder 23 and a register 24 is supplied. Then the output of the controller 26, an address bus source selection signal ABS contained in the instruction read out of the program memory and the condition signal are supplied to a decoder 27. Then the decoder 27 produces the control signal to control buffers 31-36.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program memory that is included in a microprogram control unit and applied to a microzologram sequencer that determines the address of a microinstruction to be executed next. The present invention relates to an address generation circuit.

"Background technology and its problems" A microzologram sequencer (hereinafter referred to as sequencer) 1 has a program memory 2 as shown in FIG.
Generates an address for. The microinstruction read from the zologram memory 2 is loaded into the register 3. Sequencer 1 is supplied with an address from the outside via address bus 4 . This external address is
In addition to the jump address PR and next address control signal NAC generated by the program memory 2 accessed by the sequencer 1, there is also an address MAP generated by comparing instructions from the upper zologram level.
, the vector address VE given by Interlazoto, etc. Further, a condition signal is supplied to the selector 5, and the selector 5 is controlled by the condition select signal from the register 3. The condition signal is the contents of an accumulator, etc., and is used to determine whether to jump or go to a subroutine.

'' The double sequencer 1 has a configuration surrounded by a broken line in FIG. 2. The address output from the sequencer 1 is generated from the selector 6.

The selector 6 is supplied with inputs I, S, 'D, and H. The address obtained by adding "-1" to the output of the selector 6 by the adder 7 is supplied to the register 8, and this register 8
The output of is considered as input ■. If the selector 6 selects this manual input (2), the sequencer 1 operates as a so-called counter, and the address increments by 1 every clock. An address from an incrementer consisting of an adder 7 and a register 8 is temporarily stored in a stack 9, and the output of the stack 9 is used as the input S of the selector 6.

Stack 9 is LIFO(La5t-in, fi
This stack 9 is called rst"out" and stores different addresses in sequence, and the one that was put in last is the first one to be taken out.This stack 9 is
It is necessary to call the subroutine of the microprogram multiple times. That is, an address obtained by adding 1 to the current address from register 8 is stored in stack 9, and when a return instruction comes, the output of stack 9 is selected.

The D input of the selector 6 is given from the external address bus 4 and corresponds to an address jump. Jump address P where zologram memory 2 occurs
R, a jump address MAP obtained by decoding instructions from a higher program level and serving as an initial address for selecting multiple microprograms, and a vector address VEC given by Interazoto, each consisting of I and Raichi1. Buffers 10, 11, and 12 selectively supply the address bus 4. Addresses from the outside cannot necessarily be input at the timing of use, so a register 13 is provided that is connected to the input of the selector 6, and such an address can be input to the register 13 in advance. and use it when needed.

Buffers 10, 11.12 are controlled by the output of decoder 14. A select signal for the selector 6, a control signal for the stack 9, and an input signal for the decoder 140 are generated by the controller 15. The controller 15 controls the next address control signal NAC generated by the program memory 2 so that each part operates in a predetermined manner.
C is decoded and control signals are given to each part.

This next address control signal NAC is coded with instructions such as jump, jump subroutine, and increment.

The controller 15 also includes an external selector 5 (first
(See figure). This condition signal is used to perform conditional jumps, conditional jump subroutines, conditional IJ turns, etc. A command meaning to set a condition is used to control the next address by looking at this condition signal. Ru.

In the conventional sequencer 1 described above, an address input from the outside is executed in the following procedure.

First, the program memory 2 is accessed, and a command to select an external address (next address control signal NAC) is supplied to the crab controller 15.
It is decoded by the hunt roller 15.

Next, it is decoded by the decoder 14, for example, the buffer 10 is opened, and the external address MΔP is input to the selector 6 via the address bus 4, selected by the selector 6, and given to the program memory 2 again.

In this operation, the operating speed is determined by the time from when an instruction is output from the register 3 provided on the output side of the programmer 2 to when the next stable instruction is read into the register 3. Therefore, the operating speed of sequencer 1 is
and program memory 20. The conventional sequencer 1 does not allow address selection.
1.12 selection and selector 6 have 02 stages of mark selection, which has the disadvantage that it takes time for the address to appear on the output. Furthermore, since it is not a next address control code but is encoded, it has the disadvantage that it takes time to decipher it.

Furthermore, the conventional sequencer 1 is usually a one-chip IC.
However, since it is necessary to input and output address pins and numbers, the number of IC terminals is large, and the IC
The problem of increased costs arose when constructing the structure.

``Object of the Invention'' Therefore, an object of the present invention is to provide an address generation circuit that operates faster than the conventional one.

Another object of the present invention is to provide an address generation circuit that can reduce the number of terminals when configured as an IC circuit.

F-Summary of the Invention This invention provides an address incrementer that adds 1 to the current address value in order to increment every clock, a stack memory that stores the output of this address incrementer, and an address incrementer and a stack memory. It is equipped with an address bus that is commonly connected to the output of the program memory and the outside, receives a next address control signal from an external program memory, determines the address of the program memory in the next clock cycle, and gives the address from the address bus. This is an address generation circuit for a program memory.

"Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to FIG.

In FIG. 3, numeral 21 surrounded by a broken line is a sequencer to which the present invention is applied, and has an IC circuit configuration.・Address bus 2 leading from the inside of this IC to the outside
2 is provided, and all address selection is achieved by selecting the bus source of this address bus 22. Sequencer 2
1 includes an incrementer consisting of an adder 23 and a register 24, and a stack 25 to which the output of the incrementer is supplied.The input of the incrementer is connected to the address bus 22, and the output thereof is connected to the address bus 22. Buffer 31
The output of the stack 25 is connected to the address bus 22 via a buffer 32.

Outside the sequencer 21, the vector address VEC is supplied to the address node 22 via the buffer 33, and the vector address MAP is supplied to the register 28 and the buffer 34.
The jump address PR from the zologram memory is supplied to the address bus 22 via the buffer 35, and the jump address PR from the register 2 is supplied to the address bus 22 via the buffer 35.
9 and ) (supplied to the address bus 22 via the sofa 36. The addresses generated by the sequencer 21 are taken from the address bus 22 outside the sequencer 21 and supplied to the zologram memory.

A controller 26 in the sequencer 21 is supplied with the next address control code included in the instruction read from the program memory, and the controller 26- controls the stack/pop operation of the stack 25. A decoder 21 is provided in the sequencer 21, and the decoder 27 is supplied with the output of the controller 26, an address bus source selection signal ABS included in the instruction read from the program memory, and a condition signal. The decoder 27 provides buffers 31 , 32 , 33 ,
34, 35.

A control signal is generated to control 36.

In this way, address bus source selection is considered separately from next address control and is directly decoded, so instructions from program memory registers are immediately decoded and each buffer is selected, so fo Durham memory can be accessed at high speed. be done.

Also, an IC for connecting the sequencer 21 and the outside
The number of terminals is the sum of the number of address bits of the address bus 22 and the number of pits of each of the condition signal, netast address control signal NAC, and address bus source selection signal ABS.

"Effects of the Invention" According to the present invention, unlike the conventional sequencer 1, the address selection is performed in one stage of the buffer, and the address bus source selection signal is immediately decoded, so the operation is faster than the conventional sequencer 1. A possible sequencer 21 can be realized. This invention does not require IC terminals for both address input and address output;
This has the advantage that the number of C terminals can be reduced, and the circuit built into the IC is simpler than the conventional 7-controller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a conventional microprogram control unit to which the present invention can be applied, FIG. 2 is a block diagram of a conventional sequencer, and FIG. 3 is a block diagram of an embodiment of the present invention. . 21.../-kenza, 22...-address bus, 31.32.33.34.35.36...
・－・・・Buffer. Agent Masato Sugiura

Claims (1)

[Claims] An address incrementer that adds 1 to the current address value in order to increment every clock, a stack memory that stores the output of this address incrementer, and an output common to the output of the address incrementer and the stack memory and the outside. It is equipped with an address bus to be connected, receives a next address control signal from an external program memory, determines the address in the next clock cycle of the program memory described in 1., and provides the address from the address bus. Characteristic address generation circuit of zologram memory.