JPS6267637A - Array multiplier - Google Patents

Abstract

PURPOSE:To perform a quick divisional operation by detecting the decoded signal of a multiplier at the divisional operation time and generating an increment signal when a multiplicand is negative and selecting the increment signal for divisional operation and selecting the multiplicand for non-divisional operation. CONSTITUTION:A multiplying array is divided into several array blocks 121.... Operating cells C11-Cij are arranged in each of blocks 121.... Each of cells C11-Cij consists of a selector SEL1 to which Xi, the inverse of Xi, etc. are inputted, a selector SEL2 to which the output X' of the selector SEL1, an increment signal INC, etc. are inputted, and a full adder FA to which the output X'' of the selector SEL2, a sum signal S, and carry C are inputted. The decoded signal of the multiplier is detected for divisional operation and the signal INC is generated when the multiplicand is negative. The selector SEL2 selects the signal INC for divisional operation and selects the signal X' for non-divisional operation. Thus, the quick divisional operation is performed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an array multiplier that can be divided into two using the Booth algorithm. Concerning the array multiplier used.

[Technical background of the invention and its problems]

Conventionally, a multiplier having a configuration as shown in the block diagram of FIG. 5, for example, has been used as a multiplier that can be divided into two. In the figure, multipliers MO to M3 each have an m-bit×m-bit multiplication function.

These multipliers MO to M3 each have a multiplicand X, .
XL (XII: upper bit, xL: lower bit) and multiplier y11. Y, (Yl (: upper bit, Y,: lower bit) is selectively supplied. In other words, multiplier MO
is supplied with the multiplicand X 9 multiplier Y, which is output as an operation (multiplication) output signal ZO on the lower bit side, and the output on the upper bit H side is supplied to the adder AO.

On the other hand, the multiplicand X and the multiplier Y are supplied to the multiplier M1, and the calculation output on the lower bit L side is supplied to the adder AO via the selector SO. The addition output from adder AO is supplied to adder A1, and the carry Ca is supplied to adder A2. The calculation output of the higher bit H side of the multiplier M1 is supplied to the adder A2 via the selector S1.

Furthermore, the multiplicand X5 and the multiplier YH are supplied to the multiplier M2, and the calculation output on the lower bit L side is supplied to the adder A1 via the selector S2. The addition output from adder A1 is output as output signal z1, and carry Ca is supplied to adder A3.

On the other hand, the calculation output of the higher bit H side of the multiplier M2 is supplied to the adder A2 via the selector S1.

The addition output of adder A2 is supplied to adder A3, and carry Ca is supplied to adder A4.

Further, the multiplicand X2 and the multiplier Y11 are supplied to the multiplier M3, and the calculation output on the lower pit L side is supplied to the adder A3. The addition output from adder A3 is output as output signal Z2, and carry Ca is supplied to adder A5. On the other hand, the calculation output on the upper pit H side of multiplier M3 is output from adder A
4. This adder A4 has “0” as the addition number.
'' is supplied to the adder A5, and an output based on the output of the multiplier M3 and the carry Ca of the adder A2 is supplied to the adder A5.

Further, 0'' is supplied to the adder A5 as the addition number, and an output based on the addition output of the adder A4 and the carry Ca of the adder A3 is output as the output signal Z3. .

In such a configuration, when performing 2m bits x 2m bits multiplication, the selector SO selects the output of the lower bit L side of the multiplier M1, and the selector S1 selects the output of the higher bit H side of the multiplier M1. With,
The output of the higher bit H side of the multiplier M2 is selected. Also,
The output of the lower bit L side of the multiplier M2 is selected by the selector S2. By doing this, multiplication of 2m bits x 2m bits can be performed.

On the other hand, when performing two systems of multiplication of m bits x m bits, the multiplier M
1. The output of M2 is set to ``0'' and this ``0'' is supplied to the adders AO, AI and A2 as the addition number.By doing this, Zl and 72 have rXL-X, J, and Z3
and 72, rXH-X, , J are obtained, respectively.

When constructing a multiplier as described above, various problems occur as described below.

First of all, there are a lot of wires. In particular, the number of wiring increases where the operands X and Y are inputted, and where the results of the q multipliers MO to M3 are inputted to the next stage selector 5o-82 and adder AO-A3.

This tendency becomes more pronounced as the bit length increases.

Second, there are many redundant circuits. For example, each multiplier MO-M3
has a built-in final phase adder, and adders AO to A
It overlaps with the function of 5. Further, the selectors SO to S2 are also not required when calculating 2m bits by 2m bits.

Thirdly, the above 1. For the second reason, the pattern area increases when integrated into an LSI (large scale integration).

Fourth, the operating speed is slow. This is because, as described above, when there are many (long) wires, delays due to wire capacitance and the like increase.

To solve the above-mentioned problems, a divisible device can be constructed using an array multiplier suitable for LSI (large scale integration). As such, for example, the one shown in FIG. 6 has been proposed. That is, as shown in the block diagram of FIG. 6, the multiplication array is divided into four parts, and the first array block 121 performs the multiplication of X-Yll, and the fourth array block 124 performs the multiplication of X-Y. At this time, the selection control signal B is input to the X input of the second array block 122.
0 through the first selection circuit 13 controlled by DIV.
'' and no multiplication is performed here. In addition, the selection control signal BDIV is also applied to the X input of the third array block 123.
0'' is applied through the second selection circuit 15 controlled by
The separation circuit 14 controlled by DIV separates X,.Y into Zl and ZO, and XH.[Yll into 23. It is output to Z2.

The key to increasing the speed of multipliers is reducing partial products, and one of them is the Booth algorithm. However, when constructing a divisible array multiplier using the Booth algorithm, the following problems arise. That is, the Booth algorithm decodes three adjacent bits of the multiplier, and converts the multiplicand X into X.

-X, 2X, -2X, "O" (7) 5 different variations are given to each cell. Among these, negative numbers -X and -2X are expressed as two's complement by creating negation X and 2X, and converting them to LSB.
Add 1″.

As a multiplier that performs such operations, a structure as shown in the block diagram of FIG. 7 has been proposed. In FIG. 7, when the control signals used to select -X and -2X at each stage are established, half adder 1-
Add it 1 u to I A. And final sum addition 1
When inputting to 25, narrow it down to 2 people. Although this has the advantage that a dividable Booth multiplier can be constructed without destroying the regulation properties of array multipliers, it has the problem of increasing unnecessary hardware.

[Purpose of the invention]

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce hardware and delay time, and as a result, the booth is suitable for LSI implementation, has regular wiring, and can perform high-speed calculations. The purpose is to provide a divisible array multiplier using an algorithm.

(Summary of the Invention) In order to achieve the above object, the present invention provides an arithmetic means in which arithmetic cells are arranged to divide and multiply a multiplier and a multiplicand into half words, and a decode signal of the multiplier during a -division operation. To provide an array multiplier comprising means for generating an increment signal when a multiplicand becomes a negative number, selecting an increment signal during a division operation, and selecting a multiplicand and applying it to an operation cell during a non-division operation.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an array multiplier according to an embodiment of the present invention, FIG. 2 is a partially enlarged view of FIG. 1, FIG. 3 is a block diagram of the arithmetic cell in FIG. 1, and FIG. FIG. 4 is a block diagram showing details of the arithmetic cell in FIG. 3;

As shown in each figure, the multiplication array includes a first array block 121, a second array block 122, a third array block 123 and a fourth array block 124.
It is divided into four blocks. Each block 121,
Arithmetic cells 011 to C1j are arranged at 122, 123° and 124. Note that the calculation cell C-C1, is X,,X,,
X, -1°11 1J I +X,
-X, -2X, 2X, the first selector 5EL1 to which "0" is input, and the output X' of the first selector 5EL1,
a second selector 5EL2 to which the increment signal INC and separation control signal DrV are input; and a second t-rector 5.
It is composed of a full adder FA to which the output X'' of EL2, the sum signal S and the carry C are input, and the sum output S and the carry output ut Cout are sent out.

In such a configuration, when dividing into two, O'' is always input to the X input of the third array block 123. Therefore, in this cell, the first array block 121 or the fourth
Since only the addition of the sum signal S of the array block 124 and the carry C is performed here, the input of X is vacant. Therefore, when dividing, decoded signals X, -X, 2X, -2
X.

When -X or -2X of "O" is active, 1" is sent to the vacant X input, and the sum signal S and carry C
Find the sum of

That is, five decoded signals X, -X, 2X.

When -X or -2x of =2x and "O" is active, this is determined by the OR gate, and the increment signal INC is sent to the arithmetic cell C1j as a "1" signal.

In the calculation cell C1j, X and -X, respectively.

Selector 5EL1 to which 2X and -2X are input selects four
Select input x, ,x, ,x, ,x, ,+
+ +-. When nothing is selected, "°0" is activated, and the output X' of the selector 5ELI becomes "OI+."
' and the increment signal INC, the division control signal DIV
is selected by the selector 5EL2 to which is input. That is, the increment signal INC is selected when dividing, and the output X' is selected when not dividing.

FIG. 2 shows the boundary between the first array block 121 and the third array block 123. Originally the first 7
Arithmetic cell C11 in the first column on the right side of the lay lock 121
, C21 should be added "'1", but 3 has already been added.
Since two inputs have been determined, "1" is added to the route that the sum signal S of that cell should take. In other words, calculation cell C23
, C33 corresponds to this, and when negative numbers -X and -2X occur during division, "1" is added to 188 in each stage.

As a result of the array multiplication of each array block 121, 122, 123, 124, the sum output S and the carry output C8, t are narrowed down to two by the half adder HA.

Note that the increment signal INC from the bottom stage is also added to the half adder HA as a carry.

As described above, the two signals are added in the final phase adder 125 to obtain the final multiplication result.

Note that in the configuration of this embodiment, there is a delay of one stage of the half adder HA, but since the signal passes through the half adder HA while the final phase adder is performing the final phase addition, it is essentially a half adder HA. It can be seen that there is no delay of 1-IA. On the contrary, since the scale of the half adder 1-IA can be reduced by half compared to the configuration shown in FIG. 7, it is effective in reducing the hardware cost.

〔Effect of the invention〕

As described above, according to the present invention, the number of wirings is small, the configuration is regular, so it is suitable for LSI integration, there are few redundant circuits, the amount of hardware can be reduced, and the area is reduced, so speed is improved, etc. An array multiplier with the following characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an array multiplier according to an embodiment of the present invention, FIG. 2 is a partially enlarged view of FIG. 1, FIG. 3 is a block diagram of the arithmetic cell in FIG. 1, and FIG. Figure 3 is a block diagram showing details of the arithmetic cell, Figure 5 is a block diagram of a conventional divisible array multiplier, Figure 6 is a block diagram of a well-known divisible Booth multiplier, and Figure 7 is a block diagram of a known divisible array multiplier. FIG. 2 is a block diagram of an incrementing array multiplier. 121.122, 123.124...Array block, HA...Half adder, 125...Final phase adder, 5EL1.5EL2...Selector. Applicant's representative Mr. Sato-O No. 3 Ash Figure 4

Claims (1)

[Claims] A calculation means arranged with calculation cells that divides the multiplier and the multiplicand into half words and multiplies them, detects the decode signal of the multiplier during the division operation, generates an increment signal when the multiplicand becomes a negative number, and generates an increment signal during the division operation. and means for selecting a multiplicand and applying it to the operation cell during non-divided operation.