JPH02112020A - Unit adder and parallel multiplier - Google Patents

Abstract

PURPOSE:To improve the calculating speed of the title adder and multiplier by providing a gate circuit which produces a carry output to a higher digit by performing a logical process on part of outputs of plural gate circuits and two-stage gate circuits which produce a sum output by performing logical processes on the remaining outputs and a carry input from a low order digit. CONSTITUTION:The unit adder and parallel multiplier of this inventions are provided with four sets of NAND circuits G1-G14 which respectively input three inputs of different combinations of four inputs Xo-X3 of a certain digit of binary numbers to be subjected to addition and take the AND of the inputs and a NAND circuit G2 which outputs the 1st carry output to a higher digit by taking the ND of the outputs of the circuits G11-G14. In addition, an exclusive NOR circuit G6 which takes on OR for producing a sum output S by taking the exclusive OR of the output of an exclusive OR circuit G5 and carry input from a lower digit, NOR circuit G7 which takes the OR of the output of the circuit G5 and a carry input from a lower digit, etc., are also provided. Therefore, the number of passed gate stages can be reduced to 3/4 and the calculating speed can be improved as compared with the conventional 4-stage example, since the number of gate stages to be passed from the four inputs to the sum output becomes three.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a unit adder and a binary parallel multiplier realized on a semiconductor integrated circuit, and particularly relates to a unit adder and a binary parallel multiplier that have 5 inputs and 3 outputs. This paper relates to a circuit configuration of an adder and a parallel multiplier using a binary addition method capable of increasing calculation speed.

(Prior art) When realizing a binary parallel multiplier on a VLSI (very large scale integrated circuit), (1) the quadratic Booth algorithm, (2
) It is common to use a carry-save method in which full adders are arranged vertically and horizontally.
EIE L E CT RON I CS 1978
．． No. 5.29, P, 76-89rA Look at Multiplier Circuit Systems Using Parallel Computing Systems, Which Are Increasingly LSI-based.

By using the above quadratic Booth algorithm,
By reducing the number of calculation stages and using the carry-save method, it is possible to improve the regularity of a pattern suitable for LSI. However, when calculation speed is considered important, the carry-save method (2) is not optimal, and Wallace's addition method, which performs binary addition, is superior.

Furthermore, with the expansion of the application fields of L and Sl and the development of digital processing, the demand for higher speed digital operation LSIs is increasing.

However, although Wallace's addition method can reduce the number of calculation stages, it results in a complicated layout pattern when integrated into an LSI. In particular, as the number of digits handled increases, the complexity of the pattern tends to increase. This increase in pattern complexity is manifested in an increase in the number of wires connecting each pixel within the LSI.

Considering the current LSI technology, the problem of increasing the speed of calculation is
In addition to increasing the speed of the elements themselves, this greatly depends on reducing the wiring capacitance due to wiring between elements. Therefore, in order to increase the speed of the arithmetic unit, it is necessary to minimize or suppress the wiring length.
We must also consider reducing wiring capacity and regularizing the layout configuration.

Multipliers that use the conventional Wallas addition method have a full adder as their basic configuration, but large-scale multipliers with 32 bits or more require too complicated wiring, and the layout cannot accommodate the complicated wiring. It may not be possible, or even if it is possible, it will take a huge amount of time to respond, so the actual L
It was not used in SI.

Recently, computer-aided design (CAD)
) With the development of technology, it is possible to perform the above layout, but with this CAD technology, it is difficult to minimize or suppress the wiring length as described above, and this leads to deterioration of LSI characteristics due to an increase in wiring capacitance. This tendency becomes more pronounced as the scale of calculation becomes larger.

(Problems to be Solved by the Invention) As described above, the multiplier that adopts the conventional class of addition method has a complicated layout pattern when integrated into an LSI, and it is difficult to perform large-scale multiplication. In the vessel,
This was done to solve the problem of overly complex wiring, which makes it difficult to minimize or suppress the wiring length, and leads to deterioration of LSI characteristics due to increased wiring capacitance. The number of calculation stages is smaller than that of the conventional method, and the layout pattern is highly regular, simplifying the layout, making it possible to minimize or suppress the wiring length, and increasing the calculation speed by reducing the wiring capacity, especially for 32 bits or more. The purpose of this invention is to provide a parallel multiplier suitable for large-scale high-speed multipliers.

Another object of the present invention is to provide a unit adder suitable as a high-speed 5-input, 3-output adder used, for example, as a basic component of the above-mentioned parallel multiplier.

[Structure of the Invention] (Means for Solving the Problems) The unit adder of the present invention has two inputs or three inputs of different combinations among four inputs of a certain digit of a binary number to be added. A plurality of one-stage gate circuits each input in a corresponding manner, and a one-stage or two-stage gate circuit that logically processes a part of the outputs of these multiple gate circuits to generate a carry output to the upper digit. and a two-stage gate circuit that logically processes the remainder of the outputs of the plurality of gate circuits and the carry input from the lower digits to generate a sum output.

Further, the parallel multiplier of the present invention is characterized in that a parallel multiplier array that performs addition in the form of a binary tree is configured using the unit adder as a constituent unit.

(Function) The unit adder described above has three stages of passing gates from four inputs to the sum output. The number of passing gate stages is reduced by 3/4 times compared to the four stages in the previous example, making it possible to increase the speed.

In addition, the difference between the number of passing gate stages from the four inputs to the sum output and the number of passing gate stages until the carry output is only one stage, and there is almost no time difference between the above 100 outputs, and the calculation using this unit adder Enables faster circuits. Furthermore, as described above, since there is little difference in the number of pass gate stages, the circuit pattern has excellent symmetry and a compact layout is possible.

In addition, the above-mentioned parallel multiplier uses the high-speed 5-input 3-output unit adders as described above as a constituent unit and combines them in a binary tree to form a parallel multiplier array, so the basic structure is a full adder. The number of calculation stages is smaller than that of the conventional class addition method, the layout pattern is highly regular, simplifying the layout, the wiring length can be minimized or suppressed, and the calculation speed is increased by reducing the wiring capacity. This makes it particularly suitable for large-scale high-speed multipliers of 32 bits or more.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

The unit adder shown in FIG. 1 has four inputs X of certain digits of binary numbers to be added. Three inputs of different □ combinations of ~X3 (Xo-X2), (X1~Xt), (X
2~Xo) and (X3~X1) are respectively inputted correspondingly, and four sets of NAND circuits G1. ~G1
4 and the respective outputs of these four sets of first NAND circuits 011 to G14 to generate a first carry output Co to the upper digit.
A NAND circuit G2 that generates u t and four inputs Xo-
NOR circuit G3 that takes the logical sum of x3 and four inputs Xo~
Two inputs of different combinations of X3 (X0%X
1), (X2., X3) are respectively input in correspondence l2,
Two sets of exclusive OR circuits G4. ,G
42, an exclusive OR circuit G5 that takes the exclusive OR of each output of these two sets of exclusive OR circuits 041 and G42, and an exclusive OR circuit G5 that takes the exclusive OR of each output of the two sets of exclusive OR circuits 041 and G42, and An exclusive NOR circuit G6 that performs a logical sum to generate a sum output S, and an exclusive OR circuit G5
A NOR circuit G7 which takes the logical sum of the output of Cin and the carry input Cin from the lower digit, and a second carry output C to the upper digit by taking the logical sum of the output of this NOR circuit G7 and the output of the NOR circuit G3. It consists of a NOR circuit G8 that generates .

On the other hand, the unit adder shown in FIG. 2 receives four inputs X of a certain digit of a binary number to be added. Two inputs cxoSx, ) (X2, XI
) are respectively input and logically summed, two sets of OR circuits G 2 ], + G 212, and a NAND circuit G22 . , an inverter circuit G222 that inverts the output of this NAND circuit G221 to generate a first carry output Cout to the upper digit, and four inputs X. -X
, two inputs of different combinations (Xo s
Two sets of exclusive OR circuits G23 which input XI ) and (X2 %
1, G23□ and these two sets of exclusive OR circuit G231
An exclusive OR circuit G24 calculates the exclusive OR of each output of %G232, and an exclusive OR of the output of this exclusive OR circuit G24 and the carry input Cin from the lower digit is generated to generate a sum output S. An exclusive OR circuit G25, a NAND circuit G26 which takes the AND of the output of the exclusive OR circuit G24 and the carry input Cin from the lower digit, and two inputs (X□ s Xs ), (
Two sets of AND circuits G27. G272 and this 2
Set of AND circuits G27. , G27□, an OR circuit G29 that ORs the output of this NOR circuit 028 and the output of the exclusive OR circuit G24, and an output of this OR circuit G29 and a NAND circuit. G2
6 and a NAND circuit G30 which generates a second carry output C to the upper digit by performing a logical product with the output of 6.

The operation of the unit adders shown in FIGS. 1 and 2 is expressed by the truth table shown in FIG.
Cs Cout) functions as a unit adder. In addition, in Fig. 3, (S, C
, Cout) is the truth table in Figure 1, and the rightmost set (
S.C.

Cout) is the truth table in FIG.

Moreover, according to the unit adder, four inputs Xo−X,
The number of stages through which the exclusive OR circuit passes from to sum output S is three.

In contrast, as shown in FIG. 9, the conventional full adder F
When a unit adder with 5 inputs and 3 outputs is realized using two stages of A, exclusive OR circuits EOI to EO4, AND circuits A1 to A4, and OR circuits ORI and OR2 are connected as shown in the figure, and inputs X, , The number of stages through which the exclusive OR circuit passes from X to the sum output S is four.

Therefore, in the unit adder of the present invention, the number of passing gate stages is reduced by 3/4 times as compared to the adder shown in FIG. 9, and the processing speed can be increased. Further, in the unit adder of the present invention, the difference between the number of passing gate stages from the four inputs to the sum output and the number of passing gate stages until the carry output is only one stage, and there is almost no time difference between the two outputs. It is possible to increase the speed of an arithmetic circuit using this unit adder. Furthermore, as described above, since there is little difference in the number of pass gate stages, the circuit pattern has excellent symmetry and a compact layout is possible.

FIG. 4 shows a parallel multiplier array constructed by combining the unit adders WAD of the present invention as described above in a binary tree shape, for example, 16 items of 3-bit 2
decimal data (ZOr ”O*Xo) ~(Zl s *
Divide Yt 5 * Xi s ) into 4 groups for every 4 consecutive items, and divide the corresponding bit of each group (Xo
=Xv)~(XI□~X,5), (Yo -Y
3) ~(Yl2~Yl5)
, (Z□ -23) ~ (Zt 2 ~ Zt s ), respectively, in the first layer unit adder 41. There are four inputs: ~4112. Then, the sum output S of the two sets of unit adders in the first layer at a certain digit is calculated by the unit adder 411 in the second layer.
3 * It becomes the input of the unit adder of the same digit among 4115.4117, and the second carry output C of the two sets of unit adders in the first layer becomes the input of the unit adder of the one higher digit. .

Similarly, the sum output S of the remaining two sets of unit adders in the first layer at a certain digit is calculated by the unit adder 4114 in the second layer.
．． The second carry output C of the two sets of unit adders in the first layer becomes an input to the unit adder of the next higher digit. Then, the second layer unit adders 4113 to 411
The sum output S of the two sets of unit adders with the same digit out of 8 becomes the input of the unit adder with the same digit among the unit adders 4119 to 4121 in the third layer, and performs the unit addition in the second layer. The second carry output C of the unit is sent to the unit adder 4119 of the third layer.
It becomes the input of the unit adder of one high-order digit out of 4121.

Further, in each layer, the first carry output Cout of the unit adder of the lower digit becomes the carry input Cin of the corresponding fourth layer unit adder of the higher digit.

Note that the first carry output Cout and the second carry output C may be used interchangeably.

In the parallel multiplier array, unit adders 4119 to 4121 in the third layer correspond to the top layer of the binary tree configuration.
From, the sum output of each corresponding digit 5t-1=3i+l
and carry outputs C1-1 to Ci+1 are obtained.

Figure 5 shows a 32-bit multiplier array in which unit adders are combined in a binary tree as a constituent unit to form a parallel multiplier array as shown in Figure 4, and the second-order Booth algorithm is applied. Showing parallel multipliers. The block configuration of this 32-bit parallel multiplier itself is well known, and as shown in FIG. 4, a maximum of seven unit adders are required for each bit.

Here, 1 is the multiplicand, 2 is the multiplier, and 3 and 4 are data buffers. 6a to 6d and 8a to 8d are selectively controlled by the decoder necessary to apply the second-order Booth algorithm and the output of this decoder. selector, 9
a to 9 d s 12 a % 12b and 15 are adder rows in which a plurality of the unit adders are arranged in the bit width direction, and are connected as a whole to form three layers in a binary tree shape. In this case, the first layer adder arrays 9a to 9d are as follows:
As shown in FIG. 6, only 39 unit adders WAD are arranged, and similarly the second layer adder row 12
As shown in FIG. 6, each of a and 12b is composed of 39 unit adders WAD only, and the adder row 15 in the third layer corresponding to the top layer is as shown in FIG. , only 47 unit adders WAD are arranged, and each of these adder columns 9 a to 9 ds 12 as 12
The pattern layout of b-, 15 is simple. Reference numeral 17 denotes a high-speed two-input adder that calculates the final result, and usually a carry-first-accumulate or carry-selection type adder is used.

In addition, if sign correction is required, this high-speed two-input adder is used.

FIG. 8 shows a 32-bit parallel multiplier in which a parallel multiplier array is constructed by combining unit adders in a binary tree as a constituent unit, as shown in FIG. algorithm is not applied. The block configuration of this 32-bit parallel multiplier itself is well known, and it is necessary to perform addition of a maximum of 32 items for each bit.

Here, 1 is a multiplicand, 2 is a multiplier, 3 and 4 are data buffers, 9a to 9h, 12a to 12d.

15a, 15b, 17 are unit adders WA in the bit width direction.
D is an adder array in which a plurality of adders are arranged, and the adders are connected to form four layers in a binary tree shape as a whole. in this case,
98 to 9h are adder columns of the first layer, 12a to 12d are adder columns of the second layer, 15a and 15b are adder columns of the third layer, and 18 is the fourth layer corresponding to the top layer. is an adder string.

20 is a high speed two-input adder that calculates the final result.

The parallel multipliers shown in FIG. 5 and FIG. Since the array is configured, the number of calculation stages is smaller than that of the conventional class of addition method, which has a full adder FA as its basic structure.In other words, as described above, the present invention shown in FIG. 1 or FIG. If we take the unit adder WAD as the basic configuration,
Compared to the case where the basic configuration is a unit adder in which two stages of full adders FA are connected as shown in Fig. 9, the number of stages passing through the exclusive OR circuit is reduced by 3/4 times (overall, each digit is It has three stages of exclusive OR circuits, making it possible to increase speed. Moreover, the parallel multiplier of the present invention as described above has a highly regular layout pattern, and the layout is simple.
Since the wiring length can be minimized or suppressed and the calculation speed can be increased by reducing the wiring capacitance, it is particularly suitable for large-scale high-speed multipliers of 32 bits or more.

[Effects of the Invention] As described above, according to the parallel multiplier of the present invention, the number of calculation stages is smaller than that of conventional class addition methods, the layout pattern is highly regular, the layout is simplified, and the wiring length can be reduced. This makes it possible to minimize or suppress the wiring capacitance, thereby increasing the speed of calculations, and is particularly suitable for large-scale high-speed multipliers of 32 bits or more.

Further, the unit adder of the present invention is suitable as a high-speed 5-input 3-output adder used as a basic component of the above-mentioned parallel multiplier, for example.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the unit adder of the present invention,
FIG. 2 is a circuit diagram showing another embodiment of the unit adder of the present invention, FIG. 3 is a diagram showing the truth value of the operation of the unit adder of FIGS. 1 and 2, and FIG. 4 is a circuit diagram of the unit adder of the present invention. Figure 5 is a block diagram showing an example of a multiplier array used in a parallel multiplier in Figure 4. FIG. 6 is a block diagram showing an example of the first layer adder column and the second layer adder column in FIG. 5, and FIG. FIG. 8 is a block diagram showing an embodiment of the adder array in the third layer in the figure. FIG. 9, a block diagram showing one embodiment, is a circuit diagram showing a unit adder with five inputs and three outputs using a conventional full adder. xo-x, 4 inputs, G 1 ) ~ G 14, G
2...NAND circuit, G3, G7, G8...Nor circuit, G4. G42...Exclusive OR circuit, G5, G6
・・・Exclusive NOR circuit, carry input for Ci n, Co
u t...first carry output, C...second carry output, S...sum output, G211, G212, G2
9...OR circuit, G22. G26, G30...
NAND circuit, G222...Inverter circuit, G231
, G232, G24, G25...exclusive OR circuit, G
27°G272...AND circuit, 028...NOR circuit, EAD...5 input 3 output unit adder, 1...
Multiplicand, 2... Multiplier, 3.4... Data buffer,
6a to 6d...decoder, 8a to 8d...selector, 9a to 9h...first layer adder column, 12a to 1
2d... Second layer adder column, 15.15a, 15b
... Third layer adder column, 18... Fourth @th adder column, 17.20... Final adder (high-speed 2-input adder). Applicant's agent Patent attorney Takehiko Suzue Figure in Figure Figure 8 Figure 9

Claims (5)

[Claims] (1) four sets of first gate circuits in which three inputs of different combinations of four inputs of a certain digit of a binary number to be added are respectively inputted and the negation of logical product is performed; a second gate circuit that takes the logical product of the respective outputs of the four sets of first gate circuits and generates the first carry output to the upper digit; and a second gate circuit that takes the logical product of the four inputs and generates the first carry output to the upper digit; a third gate circuit; two sets of fourth gate circuits to which two inputs of different combinations of the four inputs are respectively input and take an exclusive OR; A fifth gate circuit which takes the exclusive OR of each output of the fourth gate circuit, and a fifth gate circuit which takes the exclusive OR of the output of this fifth gate circuit and the carry input from the lower digit and sums it. a sixth gate circuit that performs a logical sum negation to generate an output; a seventh gate circuit that performs a logical sum negation between the output of the fifth gate circuit and a carry input from a lower digit; A unit addition characterized by comprising: an eighth gate circuit that generates a second carry output to a higher digit by performing a logical OR of the output of the gate circuit and the output of the third gate circuit; vessel. (2) two sets of first gate circuits in which two inputs of different combinations of four inputs of a certain digit of a binary number to be added are respectively inputted and logically summed; a second gate circuit that ANDs each output of the first gate circuit of the set to generate a first carry output to the upper digit; and two inputs of different combinations of the four inputs. two sets of third gate circuits which take the exclusive ORs of the respective inputs, and a fourth gate circuit which takes the exclusive ORs of the respective outputs of these two sets of third gate circuits; a fifth gate circuit that generates a sum output by performing exclusive OR of the output of the fourth gate circuit and the carry input from the lower digit; and the output of the fourth gate circuit and the carry input from the lower digit. and two sets of seventh gate circuits each receiving a corresponding input of two different combinations of the four inputs and calculating a logical product. , an eighth gate circuit which takes the logical sum of the respective outputs of these two sets of seventh gate circuits; and a logical sum which takes the logical sum of the output of this eighth gate circuit and the output of the fourth gate circuit. a ninth gate circuit; and a tenth gate circuit that generates a second carry output to the upper digit by performing a logical AND operation on the output of the ninth gate circuit and the output of the sixth gate circuit. A unit adder comprising: (3) A parallel multiplier comprising a parallel multiplier array that performs addition in a binary tree form using the unit adder according to claim 1 as a constituent unit. (4) A parallel multiplier comprising a parallel multiplier array that performs addition in a binary tree form using the unit adder according to claim 2 as a constituent unit. (5) A parallel multiplier, characterized in that it is formed by applying a second-order Booth algorithm to the parallel multiplier according to claim 3 or 4.