JP3098648B2 - Multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying two arbitrary data, and more particularly to a multiplier for performing multiplication of a number represented by a binary number by hardware.

[0002]

2. Description of the Related Art In the field of image processing that handles a large amount of image data and the field of information processing using a computer,
Multiplication by multiplying data is an important process. In such fields, data is usually represented in binary, and multiplication also involves multiplying binary data.

FIG. 19 shows an example of multiplication of a 4-bit binary number. An intermediate sum surrounded by a broken line, which only performs the same operation as the decimal arithmetic, is called a partial product. The multiplication result is obtained by adding the partial products for each digit.

FIG. 20 shows a circuit of a conventional parallel multiplier for realizing multiplication of a 4-bit binary number. The multiplier shown in FIG. 20 is generally called a multiplier using a carry-save addition method. Referring to FIG. 20, the multiplier includes a register circuit 201a that holds multiplicand data (value is X),
Register circuit 2 for holding multiplier data (value is Y)
01b, four A's arranged in each of the first to fourth columns
ND gates 271, 232, 233 and 234, multiplicand data line 202a, multiplier data line 202b, data output line 211 for outputting a result of multiplication of multiplicand data and multiplier data, half adder 220, full adders 221 and 222 including. Reference numeral 205 denotes a partial product addition unit. The partial product addition unit 205 includes the AND gate 231 described above.
234, a half adder 220, and full adders 221 and 222 are arranged in an array. Reference numeral 210 denotes a last-stage adder sequence.

In operation, partial products of multiplicand data X and multiplier data Y are the first to fourth columns of AND gates 23.
1 to 234. AND gate 231
Product of the first column obtained by the above and AND gate 232
The sum with the second partial product obtained by
Required by Next, AN is added by full adder 221.
The partial product obtained by the D gate 233 and the half adder 22
The sum of the addition result of 0 (sum output and carry bit) is obtained. Further, the sum of the partial product obtained by the AND gate 234 in the fourth column and the addition result of the full adder 221 is obtained by the full adder 222 in the final stage. Full adder 2
22 supplies the obtained sum output and carry bit to the final-stage adder sequence 210.

As described above, the multiplication shown in FIG. 19 can be performed. FIG. 20 shows an example of a 4-bit multiplier. In the present computer world, data of 54 bits or more is used. Therefore, a multiplication of 54 bits or more is required. In this case, the partial product adder 205 in FIG. 20 becomes very large. When the partial product adder becomes large in scale, each signal is sequentially propagated through each adder, so that the signal delay in the partial product adder becomes extremely large. The number of stages of the adder is proportional to the number of partial products in the multiplication.

The use of Booth's algorithm can reduce the number of partial products. As an example, consider a 54-bit multiplication. In the normal multiplication, there are 54 partial products, but when the second-order Booth algorithm is used, the number of partial products is 27. Therefore, the operation time required for the multiplication can be reduced.

However, even when a secondary booth is applied, there is a signal delay of 25 stages in the adder in the carry-save addition type partial product adder.

Therefore, in order to further reduce the operation time, the configuration of the partial product addition unit is devised. FIG. 21 shows a two-parallel carry-save addition method that has been devised as described above.
Referring to FIG. 21, the two-parallel carry-save addition method is as follows.
Carry save addition is performed on every other generated partial product. That is, two carry-save additions are performed in parallel for one digit of the partial product. As a result,
It is 2 in 1/2 of the adder passing by carry save addition method
A total of four bits can be generated bit by bit. These four bits are output as two bits using two stages of carry save addition (not shown).

In this way, when the secondary booth is used for the 54-bit multiplication and the two-parallel carry-save addition method is applied, the number of stages of full adders to be passed is 12 + 2 = 14.
It becomes a step.

The hardware layout in the two-parallel carry-save addition method has a regularity and a small area because the full adders are arranged in an array.

In addition to the secondary booth and the two-parallel carry-save addition method, there is a Wallace method as a method of reducing the number of stages of partial products. The Wallace method is a method of reducing the number of stages of addition by arranging full adders at each digit in a tree shape.

In FIG. 22, 6-2 compresses 6 inputs into 2 outputs.
Here is an example of Wallace. Also shows the number of stages required to squeeze N input to two outputs in FIG 4.

Referring to FIG. 22, the 6-2 Wallace system is as follows.
A 6-2 Wallace circuit is arranged at each digit of the partial product. 6 each
-2 Wallace circuit is a full adder 24 arranged in the first stage.
1a and 241b, full adder 2 arranged in the second stage
42, and a full adder 243 arranged in the third stage.

In operation, the first stage full adder 241
a generates a sum output and a carry bit by adding 3-bit data, and outputs the sum output to the full adder 24 at the second stage.
2 and the carry bit is incremented by 1
Give to 42. The full adder 241b adds the 3-bit data to generate a sum output and a carry bit, provides the sum output to the full adder 242 in the second stage, and adds the carry bit to the next higher digit. To the container 243.

The full adder 242 in the second stage is a full adder 2
The sum outputs from 41a and 241b and the carry bit from the next lower digit are added, the sum is given to the full adder 243 of the third stage, and the carry bit is added to the full adder 243 of the next higher digit. Give to. Third stage full adder 2
43 adds the sum output from the full adder 242 and the carry bit from the next lower digit to generate a sum output and a carry bit. In this manner, in the 6-2 Wallace system, the sum of the six partial products can be obtained by the three-stage full adder, so that the signal delay can be reduced.

When the Wallace method is used for all of the partial products, the number of stages can be further reduced. The one that applies Wallace to all of the partial products is called Full Wallace. 54
A material obtained by applying the Furuwaresu when using secondary Booth to the multiplication of the bit shown in FIG. 2 3. Number of full adder signal goes through as shown in FIG. 2. 3 requires only seven stages. However, there is a problem with the layout. 1 digit Placing adder in the form of a leave of the tree-shaped as shown in FIG. 2 3 increases the area becomes the layout of the triangle.

In order to obtain a rectangular layout,
If the digit adders are arranged vertically, the wiring becomes complicated and long. In addition, since the partial product number increases in order from the lowest digit, reaches the maximum in the center, and then decreases again, it is necessary to make various input wallaces.

In the Wallace method, the effect of increasing the speed increases as the number of inputs increases, but at the same time, the degree of the above-mentioned problems increases.

[0020]

As described above, the conventional parallel multiplier has the following problems.

(1) Multipliers of the two-parallel carry-save addition method have a large number of adders and lack high-speed performance.

(2) A full wallet has a complicated layout of an adder, a long wiring length, and a large area.

Therefore, an object of the present invention is to provide a multiplier for multiplying two arbitrary data, which can execute multiplication at high speed and reduce the layout area.

[0024]

[0025]

[0026]

Multiplier according to this invention, in order to solve the above-mentioned object, the partial product for adding the generated generated partial product to a partial product using the secondary Booth scheme for two arbitrary data Includes adder. The partial product adder includes first to fifth
And first to third adding means. The first to fourth compression means are provided corresponding to the respective digits of the partial product, and each compresses the data of 6 bits into two bits composed of a sum output and a carry bit using the Wallace method.
The first addition means adds the sum output of the first to third compression means and the carry bit from the lower digit by using a two-parallel carry-save addition method to generate a sum output and a carry bit. The second addition means adds the sum output of the fourth compression means, the sum output of the first addition means, and the carry bit from the lower digit using a two-parallel carry-save addition method. The third addition means adds the remaining bits of the one-digit data of the partial product using the carry-save addition method. The fifth compression means compresses the 6-bit data consisting of the addition result of the second addition means, the addition result of the third addition means, and the carry bit from the lower digit into two bits using the Wallace method.

Preferably, the first to fifth compression means
Stage, the first to third adding means, from the top,
Means, second compression means, third compression means, first adder
Stage, fourth compression means, second addition means, third addition means
The stages are arranged in the order of the fifth compression means.

[0028]

[Action] In this invention, it is possible to perform a high speed multiplication compared by providing at least five compression means, and for adding the parallel carry save addition method for all partial products. Further, the wiring can be simplified and the area can be reduced as compared with the case where all partial products are multiplied by the full Wallace method. Further, the wiring can be prevented from becoming complicated by compressing the compression result of the compression means by the two-parallel carry-save addition method. Therefore, the length of the wiring is also reduced, and the signal delay due to the wiring can be reduced.
As a result, the multiplication can be executed at substantially the same speed as that of the full Wallace method.

[0029] Preferably, the partial product adder includes, in order from the top, a first compression means, a second compression means, a third compression means, a first addition means, a fourth compression means, and a second addition means. Since the layout is made up of the means, the third adding means, and the fifth compressing means, the wiring can be simplified and the area can be significantly reduced as compared with the full wallless system. Further, the multiplication speed can be greatly reduced as compared with the case where addition is performed on all partial products by the two-parallel carry-save addition method. Further, since the wiring length can be reduced, the multiplication can be performed at a speed similar to that of the full Wallace method.

[0030]

[0031]

【Example】

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 1 is a block diagram showing a schematic configuration of a multiplier according to the present invention. Referring to FIG. 4, this multiplier includes a register circuit 41a for holding multiplicand data X, a register circuit 41b for holding multiplier data Y, a multiplicand data line 42a, a multiplier data line 42b, and a secondary booth decoding circuit 43. ,
Booth decode result output line 44, partial product adder 4
5, output line 46 of partial product adder 45, last adder column 4
7, an output line 48 for outputting a multiplication result obtained by multiplying the multiplicand data X and the multiplier data Y.

The partial product adder 45 includes a row of a secondary booth selection circuit and a row of adders. In FIG. 4, the register circuit 41 and the full adder may be exactly the same as the conventional one, and there are many realizing methods, and any realizing method does not affect the present invention. It is not described in detail here, nor is it necessary. The last-stage adder array 47 is a circuit for adding two data, and a similar realization method is not described in detail.

FIG. 5 is a diagram for explaining the algorithm of the booth decoding circuit 43, and FIG. 6 is a diagram showing the selection of the booth decoding circuit 43 and the booth arranged in the partial product adder 45 shown in FIG. FIG. 2 is a block diagram of the circuit and the operation view.

Referring to FIGS. 5 and 6, the second-order Booth algorithm generates a partial product for a multiplier of 2 bits. However, strictly speaking, since one bit overlaps, it is necessary to generate partial products of 0, ± X, ± 2X as shown in FIG. 5 corresponding to the values of three consecutive bits of the multiplier Y. The generation of 2X is performed by one bit shift. On the other hand, since the generation of the negative number is represented by the two's complement of the multiplicand X, X
, And add 1 to the least significant bit. In order to realize this, as shown in FIG. 6, in the Booth decoder, the absolute value of the partial product (0,
X, 2X) and one signal for selecting inversion are generated.
The booth selection circuit 45a receives these three signals, and when the absolute value is 0, 0, and when the absolute value is X, the multiplicand X
_{If k} is 2X, the multiplicand X _k-1 is selected, and if inversion is required, its value is inverted to generate a partial product.

FIG. 1 is a block diagram of the partial product adder 45 shown in FIG. Referring to FIG. 1, partial product addition section 45 includes 6-2 Wallace sections 1, 2, 3, 4, and 8 for compressing 6-bit data into 2-bit data, and 6-bit data in parallel. Carry-save adders (hereinafter referred to as parallel CSA) 5 and 6 for generating 4-bit data and carry-save adders (hereinafter referred to as "parallel CSA") for adding 2-bit data by adding 3-bit data. , C
SA) 7).

As shown in FIG. 1, the partial product adder 45 has a 6-2 Wallace section 1 → 6-2 Wallace section 2 → 6-2.
Wallace part 3 → Parallel CSA5 → 6-2 Wallace part 4 → Parallel C
SA6 → CSA7 → 6-2 Wallace unit 8 are arranged in this order. Hereinafter, the vertical direction in FIG. 1 is referred to as a vertical direction, and the horizontal direction is referred to as a horizontal direction unless otherwise specified.

The 6-2 Wallace sections 1 to 4 include a row of booth selection circuits and a row of 6-2 Wallace addition circuits. 6-
The 2-Wallace unit 8 includes a row of 6-2 Wallace addition circuits and does not include a row of booth selection circuits. The CSA 7 includes a row of booth selection circuits and a row of full adders.

Next, the schematic operation of the partial product adder 45 shown in FIG. 1 will be described. Each of the 6-2 Wallace units 1 to 4 processes 6 stages of the 27-stage partial product and compresses one digit into 2-bit data. That is, one digit of the partial product of 24 stages is compressed to a total of 8 bits by the entire 6-2 Wallace sections 1 to 4. Parallel CSA5 is
6-2 The 6-bit data compressed by the Wallace sections 1 to 3 are added to generate 4-bit data for one digit.
Give to SA6. The parallel CSA 6 adds the 2-bit data from the 6-2 Wallace section 4 and the 4-bit data from the parallel CSA 5 to generate 4-bit data for one digit, and supplies the data to the 6-2 Wallace section 8. The CSA 5 performs addition of the partial products of the remaining three stages processed by the 6-2 Wallace units 1 to 4 of the 27-stage partial products, and generates 2-bit data for one digit to generate 6-2. Give to Wallace part 8. 6-2 Wallace section 8 includes parallel CSA and CSA7.
Is compressed into 2-bit data and applied to the final adder sequence 47 (FIG. 4).

As described above, the addition can be performed for the 27-stage partial products. FIG. 2 is a block diagram showing details of two digits of the partial product adder shown in FIG.

Referring to FIG. 2, one digit of partial product adder 45 has 6-2 Wallaces 1a, 2a, 3a, 4a and 8a each comprising a row of Booth selection circuits and a 6-2 Wallace addition circuit. And full adders 5a, 5b, 6a and 6b and full adder 7a.

6-2 Wallaces 1a, 2a and 3a are connected to full adder 5 through output lines 9a, 9b and 9c, respectively.
a and 5b. 6-2 Wallace 4a
It is connected to full adder 6b via output line 9d. Full adders 5a and 5b are connected to full adders 6a and 6b via output line 10 . Full adders 6a and 6b are connected to 6-2 Wallace 8a via output line 11. The full adder 7a is connected via an output line 12 to the 6-2 Wallace 8a. The 6-2 wallace 8a is connected to the last adder column via the output line 13.

In operation, 6-2 Wallaces 1a through 3
a compresses 6-bit data into 2 bits each consisting of a sum output and a carry bit, and outputs the sum output to an output line 9;
a through 9c to full adders 5a and 5b,
The carry bit is provided to the full adder of the next higher digit. Also, 6-2 Wallace 4 a gives a sum output via the output line 9d to the full adder of one higher digit the carry bit applied to full adder 6b. Full adder 5a is 6-2 Wallace 1a
And the two sum outputs from 2a and the carry bit from the lower digit to generate a sum output and a carry bit, and sum the sum output via output line 10 to full adder 6
a, and the carry bit to the full adder of the upper digit. The full adder 5b adds the sum output of the 6-2 wallace 3a and the carry bit of the lower digit, and outputs the sum output to the output line 1.
The carry bit is supplied to the full adder 6b via 0, and the carry bit is supplied to the full adder of the upper digit. The full adder 6a includes the full adder 5
a and the carry bit from the lower digit are added to generate a sum output and a carry bit, and the sum output is given to the 6-2 Wallace 8a via the output line 11, and the carry bit is added to the upper digit. 6-2 Wallace 8a. Full adder 6b adds the sum output of full adder 5b, the carry bit from the lower digit, and the sum output of 6-2 Wallace 4a , and outputs the sum output via output line 11 to 6-2 Wallace 8a.
And the carry bit is set to the upper digit 6-2 Wallace 8a.
Give to. The full adder 7a has a partial product of three stages, ie, 3
Bit data is added, a sum output is given to 6-2 wallace 8a via output line 12, and the carry bit is set to the upper 6 digits.
-2 Give to Wallace. 6-2 Wallace 8a is a full adder 6
The two sum outputs from a and 6b, the sum output from the full adder 7a and the carry bit from the lower digit are added to generate a sum output and a carry bit. The sum output and the carry bit generated by the 6-2 Wallace 8a are supplied to the final-stage adder array via the output line 13.

FIG. 3 is a block diagram showing the details of one of the 6-2 Wallaces 1 to 4 shown in FIG. 2. A block surrounded by a thick line constitutes one digit of the 6-2 Wallace.

[0044] With reference to FIG. 3, 6-2 order of magnitude of Wallace, the selection circuit 31,32,33,3 5 Diagrams, 3
6 and 37, and full adders 34b, 38b, 39b and 40b. Booth selection circuits 31, 32, 3
3 is connected to the full adder 34b via output lines 31p, 32p, and 33p, respectively, and the booth selection circuits 35, 3
6, 37 are connected to the full adder 38b via output lines 35p, 36p, 37p, respectively. Full adder 34b
Indicates that the sum output of the full adder 3 is output via the output line 34bs.
9b, the sum output of the full adder 38b is connected to the full adder 39b via the output line 38bs. The sum output of the full adder 39b is connected to the full adder 40b via the output line 39bs. The full adder 40b has its sum output connected to the parallel CSA 5 (FIG. 1) via the output line 40bs.

Next, the operation of the 6-2 Wallace shown in FIG. 3 will be described. The booth selection circuits 31 to 33 generate partial products in response to the decode signal from the booth decode circuit 43 (FIG. 1), and supply the partial products to the full adders 34b via the output lines 31p to 33p. Booth selection circuit 3
5 to 37 are the booth selection circuits 31 to 33
A partial product is generated in the same manner as
The signal is supplied to the full adder 38b via p. Full adder 34b
Adds the three-stage partial products from the booth selection circuits 31 to 33, generates a sum output and a carry bit, gives the sum output to the full adder 39b, and outputs one carry bit via the output line 34bc. This is given to the full adder 39c of the upper digit. The full adder 38b includes the booth selection circuits 35 to 3
The partial products of three stages from 7 are added to generate a sum output and a carry bit, and the sum output is given to the full adder 39b and the carry bit is given to 40c. The full adder 39b outputs the sum output from the full adder 38b and the full adder 3 of the next lower digit.
4 Sam from the carry bit and the full adder 34b from a
The sum output produced by adding the output via an output line 39bs full adder carry bit applied to 40b through the carry bit output line 39bc next higher digit full adder 4
0c. The full adder 40b adds a sum output of the full adder 39b, a carry bit from the next lower adder 39a, and a carry bit from the next lower adder 38a to generate a sum output generated by the parallel CSA5 (FIG. 1). Give to).

Next, the signal delay of the partial product adder shown in FIGS. 1 to 3 will be described. In the 6-2 Wallace shown in FIG. 3, the full adder 34b or 38b and the full adder are used after the partial products are generated by the booth selection circuits 31 to 33 and 35 to 37 until 27 partial products are obtained. Passes through three stages of full adders, each of which comprises an adder 39b and a full adder 40b. As described with reference to FIGS. 1 and 2, the 6 bits output from 6-2 Wallaces 1a to 3b are input to full adders 5a and 5b, and the 4 bits output from full adders 5a and 5b and 6-2
Two bits output from Wallace 4a are input to full adders 6a and 6b. 4 bits of the outputs of the full adders 6a and 6b and 2 bits of the output of the full adder 7a are input to the 6-2 Wallace 8a, and the output is supplied to the partial product adder 45 (FIG. 4).

Therefore, the delay time from the generation of the partial product to the output of the operation result of the partial product adder is 3 (6-2 Wallace 1) with the delay time of one stage of the full adder as one unit. 4) +2 (parallel CSA 5 and 6) +3 (6-2 Wallace 8) = 8 stages.

The time required for the partial product addition of the present invention is compared with that of the conventional example. If the delay time for one stage of the full adder is shown as one unit, the two parallel CSAs are 14 stages, and the full wallace is 7 stages.
6-2 Wallace + parallel CSA is 8 stages. Therefore, the system according to the present invention can achieve a sufficiently high speed with respect to the two-parallel CSA system, and has only one stage delay with respect to the full-wallless system.

The congestion degree, the alternative wiring length, and the area of the wiring of the present invention are compared with those of the conventional example. In the 6-2 Wallace + parallel CSA, the most crowded wiring is on the booth selection circuit in the 6-2 Wallaces 3 and 4. It ’s 6-2 Wallace 3.
This is because, in addition to the wiring in the 6-2 Wallace, four output lines of the 6-2 Wallace 1 and 2 pass, and in the 6-2 Wallace 4, four output lines of the CSA 5 pass.

FIG. 7 is a wiring diagram of the 6-2 Wallace shown in FIG. Referring to FIG. 7, the output signal lines of the operation results on 6-2 Wallaces 2 to 4 are stepped as shown in the figure. The most congested wiring is the wiring on the selection circuit (52 in FIG. 7) of the booth on 6-2 Wallace 3.

FIG. 8 shows the booth selection circuit 52 shown in FIG.
FIG. The horizontal wiring includes three signal lines 61 from the booth decoder 43 (FIG. 4) and a partial product signal line 62 generated by the booth selection circuit 52.
(1), output signal line 6 from 6-2 Wallace 1 and 2
3 (four), output signal lines 64 (two) of the full adder inside the 6-2 Wallace 3, and multiplicand data lines 65 (two), and a total of twelve wirings pass through.

In the vertical direction, there are two digit output signal lines 66 (two lines) from 6-2 Wallaces 1 and 2 and output signal lines 67 (two lines) of the full adder inside 6-2 Wallace 3. , (4+
2) × 2 = 12. There are also generated partial product signal lines 68 (three) and multiplicand data lines 69 (two). Therefore, a total of 17 wires pass. This is because the multiplicand data line 65 in the horizontal direction needs to shift the multiplicand data input in the vertical direction in the horizontal direction in the shift instruction from the booth decode circuit 43 in the horizontal direction.

The wiring on the full adder 51 or 53 shown in FIG. 7 has two horizontal output signal lines from 6-2 Wallaces 1 and 2 and two output signal lines from the full adder inside 6-2 Wallace 3. There are 12 digits. The vertical direction is 13 lines including the 12 lines and one multiplicand data line.

The following assumptions were made to calculate the wiring length and area. 1. The design rule is that horizontal wiring is 3 aluminum, pitch is 3.0 μm, vertical wiring is 2 aluminum, pitch is 5.
0 μm. Note that 3 aluminum means the third layer on the semiconductor, and 2 aluminum means the second layer.

2. Transistor density of 15000Tr /
mm ² . Since the full adder is 24Tr, its area is 24 × 100000/15000 = 1600 μm ² and its size is assumed to be 40 μm × 40 μm. It is assumed that the booth selection circuit is also 20Tr and has the same size as the full adder.

Based on the above assumptions, the size of the booth selection circuit and the size of the full adder are calculated. About 6-2 Wallace 3
The wiring size on the booth selection circuit is as follows: vertical; 12 (lines) × 5.0 (μm) = 60 μm horizontal; 17 (lines) × 3.0 (μm) = 51 μm Full adder (51 in FIG. 7) 53) The wiring size on the top is: vertical; 12 (lines) × 5.0 (μm) = 60 μm; horizontal; 13 (lines) × 3.0 (μm) = 39 μm.

The Booth's selection circuit and full adder are basic circuits that constitute a partial product adder, and are called basic cells. The width of the basic cell is determined by the largest part of the path through which one digit passes. The largest width is 6-
It is a booth selection circuit of 2 walls 3 and its length is 51μ
m. Therefore, the width of both the booth selection circuit and the full adder is 51 μm.

On the other hand, the vertical length of the basic cell differs depending on the location. In the 6-2 Wallace 3, as described above, the booth selection circuit is 60 μm, and the full adder is 51, 5 in FIG.
3 is 60 μm, and the full adders 54 and 55 in FIG. 7 are 40 μm because there is no horizontal wiring.

The 6-2 Wallace 2 has a smaller number of wirings than the 6-2 Wallace 3 by two, so that the wiring on the selection circuit of the booth has 10 (lines) × 5.0 (μm) = 50 μm. The total number of adders is 8 (lines) × 5.0 (μm) = 40 μm.
The lengths of the 6-2 wallets 1, 4, the booth selection circuit and the full adder of the CSA 7 are also 40 μm.

The area of the partial product adder is calculated based on the size of each basic cell. FIG. 9 shows an outline of a layout of a partial product adder to which the present invention is applied.

Since the width of the basic cell is 51 μm, 51 (μm) × (54 + 27) (bits) = 41
It becomes 31 μm.

Vertically, 6-2 Wallaces 1 and 2 are 50 μm × 6 (booth selection circuit) +40 μm × 4 (full adder) = 460 μm 6-2 Wallaces 3 and 4 are 60 μm × 6 (booth selection circuit) +60 μm × 2 (full adders 34 and 38) +40 μm × 2 (full adders 39 and 4
0) = 560 μm Parallel CSA5 and 6 are 40 μm × 2 (full adder) = 80 μm CSA7 is 60 μm × 3 (booth selection circuit) + 60 × 1 (full adder) = 240 μm 6-2 Wallace 8 is 40 × 4 ( Full adder) = 160 μm, and when all are added, 460 × 2 + 560 × 2
+ 80 × 2 + 240 + 160 = 2 600 μm.

Therefore, the area is 4131 (width) × 2
600 (vertical) = 10,740,600 μm ² .

The maximum wiring length which is the longest among the wirings connecting the basic cells is calculated. The longest wiring is 6-
It is a wiring connecting the operation result of 2 Wallace 1 and the full adder of the parallel CSA 5, and the length is 460 (6-2 Wallace 2) +560 (6-2 Wallace 3) = 1020 μm Width: 51 × 6 × 2 (6-2 Wallace 2 and 3) = 612 μm Therefore, the maximum wiring length is 1020 + 612 = 1,632 μm
m.

Next, calculation is performed for the two-parallel CSA of the conventional example. FIG. 10 shows a part (partial products 1 to 9) of a two-parallel CSA
FIG. 3 is a diagram showing an outline of a layout. The wiring is most crowded on the selection circuit 96B of the booth in FIG. FIG.
1 shows wiring on the selection circuit 96b of the booth.

The horizontal wiring on the booth selection circuit 96B is connected to the signal line (3
), The generated partial product signal line 62 (one), the full adder 9
1f, output signal lines (2), multiplicand data lines (2
) And a total of eight wires pass through.

In the vertical direction, the generated partial product signal line 68
(Three), multiplicand data lines (two), and output lines (two) of full adders 91a and 91g correspond to two digits, that is, 2 × 2 = 4.
There are a total of nine wirings.

On the other hand, in the full adder, the multiplicand data line (one) and the output signal line (two) of the full adder correspond to two digits, that is, four lines in the vertical direction, and the wiring of five diameters passes. There is no horizontal wiring.

Therefore, the size occupied by the wiring on the basic cell is as follows: vertical (8) × 5.0 (μm) = 40 μm horizontal; 9 (line) × 3.0 (μm) = 27 μm With the wiring on the full adder, vertical; 0 (lines); horizontal; 5 (lines) × 3.0 (μm) = 15 μm, which fits in the basic cell.

Therefore, in all places of the partial product addition section, both the full adder and the booth selection circuit have a vertical length of 40 μm.
m, 40 μm in width.

The area of the partial product adder is calculated based on the size of the basic cell. The width of the basic cell is 40 μm.
Therefore, 40 (μm) × 81 (bits) = 3240
μm.

In the vertical direction, 40 (μm) × 27 (booth selection circuit) +40 μm × 25 (full adder) = 2040 μm.

The area is 3240 (width) × 2040 (length)
= 6,609,600 μm ² .

The longest wiring is the full adder 91F shown in FIG.
And 40 × 4 (booth selection circuit) + 40 × 1 (full adder) = 200 μm width; 40 × 2 = 80 μm The wiring length is 200 + 80 = 280 μm.

Calculation is also made for Wallace of the conventional example. FIG.
2 is a diagram showing a configuration of one digit of Full Wallace.

In the full wallace, the most crowded wiring is on the booth selection circuit 128 in FIG. The wiring on the booth selection circuit 128 is shown in FIG.

Referring to FIG. 13, the signal of the result of the full Wallace operation is transmitted through a grid-like wiring. In the vertical direction, 18 output signal lines for the nine full adders (121 in FIG. 23) of the first stage of the adder which are logically tree-shaped, the generated partial product signal lines (three), Multiplicand data line (2 lines)
And a total of 23 wires pass through. Booth selection circuit 12
In the horizontal wiring on the line 8, eight output signal lines pass through the three booth selection circuits, so that six lines are generated for each one, and the signal lines (three) from the decoding circuit 43 of the booth are generated. There are a partial product signal line (one) and a multiplicand data line (two), and a total of twelve wires pass through.

Next, the full adder will be described. There is no horizontal wiring on the full adder. In the vertical direction, the multiplicand data lines (two lines) and the output signal lines of the full adder (18 lines), a total of 2 lines
Zero wiring passes.

The size of the wiring on the selection circuit of the booth is as follows: vertical; 12 (lines) × 5.0 (μm) = 60 μm horizontal; 23 (lines) × 3.0 (μm) = 69 μm The size of the wiring is as follows: vertical; 0 (lines); horizontal; 20 (lines) × 3.0 (μm) = 60 μm.

Accordingly, the booth selection circuit 128 is 60 μm long and 69 μm wide, and the full adder is 40 μm long and 69 wide.
μm.

When the area of the partial product adder is calculated based on the size of the basic cell, the width of the basic cell is 69 μm.
m, 69 μm × 81 (bits) = 5589 μ
m.

The width is 60 μm × 27 (booth selection circuit) +40 μm × 25 (full adder) = 2620 μm, and the area is 5589 (width) × 2620 (length) = 14.6.
43,180 μm ² .

The longest wiring is the full adder 121F shown in FIG.
The length is vertical; (60 (booth selection circuit) × 3 + 40 (full adder)) × 8 = 1760 μm Width: 69 × 3 × 8 = 1656 μm The wiring length is 1760 + 1656 = 3416μ
m.

FIG. 14 summarizes the above comparisons. As for the area, the partial product adder according to the present invention is sufficiently small, that is, 0.73 times that in the case of using Full Wallace.

As for the high speed, the signal generation delay of the partial product adder of the present invention is faster by six full adders than in the case where the two parallel CSA is applied. Therefore, a sufficiently high speed can be achieved. Also, there is only a delay of one stage compared to the case where Full Wallace is applied. However, this delay is a logical count of the number of full adders on the data path, and does not take into account the delay due to wiring. In the maximum wiring length, Full Wallace is longer than 1784 μm, and the difference between the method according to the present invention and Full Wallace is further reduced in consideration of the delay due to the wiring capacitance. In the future, as the LSI process becomes finer, the gate capacitance and the junction capacitance will decrease, and the delay of the full adder will decrease, whereas the wiring capacitance will not decrease so much and the delay due to the wiring will not decrease much. Therefore, there is a possibility that the partial product adder according to the present invention is faster than the case where Full Wallace is applied.

Embodiment 2 FIG. 15 is a block diagram showing another embodiment of the multiplier according to the present invention. Referring to FIG. 15, the multiplier includes a 3-parallel carry-save adder 301 and a 6-2 Wallace 302.

In operation, when a second order booth is applied to a 54-bit multiplication, a maximum of 27 partial products are generated per digit. When carry save addition is performed by skipping three of these using a full adder, the total adder passes through seven stages, and
Compressed into partial products. These are 6-2 Wallace 302
And the output becomes the output of the partial product adder.

The delay time from the generation of the partial product to the output of the operation result of the partial product adder is 7 (3-parallel CSA 301) +7 in units of the delay time of one stage of the full adder.
3 (6-2 Wallace 302) = 10 stages.

The congestion degree of the wiring according to the present invention is determined by the maximum wiring length,
The area is compared with the conventional example. FIG. 16 is a diagram showing an outline of a layout of the three parallel carry save adder 301.
The partial products 1, 2, and 3 are added to the full adder 161Fa,
5 and 6 are input to the full adder 161Fb, and the partial products 7, 8, and 9 are input to the full adder 161Fc. Booth selection circuit 167
B, 168B and 169B have full adders 161Fa and 16
Four 1 Fb output signal lines pass. This wiring has a step-like shape similar to the 6-2 Wallace + parallel CSA system shown in FIG.

The horizontal wirings are signal lines (three) from the booth decoder 43, generated partial product signal lines (one), and output signal lines (4) from the full adders 161Fa and 161Fb.
Book) and a multiplicand data line (two), and a total of 10 wires pass through.

In the vertical direction, full adders 161Fa and 161F
The number of output signal lines (4) of b corresponds to two digits, that is, 4 × 2 = 8, and the generated partial product signal lines (3) and multiplicand data lines (2) total 13 wirings.

In the wiring on the full adder 161Fc, there are eight output signal lines for two digits in the horizontal direction from the full adders 161Fa and 161Fb. The vertical direction is nine lines including the eight lines and one multiplicand data line.

From the partial products 10 to 27, each partial product becomes an input of the full adder and an output of the full adder skips two full adders and becomes an input of the third full adder.

FIG. 17 is a block diagram of the full adder 16 shown in FIG.
FIG. 3 is a detailed wiring diagram of a circuit below 1Fc. Referring to FIG. 17, the horizontal wiring on the booth selection circuit includes three signal lines from booth decode circuit 43 and two multiplicand data lines, and a total of five wirings pass through.

In the vertical direction, the output signal lines (six lines) of the three full adder columns at the preceding stage correspond to two digits, that is, 6 × 2 = 12 lines, and the multiplicand data lines (two lines) total 14 lines. Pass.

The wiring on the full adder is 3
Six output signal lines from one full adder array pass. In the vertical direction, there are a total of thirteen wirings, i.e., twelve output signal lines for two digits and two multiplicand data lines for the preceding three full adder columns.

The size of the booth selection circuit and the full adder are calculated based on the number of wirings described with reference to FIGS. Assuming the same conditions as in the first embodiment for the pitch of the aluminum wiring and the like.

The size of the wiring on the booth selection circuits 161B to 169B is as follows: vertical; 10 (lines) × 5.0 (μm) = 50 μm horizontal; 13 (lines) × 3.0 (μm) = 39 μm The size of the wiring on the devices 161Fa, 161Fb, and 161Fc is as follows: vertical; 8 (lines) × 5.0 (μm) = 40 μm; horizontal; 9 (lines) × 3.0 (μm) = 27 μm. The wiring size on the selection circuit of the booth to be generated is as follows: vertical; 5 (lines) × 5.0 (μm) = 25 μm horizontal; 14 (lines) × 3.0 (μm) = 42 μm Input partial products 10 to 17 The size of the wiring on the full adder is as follows: vertical; 6 (lines) × 5.0 (μm) = 30 μm; horizontal; 13 (lines) × 3.0 (μm) = 39 μm.

Therefore, the width of the basic cell is 42 μm. All adders have a vertical length of 40μ
m, the booth selection circuit for generating the partial products 1 to 9 is 50 μm.
m, the selection circuit of the booth that generates the partial products 10 to 27 is 4
0 μm.

The area of the partial product adder is calculated based on the size of the basic cell. The width of the basic cell is 42 μm.
Therefore, 42 (μm) × (54 + 27) (bits)
= 3402 μm.

In the vertical direction, 50 μm × 9 (booth selection circuit) +40 μm × 3 (full adder) = 570 μm for partial products 1 to 9 and 40 μm × 18 (booth selection circuit) for partial products 10 to 27 +40 μm × 18 (full adder) = 1440 μm 6-2 Wallace 302 becomes 40 × 4 (full adder) = 160
μm, and when all are added up, 570 + 144
0 + 160 = 2170 μm.

Therefore, the area is 3402 (width) × 2
170 (vertical) = 7,382,340 μm ² .

The longest wiring is the full adder 1 shown in FIG.
61Fa is a wiring connecting the operation result of 61Fa and the full adder 162Fa, and the length is vertical; (50 × 3 (booth selection circuit) +40 (full adder)) + 40 = 420 μm horizontal; 42 × 3 × 2 = 252 μm. Therefore, the maximum wiring length is 420 + 252 = 67.
2 μm.

FIG. 18 summarizes the above comparisons. Regarding the high speed, the signal delay of the partial product adder of the present invention is smaller than that of the case where the two parallel CSA is applied.
Higher speed can be achieved faster by a step. Further, the area of the partial product adder according to the present invention is 0.5 times that in the case of using Full Wallace, and is sufficiently smaller than 1.12 times that in the case of using two parallel CSA.

[0105]

By the this invention as described above, according to the present invention lever, it is possible to perform a multiplication in Furuwaresu manner comparable speed, it is possible to obtain a multiplier which can reduce the area.

[0106]

[Brief description of the drawings]

FIG. 1 is a block diagram of a partial product adder showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed diagram of two digits of the partial product adder shown in FIG. 1;

FIG. 3 is a block diagram showing details of one of the 6-2 Wallaces shown in FIG. 1;

FIG. 4 is a block diagram showing a configuration of an entire multiplier according to the present invention.

FIG. 5 is a diagram for explaining an algorithm of the booth decoding circuit 43 shown in FIG. 4;

6 is a block diagram of the booth decoding circuit and the booth selection circuit arranged in the partial product adder shown in FIG. 4 as viewed from the operation side.

FIG. 7 is a wiring diagram in 6-2 Wallace 3 shown in FIG. 1;

FIG. 8 is a detailed wiring diagram of a selection circuit of the booth shown in FIG. 7;

FIG. 9 is an overall schematic diagram of a layout of a partial product adder shown in FIG. 1;

FIG. 10 is a partial layout diagram of a two-parallel carry-save addition method.

11 is a detailed wiring diagram of a part of the two-parallel carry-save addition method shown in FIG. 10;

FIG. 12 is a layout diagram of one digit of the full wallet system.

FIG. 13 is a detailed wiring diagram in a full wallet system.

FIG. 14 is a diagram showing a comparison between the first embodiment of the present invention and a conventional example.

FIG. 15 is a block diagram showing another embodiment of the present invention.

16 is a layout diagram of a part of the partial product adder shown in FIG.

FIG. 17 is a detailed wiring diagram of a part of the partial product adder shown in FIG. 16;

FIG. 18 is a diagram showing a comparison between the second embodiment of the present invention, the first embodiment, and a conventional example.

FIG. 19 is a diagram illustrating an example of multiplication of a 4-bit binary number.

FIG. 20 is a block diagram showing a configuration of a conventional 4-bit multiplier.

FIG. 21 is a conceptual diagram of a two-parallel carry-save addition method.

FIG. 22 is a block diagram of 6-2 Wallace, which is an example of the Wallace method.

FIG. 23 is a logical configuration diagram of a 27-input full wallet.

FIG. 24 is a diagram showing the number of inputs and the number of delay stages in the Wallace method.

[Explanation of symbols]

 1-3 6-2 Wallace section 5, 6 Parallel carry save adder 7 Carry save adder

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F ^7/ 38-7/54

Claims (2)

(57) [Claims] 1. A multiplier that multiplies two arbitrary data as multiplier data and multiplicand data, and generates a partial product of the two arbitrary data using a secondary booth. The partial product addition means is provided in correspondence with each digit of the partial product, and each outputs 6-bit data using a Wallace method with a sum output and a carry bit. First, second, third and fourth compression means for compressing into two bits consisting of: a sum output of the first to third compression means and a carry bit from a lower-order digit in two parallel carry-save addition schemes First adding means for generating a sum output and a carry bit by using the following formulas: a sum output of the fourth compression means, a sum output of the first adding means, and a carry bit from a lower digit. Two average Second adding means for adding using a carry-save addition method; third adding means for adding the remaining bits of the one-digit data of the partial product using a carry-save addition method; multiplication and fifth compressing means for compressing the carry bit to 2 bits using the Wallace method of adding means adding results from the addition result and lower digit of the third addition means, characterized in that it comprises for vessel. 2. A pre-Symbol first to fifth compression means, said first to third addition means, the first compression means from above, the second compression means, the third compression means, the first Addition means, fourth
Compression means, second adding means, a third addition means, claim characterized in that it is arranged in order of the fifth compression means 1
The multiplier according to 1.