JPS6267459A - Speed detection circuit using multipolar resolver - Google Patents

Speed detection circuit using multipolar resolver

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Publication number
JPS6267459A
JPS6267459A JP20782385A JP20782385A JPS6267459A JP S6267459 A JPS6267459 A JP S6267459A JP 20782385 A JP20782385 A JP 20782385A JP 20782385 A JP20782385 A JP 20782385A JP S6267459 A JPS6267459 A JP S6267459A
Authority
JP
Japan
Prior art keywords
level
signal
signals
low
speed detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20782385A
Other languages
Japanese (ja)
Inventor
Toshihiro Sawa
俊裕 沢
Tsukasa Matsumura
松村 司
Kenji Yamada
賢二 山田
Kazuhiro Kuchiwaki
口脇 和廣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yaskawa Electric Corp
Original Assignee
Yaskawa Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yaskawa Electric Manufacturing Co Ltd filed Critical Yaskawa Electric Manufacturing Co Ltd
Priority to JP20782385A priority Critical patent/JPS6267459A/en
Publication of JPS6267459A publication Critical patent/JPS6267459A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a speed detection signal at low ripple voltage, by providing two digital type monostable circuits in a speed detection circuit using a multipolar resolver while a bridge circuit comprising a resistance and an FET switch is interposed. CONSTITUTION:Digital monostable circuits 2 and 2' triggered by an output signal A of a frequency divider 10 and an inversion signal A thereof, each counting pulses of 4.608MHz up to 1024 and output signals B and C, at high-level during the counting and at low-level after the counting. Then, as the signals B and C are of a TTL level, to drive an FET switch, a level conversion is performed to turn the high-level signals B and C into a voltage Vp and the low-level ones into a voltage VN. When switches 13 to 16 made up of FETs are driven by signals B' and C' thus converted in the level, the switches 13 and 15 are turned On and those 14 and 16 OFF according to the level of the signals B' and c'. Thus a differential effect due to a bridge circuitry of the switches 13 to 16 turns a speed detection signal into a low ripple.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、回転軸に装着する多極レゾルバを使用した速
度検出回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed detection circuit using a multipolar resolver mounted on a rotating shaft.

〔従来技術と問題点〕[Conventional technology and problems]

工作機主軸駆動装置において、工具、ワーク交換などの
ために、主軸の位置決め制御が要求されている。
In machine tool spindle drive devices, positioning control of the spindle is required for exchanging tools and workpieces.

これを達成するためには、低速度での安定した運転と、
剛性すなわち速度制御ゲインを高くすることが必要であ
る。
To achieve this, stable operation at low speeds and
It is necessary to increase the rigidity, that is, the speed control gain.

例えば、主軸モータ定格速度6000rpmに対し、2
rpmで安定して運転し、かつ、2rpmの速度偏差で
、定格トルクを発生するだけの速度制御ゲインが必要で
ある。
For example, for a spindle motor rated speed of 6000 rpm, 2
A speed control gain is required that allows stable operation at rpm and generates rated torque with a speed deviation of 2 rpm.

従って、速度検出回路の温度ドリフトを小さくするとと
もに、リップル電圧を十分小さくしなければならい。
Therefore, it is necessary to reduce the temperature drift of the speed detection circuit and to sufficiently reduce the ripple voltage.

第3図は、従来方式の速度検出回路の構成を表わすブロ
ック図である。
FIG. 3 is a block diagram showing the configuration of a conventional speed detection circuit.

1は4.608MH2の周波数を発生する水晶発振器、
2はデジタル方式単安定回路、3と4はFETによるス
イッチ、5はローパスフィルタ、6は水晶発振器1から
入力を1/256に分周して18KHzを出力する分周
器、7は2相正弦波発生回路、8は多極レゾルバ(α、
βは励磁巻線、θは検出巻線)、9はレゾルバ検出信号
をパルスに変換する電圧比較器、10はレゾルバからの
信号を178に分周する分周器である。
1 is a crystal oscillator that generates a frequency of 4.608MH2,
2 is a digital monostable circuit, 3 and 4 are FET switches, 5 is a low-pass filter, 6 is a frequency divider that divides the input from crystal oscillator 1 to 1/256 and outputs 18KHz, and 7 is a two-phase sine wave generation circuit, 8 is a multipolar resolver (α,
9 is a voltage comparator that converts the resolver detection signal into a pulse, and 10 is a frequency divider that divides the signal from the resolver into 178.

第3図において、2相正弦波発生回路7の出力は、90
0の位相差を持つ2つの18KHzの正弦波信号であり
、レゾルバ8のα、β相の励磁巻線を励磁する。レゾル
バ8の検出巻線θには、次のく1式)のf。のような周
波数信号が発生する。
In FIG. 3, the output of the two-phase sine wave generating circuit 7 is 90
These are two 18 KHz sine wave signals with a phase difference of 0, and excite the α and β phase excitation windings of the resolver 8. The detection winding θ of the resolver 8 has f of the following equation (1). A frequency signal like this is generated.

・・・・・・・・・(1式) ただし、Pはレゾルバ8の極致(72ffi)、Nはレ
ゾルバ8の回転数(rpm)であり、正転時は符号が+
、逆転時は符号が−になる。
...... (1 formula) However, P is the maximum of resolver 8 (72ffi), N is the number of rotations (rpm) of resolver 8, and the sign is + during forward rotation.
, the sign becomes - when reversed.

この周波数f。の検出信号りは、分周器10で1/8に
分周され、信号Aとなり、デジタル単安定回路2の入力
となる。
This frequency f. The detected signal is divided into 1/8 by the frequency divider 10 to become a signal A, which is input to the digital monostable circuit 2.

このディジタル方式単安定回路2は、信号Δが入力され
た後、4.608MHzのパルスを1024計数する。
This digital monostable circuit 2 counts 1024 4.608 MHz pulses after receiving the signal Δ.

この計数期間中、出力Qには高レベルの信号が発生し、
Qの反転信号Qには低レベルの信号が発生しており、計
数完了後はQ。
During this counting period, a high level signal is generated at output Q,
A low level signal is generated in the inverted signal Q of Q, and after the counting is completed, Q.

Qはレベルが反転する。The level of Q is inverted.

3.4のFETによるスイッチは、ゲートGが高レベル
の時オン、低レベルの時オフになる。従って、出力Qが
高レベルの時は、ローパスフィルタ5の入力にはV、が
印加され、低レベルの時は■8が印加される。
The FET switch 3.4 is turned on when the gate G is at a high level and turned off when it is at a low level. Therefore, when the output Q is at a high level, V is applied to the input of the low-pass filter 5, and when it is at a low level, V is applied to the input of the low-pass filter 5.

ローパスフィルタ5の入力波形は、第4図のようになる
The input waveform of the low-pass filter 5 is as shown in FIG.

高レベル時間THは1024/4608 (ms)であ
り、低レベル時間T1は8/fo−TH(ms)である
。従って、ローパスフィルタ5の出力電圧■。は、第4
図の平均電圧となるので、(2式)のようになる。
The high level time TH is 1024/4608 (ms), and the low level time T1 is 8/fo-TH (ms). Therefore, the output voltage of the low-pass filter 5 is ■. is the fourth
Since this is the average voltage shown in the figure, it is expressed as (Equation 2).

・・・・・・・・・(2式) ゆえに、(1式)を用いて、 ・・・・・・・・・(3式) となり、ローパスフィルタ出力は速度Nに比例した電圧
が得られる。
・・・・・・・・・(Formula 2) Therefore, using (Formula 1), we get ・・・・・・・・・(Formula 3), and the low-pass filter output obtains a voltage proportional to the speed N. It will be done.

しかし、第2図のローパスフィルタ入力信号Eの基本波
成分の振幅■、は ・・・・・・・・・(4式) となり、(4式)(5式)より、φ=O1すなわち 宮 で最大となるから、位置決め制御に使用する低速度でリ
ップル電圧が最も大きくなる。
However, the amplitude ■ of the fundamental wave component of the low-pass filter input signal E in FIG. Therefore, the ripple voltage is largest at low speeds used for positioning control.

従って、従来の方式では、速度検出信号のリップル電圧
が障害となり、速度制御ゲインを高くできないため、位
置決め制御に対応するのが困難であることがわかる。
Therefore, it can be seen that in the conventional method, the ripple voltage of the speed detection signal becomes an obstacle and the speed control gain cannot be increased, making it difficult to cope with positioning control.

(発明の目的〕 ここに本発明は、従来装置の難点を克服し、低速におい
て、低リツプル電圧の速度検出信号が得られる多極レゾ
ルバを使用した速度検出回路を提供することを、その目
的とする。
(Object of the Invention) The object of the present invention is to provide a speed detection circuit using a multipolar resolver that can overcome the difficulties of conventional devices and provide a speed detection signal with a low ripple voltage at low speeds. do.

〔発明の概要〕[Summary of the invention]

本発明は、上記目的を達成するために、多極レゾルバを
使用した速度検出回路に、デジタル式単安定回路を2個
設け、抵抗とFETスイッチで構成したブリッジ回路を
介して、差動効果による低リップル化を図った手段であ
る。
In order to achieve the above object, the present invention provides a speed detection circuit using a multipolar resolver with two digital monostable circuits, and uses a differential effect to connect the speed detection circuit to a speed detection circuit using a multipolar resolver. This is a means to reduce ripple.

〔実 施 例〕〔Example〕

本発明の一実施例における回路構成を表わすブロック図
を第1図に示す。
FIG. 1 shows a block diagram showing a circuit configuration in an embodiment of the present invention.

第1図において、第3図と同一符号は同一もしくは相当
部分であり、2′は2と同じデジタル単安定回路、17
は分周器10の出力信号Aを反転するNOV回路、11
.12はレベル変換回路、13〜16はFETによるス
イッチである。
In Figure 1, the same symbols as in Figure 3 are the same or equivalent parts, 2' is the same digital monostable circuit as 2, 17
11 is an NOV circuit that inverts the output signal A of the frequency divider 10;
.. 12 is a level conversion circuit, and 13 to 16 are FET switches.

分周器10の出力信号Aとその反転信号Aでトリガされ
たデジタル単安定回路2,2′は、それぞれ4.608
MHzのパルスを1024計数して、31数中高レベル
、計数後低レベルの信号B。
The digital monostable circuits 2, 2' triggered by the output signal A of the frequency divider 10 and its inverted signal A are each 4.608
1024 MHz pulses are counted, 31 are high level, and signal B is low level after counting.

Cを出力する。Output C.

次に、信号B、CはTTLレベルの信号であるので、F
ETスイッチを駆動するため、B、Cが高レベル時はV
 に、低レベル時は■8になるように、レベル変換する
Next, since signals B and C are TTL level signals, F
To drive the ET switch, when B and C are at high level, V
When the level is low, the level is converted so that it becomes ■8.

このレベル変換した信号B’ 、C’で、FET13〜
16を駆動すると、信号B’ 、C’が高レベルの時、
FET13,15がオン、FET14゜16がオフにな
り、信号B’ 、C’ が低レベルの時、FET13,
15がオフ、FET14,16がオンになる。
With these level-converted signals B' and C', FET13~
16, when the signals B' and C' are at high level,
When FETs 13 and 15 are turned on and FETs 14 and 16 are turned off, and signals B' and C' are at low level, FETs 13 and 15 are turned on.
15 is turned off, and FETs 14 and 16 are turned on.

ローパスフィルタ5の入力信号Fは、第1図のFET1
3〜16と抵抗R−R8で構成されたブリッジ回路の出
力信号であるから、その値は信号B’ 、C’のレベル
によって次のようになる。
The input signal F of the low-pass filter 5 is input to the FET 1 in FIG.
Since this is the output signal of the bridge circuit composed of the signals B' and C', its value is as follows depending on the levels of the signals B' and C'.

a) モード1 信号B’ 、C’が共に高レベルの場合、FET13.
15がオン、FET14.16がオフになるから、信号
Fの電圧は ■F1−■P ここで、R1−R2−R3=R4−R、R5=R6=R
7=R8=RBとすると となる。
a) Mode 1 When both signals B' and C' are at high level, FET13.
15 is on and FET14.16 is off, the voltage of signal F is ■F1-■P Here, R1-R2-R3=R4-R, R5=R6=R
7=R8=RB.

b) モード2 信号B’ 、C’ が共に低レベルの場合、FET13
.15がオフ、FET14.16がオンになるから、信
号Fの電圧は ■F2=■N となる。
b) Mode 2 When both signals B' and C' are low level, FET13
.. Since FET 15 is turned off and FET 14.16 is turned on, the voltage of signal F becomes ■F2=■N.

C) モード3 信号B′が高レベル、信号C′が低レベルの場合、FE
T13,16がオン、FET14,15がオフになるか
ら、信号Fの電圧は R/RR3+R7 R2+R658 VP+V、     RB =□□・・・(8式) %式% ゞ         ・・・・・・・・・(8′式)■
F3=。
C) Mode 3 When signal B' is high level and signal C' is low level, FE
Since T13 and 16 are on and FET14 and 15 are off, the voltage of signal F is R/RR3+R7 R2+R658 VP+V, RB =□□...(8 formula) % formula% ゞ ・・・・・・・・・(8' type)■
F3=.

d) モード4 信号8′が低レベル、信号C′が高レベルの場合、FE
T13,16がオフ、FET14,15がオンになるか
ら信号Fの電圧は R+RR/RR4+RB 2      R+2RB となり、v  =−vHとすると P ■ V、−O・・・・・・・・・(9′式)第2図は、本発
明の詳細な説明するタイムチャートである。
d) Mode 4 When signal 8' is low level and signal C' is high level, FE
Since T13 and 16 are turned off and FET14 and 15 are turned on, the voltage of signal F becomes R+RR/RR4+RB 2 R+2RB, and when v = -vH, P ■ V, -O... (9' (Formula) FIG. 2 is a time chart for explaining the present invention in detail.

第2図において、(a)はレゾルバ8が停止している場
合、(b)は正回転している場合、(C)は逆回転して
いる場合である。
In FIG. 2, (a) shows the case where the resolver 8 is stopped, (b) shows the case where it is rotating in the forward direction, and (C) shows the case where it is rotating in the reverse direction.

第2図(a)におイテ、信号Aは2.25KHzであり
、信号B、CのTH待時間、1024/4608=1/
45 (ms)であるから、モード3,4の繰り返しと
なり、信号Fの電圧■、はoVとなる。
In Fig. 2(a), signal A is 2.25KHz, and the TH waiting time of signals B and C is 1024/4608=1/
45 (ms), modes 3 and 4 are repeated, and the voltage of signal F becomes oV.

次に第4図(b)において、信号A、Aは、(1式)で
示される周波数f。の1/8である。この時の信号Aの
周期と、信号B、CのTF1時間従って、この差の時間
は信号B、C共に高レベルとなるので、モード1,3.
4を繰り返し、ローパスフィルタ5の出力電圧V。は第
2図(b)の平均電圧となるので、(10式)のように
なる。
Next, in FIG. 4(b), the signals A and A have a frequency f shown by (Equation 1). It is 1/8 of that. According to the period of signal A at this time and the TF1 time of signals B and C, the time difference is such that both signals B and C are at a high level, so modes 1, 3...
Repeat step 4 to obtain the output voltage V of the low-pass filter 5. is the average voltage shown in FIG. 2(b), so it is as shown in equation (10).

■= 8/f。■= 8/f.

(1式)、(6式)、(8式)、(9式)よりVo= ・・・・・・・・・(10式) %式% ・・・・・・・・・(10′式) となり、ローパスフィルタ5出力は速度Nに比例した電
圧が得られる。
From (Equation 1), (Equation 6), (Equation 8), and (Equation 9), Vo = ...... (Equation 10) % expression % ...... (10' Equation) As a result, a voltage proportional to the speed N can be obtained as the output of the low-pass filter 5.

またこの時のローパスフィルタ5の入力、すなわち、信
号Fの基本波成分の振幅VFは・・・・・・・・・(1
1式) ただし、 ・・・・・・・・・(12式) %式% で、V、=Oとなるから、位置決め制御に使用する低速
度はど、リップル電圧が小さくなる。
In addition, the input of the low-pass filter 5 at this time, that is, the amplitude VF of the fundamental wave component of the signal F is (1
(Equation 1) However, since V, = O, the ripple voltage becomes smaller at low speeds used for positioning control.

最後に第2図(C)において、信号Aの周期と、2TH
となる。
Finally, in Figure 2 (C), the period of signal A and 2TH
becomes.

従って、この差の時間は、信号B、C共に低レベルにな
るため、モード2.3.4を繰り返し、ローパスフィル
タ5の出力電圧■。は ・・・・・・・・・(13式) %式% ・・・・・・・・・(13′式) となる。
Therefore, during this difference time, both signals B and C become low level, so mode 2.3.4 is repeated, and the output voltage of the low-pass filter 5 is reduced to ■. is... (Formula 13) % formula % ...... (Formula 13')

ゆえに(10′式)=−(13’式)となり、ローパス
フィルタ5の出力電圧■。は回転数Nに比例し、正回転
時正電圧、逆回戦時負電圧を発生する。
Therefore, (formula 10') = - (formula 13'), and the output voltage of the low-pass filter 5 is ■. is proportional to the rotation speed N, and generates a positive voltage during forward rotation and a negative voltage during reverse rotation.

〔発明の効果〕〔Effect of the invention〕

以上の実施例に示すように、本発明によって、次の効果
が得られる。
As shown in the above embodiments, the following effects can be obtained by the present invention.

■ 本発明の速度検出回路は、速度検出信号のリップル
電圧が小さい。特に低速になる程リップル電圧が小さく
なる。
(2) The speed detection circuit of the present invention has a small ripple voltage of the speed detection signal. In particular, the lower the speed, the smaller the ripple voltage.

■ リップル電圧が小さく、かつ、その基本周波数は信
号の2倍であるから、ローパスフィルタが簡単になる。
■ Since the ripple voltage is small and its fundamental frequency is twice that of the signal, the low-pass filter becomes simple.

この結果、速度制御ゲインが高くとれ、高精度の位置制
御が可能となる。
As a result, a high speed control gain can be obtained, and highly accurate position control is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例における回路構成を示すブ
ロック図、第2図はその動作を表わすタイムチャート、
第3図は従来方式の速度検出回路のブロック図、第4図
はローパスフィルタの入力電圧波形図である。 1・・・水晶発振器、2,2′・・・ディジタル方式単
安定回路、3.4,13.14,15,16・・・FE
Tによるスイッチ、5・・・ローパスフィルタ、6.1
0・・・分周器、7・・・2相正弦波発生回路、8・・
・多極レゾルバ、9・・・電圧比較器、11.12・・
・レベル変換回路、17・・・NOT回路。
FIG. 1 is a block diagram showing a circuit configuration in an embodiment of the present invention, FIG. 2 is a time chart showing its operation,
FIG. 3 is a block diagram of a conventional speed detection circuit, and FIG. 4 is an input voltage waveform diagram of a low-pass filter. 1... Crystal oscillator, 2, 2'... Digital monostable circuit, 3.4, 13.14, 15, 16... FE
Switch by T, 5...Low pass filter, 6.1
0... Frequency divider, 7... 2-phase sine wave generation circuit, 8...
・Multi-pole resolver, 9...voltage comparator, 11.12...
-Level conversion circuit, 17...NOT circuit.

Claims (1)

【特許請求の範囲】 レゾルバ検出信号を分周して得られた信号Aと、その反
転信号@A@でそれぞれトリガされた二つのデジタル単
安定回路の一定時間幅パルス信号B、Cを作る手段と、 抵抗とFETスイッチで構成したブリッジ回路のスイッ
チを信号B、Cで開閉する手段と、その開閉する手段に
より得られた差電圧をローパスフィルタを通して、アナ
ログ電圧を導出する手段と、 をそなえることを特徴とするレゾルバを用いた速度検出
回路。
[Claims] Means for generating constant time width pulse signals B and C of two digital monostable circuits triggered by the signal A obtained by frequency-dividing the resolver detection signal and its inverted signal @A@ and means for opening and closing the switches of a bridge circuit composed of resistors and FET switches using signals B and C, and means for deriving an analog voltage by passing the differential voltage obtained by the opening and closing means through a low-pass filter. A speed detection circuit using a resolver featuring:
JP20782385A 1985-09-20 1985-09-20 Speed detection circuit using multipolar resolver Pending JPS6267459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20782385A JPS6267459A (en) 1985-09-20 1985-09-20 Speed detection circuit using multipolar resolver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20782385A JPS6267459A (en) 1985-09-20 1985-09-20 Speed detection circuit using multipolar resolver

Publications (1)

Publication Number Publication Date
JPS6267459A true JPS6267459A (en) 1987-03-27

Family

ID=16546097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20782385A Pending JPS6267459A (en) 1985-09-20 1985-09-20 Speed detection circuit using multipolar resolver

Country Status (1)

Country Link
JP (1) JPS6267459A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182559A (en) * 1982-04-21 1983-10-25 Yaskawa Electric Mfg Co Ltd Detecting apparatus of speed of revolution using resolver
JPS59148871A (en) * 1983-02-15 1984-08-25 Yaskawa Electric Mfg Co Ltd High-precision speed detecting circuit using resolver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182559A (en) * 1982-04-21 1983-10-25 Yaskawa Electric Mfg Co Ltd Detecting apparatus of speed of revolution using resolver
JPS59148871A (en) * 1983-02-15 1984-08-25 Yaskawa Electric Mfg Co Ltd High-precision speed detecting circuit using resolver

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