JPS6266499U - - Google Patents
Info
- Publication number
- JPS6266499U JPS6266499U JP15653885U JP15653885U JPS6266499U JP S6266499 U JPS6266499 U JP S6266499U JP 15653885 U JP15653885 U JP 15653885U JP 15653885 U JP15653885 U JP 15653885U JP S6266499 U JPS6266499 U JP S6266499U
- Authority
- JP
- Japan
- Prior art keywords
- delay circuit
- circuit
- signals
- audio
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005236 sound signal Effects 0.000 claims description 4
- 230000002265 prevention Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第1図は本考案にかかるオーデイオ装置の要部
ブロツク図、第2図は各音声信号のレベルと発生
時刻の関係図、第3図は従来のオーデイオ装置の
ブロツク図、第4図は第3図における各音声信号
のレベルと発生時刻との関係図である。
11RL……第1の遅延回路、12RL……干
渉防止回路、13RL……第2の遅延回路、14
RL……減衰帰還回路、15L,15R……フロ
ントスピーカ、16L,16R,17L,17R
……サラウンドスピーカ。
Fig. 1 is a block diagram of the main parts of the audio device according to the present invention, Fig. 2 is a diagram showing the relationship between the level and generation time of each audio signal, Fig. 3 is a block diagram of a conventional audio device, and Fig. 4 is a block diagram of the conventional audio device. FIG. 3 is a relationship diagram between the level and generation time of each audio signal in the figure. 11RL...first delay circuit, 12RL...interference prevention circuit, 13RL...second delay circuit, 14
RL...Attenuation feedback circuit, 15L, 15R...Front speaker, 16L, 16R, 17L, 17R
...Surround speakers.
Claims (1)
L0,R0をそれぞれ所定時間D1遅延する第1
の遅延回路と、 入力信号と出力信号の干渉を防止する干渉防止
回路と、 干渉防止回路を介して入力される前記第1の遅
延回路からの信号L1,R1をそれぞれ所定時間
D2遅延する第2の遅延回路と、 該第2の遅延回路の出力信号L2,R2をそれ
ぞれ所定量減衰させて第2の遅延回路の入力側に
帰還させる減衰帰還回路を有し、 前記各信号L0,R0,L1,R1,L2,R
2を所定のスピーカに入力することを特徴とする
オーデイオ装置。[Claims for Utility Model Registration] A first system that delays the audio signals L 0 and R 0 of the L-channel and R-channel by a predetermined time D1, respectively.
a delay circuit; an interference prevention circuit that prevents interference between the input signal and the output signal; and signals L 1 and R 1 from the first delay circuit inputted through the interference prevention circuit are each delayed by a predetermined time D 2 . and an attenuation feedback circuit that attenuates the output signals L 2 and R 2 of the second delay circuit by a predetermined amount and feeds the respective signals back to the input side of the second delay circuit, L 0 , R 0 , L 1 , R 1 , L 2 , R
1. An audio device characterized in that an audio signal of 2 is input to a predetermined speaker.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15653885U JPH03800Y2 (en) | 1985-10-15 | 1985-10-15 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15653885U JPH03800Y2 (en) | 1985-10-15 | 1985-10-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6266499U true JPS6266499U (en) | 1987-04-24 |
JPH03800Y2 JPH03800Y2 (en) | 1991-01-11 |
Family
ID=31078246
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15653885U Expired JPH03800Y2 (en) | 1985-10-15 | 1985-10-15 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03800Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014096735A (en) * | 2012-11-09 | 2014-05-22 | Onkyo Corp | Audio processing unit |
-
1985
- 1985-10-15 JP JP15653885U patent/JPH03800Y2/ja not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014096735A (en) * | 2012-11-09 | 2014-05-22 | Onkyo Corp | Audio processing unit |
Also Published As
Publication number | Publication date |
---|---|
JPH03800Y2 (en) | 1991-01-11 |