JPS6266397U - - Google Patents
Info
- Publication number
- JPS6266397U JPS6266397U JP15658985U JP15658985U JPS6266397U JP S6266397 U JPS6266397 U JP S6266397U JP 15658985 U JP15658985 U JP 15658985U JP 15658985 U JP15658985 U JP 15658985U JP S6266397 U JPS6266397 U JP S6266397U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- bit
- demodulator
- lock bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims 3
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Computer And Data Communications (AREA)
- Selective Calling Equipment (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は従来のビツト試験器を示す構成図である。
１１……復調器、１２……ビツト加算器、１３
……キーボード、１４……処理部、１５……ロツ
クビツトメモリ、１６……変調器。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a block diagram showing a conventional bit tester. 11...Demodulator, 12...Bit adder, 13
...Keyboard, 14...Processing unit, 15...Lock bit memory, 16...Modulator.
Claims (1)
受を伝送路を介して行なうものの信号ビツトを試
験するものにおいて、前記伝送路より入力された
搬送波をデイジタル信号に返還する復調器と、こ
の復調器の出力信号を入力するビツト加算器と、
このビツト加算器の出力を導入して変調する変調
器と、前記復調器の出力を導入し、信号中のワー
ド番号抽出機能を有する処理部と、この処理部を
介して入力され、キーボードにて指定されたロツ
クビツト情報を記憶するロツクビツトメモリとを
有し、前記処理部はワード番号抽出時にロツクビ
ツトメモリの記憶内容を参照し、前記ビツト加算
器にロツクビツト情報の有無を出力するように構
成したことを特徴とするビツト試験器。 A device that tests the signal bits of a signal configured in a predetermined transmission format through a transmission line, includes a demodulator that returns the carrier wave input from the transmission line to a digital signal, and the output of this demodulator. a bit adder that inputs the signal;
A modulator that introduces and modulates the output of this bit adder, a processing section that introduces the output of the demodulator and has a function of extracting word numbers from the signal, and and a lock bit memory for storing designated lock bit information, and the processing section is configured to refer to the stored contents of the lock bit memory when extracting a word number and output the presence or absence of lock bit information to the bit adder. A bit tester characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15658985U JPH0348709Y2 (en) | 1985-10-14 | 1985-10-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15658985U JPH0348709Y2 (en) | 1985-10-14 | 1985-10-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6266397U true JPS6266397U (en) | 1987-04-24 |
| JPH0348709Y2 JPH0348709Y2 (en) | 1991-10-17 |
Family
ID=31078344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15658985U Expired JPH0348709Y2 (en) | 1985-10-14 | 1985-10-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0348709Y2 (en) |
-
1985
- 1985-10-14 JP JP15658985U patent/JPH0348709Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0348709Y2 (en) | 1991-10-17 |
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