JPS6265360A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor element from breakdown due to excess electric energy by a method wherein a the excess electric energy is discharged through the bottom of a semiconductor region and the concentration is reduced of the current at the time of discharge. CONSTITUTION:Among a plurality of elements constituting an input or output buffer or the like in a region X, a MISFET in direct connection with a bonding pad 9, for example a protecting MISFET in an input protecting circuit, is provided. The MISFET in the region X is built on a p<+>-type semiconductor region 11. Impurity concentration n and depth of the semiconductor region 11 is optimized so that the punch-through withstand voltage between the n-type semiconductor region 4 and a semiconductor substrate 1 is controlled and adjusted to be lower than that in a junction on the side of the semiconductor region 4. In a device designed as such, a surge current coming in at a bonding pad 9 is discharged to the semiconductor substrate 1 through the bottom of the semiconductor region 4, which eliminates surge current concentration. The n-type semiconductor region 4 is protected at its junction from breakdown attributable to excess electric energy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique for preventing electrical breakdown of semiconductor elements.

[Background Art] In a semiconductor integrated circuit device including a MISFET represented by a MOSFET, an input protection circuit is generally connected between a bonding pad as an external terminal and the MISFET forming an internal circuit.

The input protection circuit consists of, for example, a resistive element and a clamping MO8FET connected in a diode configuration, and utilizes the surface breakdown of the clamp MO3FET.

The present inventor discovered the following problem in an input protection circuit that utilizes the surface breakdown. That is, when surface breakdown of a MOSFET is utilized, excessive electrical energy applied to the bonding pad is mainly released from the sides of the semiconductor region, which is the source and drain regions of the MOSFET. For this reason,
Since the current density at the time of discharge increases significantly, the MOSFET constituting the input protection circuit itself is destroyed at a certain voltage, and therefore the breakdown voltage (breakdown voltage) of the semiconductor integrated circuit device cannot be increased.

[Object of the Invention] An object of the present invention is to provide a technique for improving the reliability of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique for improving the reliability of semiconductor integrated circuit devices by preventing destruction of semiconductor elements due to excessive electrical energy.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

That is, by discharging excessive electrical energy from the bottom of the semiconductor region, the current density at the time of discharging is reduced.

Hereinafter, the configuration of the present invention will be explained along with examples.

[Embodiment 2] FIG. 1 is a sectional view of a semiconductor integrated circuit device according to Embodiment I of the present invention. This semiconductor integrated circuit device includes, for example, N-channel and P-channel MISFETs (complementary MISFETs).
It has the following. In FIG. 1, a region X is a region where a MISFET directly connected to the bonding pad 9, for example, a protection MISFET of an input protection circuit, among elements constituting an input or output buffer, etc., and a region Y is a region where, for example, a decoder, This is a region where MISFETs that are not directly connected to bonding pads such as sense amplifiers are provided.

1 and 2, 1 is a semiconductor substrate made of n-type silicon single crystal, and 2 is a field insulating film (S
3 is a P-type channel stopper region, 12 is a P
- type well region. Reference numeral 4 denotes a source or drain region made of an n0 type semiconductor region, which constitutes a MISFET in regions X and Y together with a gate insulating film (Si02@) 5 and a gate electrode 6. The gate electrode 6 is made of a polycrystalline silicon layer. This polycrystalline silicon layer has
It does not contain n-type impurities such as phosphorus (P) or arsenic (As). Note that the gate electrode 6 is made of 1, for example, molybdenum (Mo
), tungsten (W), titanium (Ti), tantalum (
It may also be formed of a high melting point metal layer such as Ta). Further, a silicide layer of the above-mentioned high melting point metal may be used. Furthermore, the high melting point metal layer or silicide layer may be provided on the polycrystalline silicon layer.

In region X, there are two MI 5FETQ+, Q2.

The input protection circuit shown in FIG. 3 is configured together with a resistor R2 and a MISFET Q3 (not shown).

The MISFET shown in area Y constitutes a decoder, an amplifier, etc. together with other N- and P-channel MISFETs (not shown). 7 is a conductive layer made of an aluminum layer. The conductive layer 7 is connected to the M I S FE through the connection hole 8.
It is connected to the semiconductor region 4 of T. Note that 5 gate electrodes 6
A conductive layer (not shown) made of aluminum is also connected to the conductive layer, and as shown in FIG. 3, a fixed potential, such as the ground potential of the circuit, is supplied.

The conductive layer 7A is the two MISFETQ+.

Q2 is electrically connected to a bonding pad 9, which is an external terminal of the semiconductor integrated circuit device, through a resistor RI.

The conductive layer 7B connects one MISFETQ to a power supply potential Vc.
c, for example, 5 [■]. The conductive layer 7C is connected to the ground potential V s to the other M I S F E T Q 2
s, for example, O[V].

10 is an insulating film made of phosphosilicate glass (PSG) or the like.

The M I S FET in the region X has a p-type semiconductor region 11
form on top of. By optimizing the concentration and depth of the semiconductor region 11, the punch-through breakdown voltage between the semiconductor region 4 and the semiconductor substrate 1 can be controlled. The concentration of the channel region IA is lower than that of the p-type semiconductor region 11.

This makes the punch-through breakdown voltage between the n-type semiconductor region 4 and the semiconductor substrate 1 lower than the junction breakdown voltage of the side portions of the semiconductor region 4.

I can do it. At this time, the surge current entering from the bonding pad 9 is discharged from the lower part of the semiconductor region 4 to the semiconductor substrate 1. This prevents surge current from concentrating on the sides of the semiconductor region 4, thereby preventing junction breakdown in the n-type semiconductor region 4 due to excessive electrical energy.

That is, the electrical reliability of the MISFET is improved.

Note that the impurity concentration and depth of the p-type semiconductor region 11 are such that when the breakdown voltage between the source and drain regions, that is, between the n-type semiconductor region 4 is about 15 [V],
The punch-through breakdown voltage between the semiconductor substrates 1 is set to about 10 [V].

Specifically, the impurity concentration of the n-type semiconductor region 4 is 10"
'~10'' When it is about 1[atoss/cj],
The impurity concentration of the p-type semiconductor region 11 is 101@[ato
ms/cd] and the depth is approximately 0.5 to 1 [μm].

On the other hand, the MISFET in region Y is provided in the p-type well region.

Note that the p-type semiconductor region 11 may be provided below the resistance element R+ made of an n'-type semiconductor region.

This resistance element R1 is a diode type MTSFETQ
1. It is connected to the input bonding pad 9 together with Q2 to form a so-called input protection circuit.

This semiconductor region 11 is the same as a p-type semiconductor region provided under the source and drain regions of MISFETs constituting a memory cell to prevent soft errors caused by α rays in, for example, static random access memory (SRAM). Can be formed during the process.

Furthermore, a p-type head region 3 is formed in a portion under the field insulating film 2 in contact with the semiconductor region 11. This is to prevent short circuits between the semiconductor region 4 and the substrate 1 due to process variations or the like. The region 3 is formed in the same process as the P-type channel stopper 3 provided in the well region 2 to prevent its surface from being inverted.

MISFE is applied to the M I S F E TQs shown in Figure 3.
A structure similar to TQ (Q2) may be applied. In addition,
In FIG. 3, Q3 is M connected in diode form.
I5FET, R2 is a resistor made of polycrystalline silicon. Omit R2 and Q3 or R1 and Ql, Q
2 may be omitted to configure the input protection circuit.

[Example ■Example ■ is the M I connected to the bonding pad 9.
5FETQ+, Q2 in shallow p-type well region 12A
is provided to transfer excess electrical energy flowing from the bonding pad 9 to the substrate 1 from the bottom of the
Release to.

As shown in FIG.
In this example, a shallow p" type well region 12A is provided in region X, and a deep P-type well region 12 is provided in region Y. For example, a ground potential vss is applied to the well regions 12 and 12A.

The well region 12A in region X has a shallow depth of about 1.5 [μml] from its surface to its bottom. M.I.
SFET 04 type semiconductor region 4 and n-type semiconductor substrate 1
This is to make it easier for punch-through to occur between the two.

Specifically, when a positive surge voltage of approximately lo [V] or more is applied to the n° type semiconductor region 4, the punch-through occurs. Between the source and drain regions,
That is, punch-through does not occur in the n-type semiconductor region 4 unless a voltage of about 15[1 or higher is applied.

Therefore, excess electrical energy flowing from the bonding pad 9 is released from the bottom of the rl'' type semiconductor region 4 to the substrate 1.

M I S F E connected to bonding pad 9
By providing T in the shallow well region 12, destruction of the MISFET due to excessive electrical energy can be prevented.

On the other hand, the depth of the well region 12 in region Y is 3[μ
m] deep. This is to increase the breakdown voltage between the n'' type semiconductor region 4 and the type semiconductor substrate 1 to about 40 [V].

Note that the semiconductor elements constituting the input protection circuit, that is,
A low resistance element made of a MISFET type diode or a semiconductor region may be provided in the shallow well region 12. This is to protect the semiconductor elements of the input protection circuit from excessive electrical energy.

[Effect Co. According to the novel technology disclosed by this application.

You can get the following effects.

(1) By providing a second semiconductor region of the opposite conductivity type to the first semiconductor region under the first semiconductor region connected to the bonding pad, or by providing the first semiconductor region in a shallow well region. Since the junction breakdown voltage at the bottom of the first semiconductor region is lowered, excess electrical energy flowing from the bonding pad can be released from the bottom of the first semiconductor region.

(2) According to (1) above, the reliability of the semiconductor integrated circuit device can be improved by preventing destruction of the first semiconductor region due to excessive electrical energy.

Although the present invention has been specifically described above with reference to the embodiments, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.

For example, an MI for protecting the output circuit as shown in FIG.
S F E TQ4. The present invention can also be applied to Qs. Further, the potential applied to the gate electrode of the MISFET to which the present invention is applied is not particularly limited.

The conductivity type of the well region and the semiconductor region provided in the well region is not limited.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device of Example I, FIG. 2 is a cross-sectional view of a semiconductor integrated circuit device of Example II, and FIGS. 3 and 4 are MISFETs to which the present invention is applied.
It is a circuit diagram using. l...Semiconductor substrate, 2...Field insulating film, 3.
... Channel stopper region, 4.11... Semiconductor region, 5.10... Insulating film, 6.7.7A, 7B, 7C.
... Conductive layer, 8... Connection hole, 9... Bonding pad, 12... Well region. Figure 3 Figure 4

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising a semiconductor region provided on the surface of a semiconductor substrate and an external terminal connected to the semiconductor region, wherein A semiconductor integrated circuit device characterized by a lower punch-through withstand voltage at the bottom. 2. The semiconductor integrated circuit device according to claim 1, wherein the external terminal is a bonding pad. 3. By providing a second semiconductor region different from the conductivity type of the semiconductor region under the semiconductor region on the surface portion of the semiconductor substrate, the punch-through breakdown voltage between the semiconductor substrate and the semiconductor region provided on the surface portion is increased as described above. 2. The semiconductor integrated circuit device according to claim 1, wherein the junction breakdown voltage is lower than the junction breakdown voltage of the semiconductor region.