JPS626522A - Triangle wave generating circuit - Google Patents

Abstract

PURPOSE:To decrease the number of terminal pins for circuit integration by providing a comparison circuit supervising an output level of a storage means and a control means activating the 2nd constant current source based on the output of the comparator circuit so as to output an output signal of the storage means as a triangle wave signal. CONSTITUTION:A reference power voltage Vref is fed to each non-inverting input of comparators COMP3, COMP4 via a resistor R16, and since each resistance of resistors R15, R16 is set equally, a drive signal is biased to 1/2Vref when the signal becomes a comparison input to a window comparator 9. That is, the signal reference level of the drive signal is 1/2Vref. Thus, the circuit reference level of a triangle wave generating circuit 8, that is, the comparison reference level of the comparator circuit 3 and the DC bias level (signal reference level) of the drive signal are set by the resistance voltage division of the same reference power voltage Vref. Thus, the circuit operation always stable is performed regardless of the variation in the power voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND ART A PWM (Pulse Width Modulation) bidirectional switching drive method is known as one method for driving a load such as a motor. This drive method has excellent features of low loss and reduced power consumption, and is particularly useful for driving loads such as motors in vehicle-mounted devices, portable devices, etc. that use batteries as power sources.

For example, as shown in FIG. 13, this PWM drive circuit uses two triangular wave signals a that are in phase with each other.

The comparator circuit 100 generates the triangular wave signals b and compares the triangular wave signals with one of the triangular wave signals a having a higher DC bias level than the other.
By using the upper and lower limit reference inputs and further using the drive signal C as a comparison input, a pair of pulse signals d and e with a pulse width corresponding to the signal level of the drive signal and corresponding to the drive direction of the load is obtained, A configuration in which a load is driven in a switching manner based on the pair of pulse signals d and e is known.

This PWM drive circuit uses a circuit that generates a triangular wave signal. Conventionally, this triangular wave generating circuit
As shown in Fig. 14, a constant period rectangular wave signal is input to the operational amplifier 0PIO, resistor Rao, R4+ and capacitor C10.
A structure in which the signal is converted into a triangular wave signal by an integrator 101 consisting of the following was used. In such a triangular wave generation circuit having an integrator configuration, when considering integration into an IC (integrated circuit), two terminal pins P+ and R2 are required in order to externally attach the capacitor CIO. However, when converting to an IC, it is desirable to have a circuit configuration that can reduce the number of terminal bins as much as possible.

R''J and LL The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a triangular wave generation circuit that can reduce the number of terminal bins when integrated into an IC.

The triangular wave generation circuit according to the present invention includes a first constant current source and a second constant current source having a constant current value twice that of the first constant current source. The configuration is such that a triangular wave signal is generated by charging and discharging a capacitor (power storage means) with a constant current through on/off control.

Example Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

In FIG. 1, a first constant current source 1 is a transistor Q
+, Q2 and a current mirror circuit consisting of resistors R+, R2. The second constant current source 2 connected in series with the first constant current source 1 has transistors Q3 and Q4 connected in parallel to each other, and bases of these transistors Q3 and Qs are commonly connected through a resistor R3. It is constituted by a current mirror circuit consisting of a transistor Q5 and emitter resistors R4 and Rs of each transistor, and is adapted to sink a current value 2io that is twice the constant current value io of the first constant current source 1. . 1st and 2nd
The common connection point of the constant current source 1.2, that is, the transistor Q2
A capacitor C1, which is a power storage means, is connected between the common connection point of the collectors of the transistors Q3 and Qa and the ground, which is a reference potential point.

The voltage across the capacitor C1 is the comparator COMP
+, COMP 2 and the comparison input of the comparison circuit 3 that monitors the voltage level, that is, the comparator CO'
It becomes the inverting input of MP+ and the non-inverting input of COMP2. The upper and lower comparison reference levels Vu and VL of the comparison circuit 3 are set by four resistors R5 to R8 connected in series with each other.
It is set by dividing the reference power supply voltage Vref by . The resistors R5 to R8 are further connected to the reference power supply voltage V ref
The voltage is divided to approximately 1/2 and the voltage is set to 1/2 V ref via an operational amplifier OP+ having a voltage follower circuit configuration. Two comparison outputs of comparison circuit 3, namely comparator COMP
The outputs of + and COMP2 become set (S) and reset (R) inputs of R8-flip-flop 4.

The d output of the flip-flop (hereinafter simply referred to as FF) 4 is composed of a transistor Q6 and resistors R9 and RIO, and the second
The constant current source 2 is supplied to a control circuit 5 which controls activation/deactivation of the constant current source 2. This control circuit 5 includes a transistor Q6
turns on in response to the 0 output of FF4, turning off transistors Q3 and Q4, thereby inactivating the second constant current source 2.

Second constant current il! The voltage across the emitter resistor R5 at i2 serves as an inverting input of an operational amplifier OP2 having a voltage borrow circuit configuration. Opamp OP2 is resistor RIIIR
A comparison reference level is set by dividing the reference power supply voltage vrer by 12, and the first
and a current value setting circuit 6 that sets the constant current values of the second constant current sources 1 and 2.

The voltage across the capacitor C1 becomes the first phase triangular wave signal φa through the operational amplifier OP3 having a voltage follower circuit configuration, and is phase inverted by the inverter 7 consisting of the operational amplifier OP4 and resistors R13 and R14 to become the first phase triangular wave signal φ.
The second phase triangular wave signal φb is opposite in phase to a. A DC bias of 1/2 V ref is applied to these triangular wave signals φa and φb.

As described above, a triangular wave generation circuit 8 is configured that generates two-phase triangular wave signals φa and φb having substantially equal peak values and mutually opposite phases. This triangular wave generation circuit 8 includes a first constant current source 1 with a constant current value of 1o and a second constant current source 2 with a constant current value of 2fo, and controls the capacitor by on/off control of the second constant current source 2. Since the configuration is such that a triangular wave is generated by charging and discharging C1 with a constant current, when converting the circuit 8 into an IC (integrated circuit), one terminal bin (the first Terminal 8a in the figure
).

The two-phase triangular wave signals φa and φb are sent to the comparator COM P
3. Upper and lower limit comparison reference inputs of the comparator circuit 9 consisting of COMP4, that is, comparator COMP3
, COMP4 are inverted inputs. Comparison input of comparison circuit 9, ie, comparator COMP3.

A drive signal for a load, for example a motor M, is supplied to each non-inverting input of COMP 4 via a resistor R+s.

A reference power supply voltage y rer is applied to each non-inverting input terminal of the comparators COM P 3 and COM P 4 via a resistor R+s (R+s = R+6>), and the resistance values of the resistors R+s and R+s are set equal. As a result, the drive signal is biased to 1/2 V raf when it becomes the comparison input of the window comparator 9. In other words, the signal reference level of the drive signal is 1/2 V raf.
It becomes r+J.

As a result, the circuit reference level of the triangular wave generation circuit 8, that is, the comparison reference level of the comparator circuit 3 and the DC bias level (signal reference level) of the drive signal are both set by resistive voltage division of the same reference power supply voltage V ref. It turns out.

Therefore, even if there are fluctuations in the power supply voltage, the two-phase triangular wave signal φ
Since the relative signal levels of a, φb and the drive signal are always kept constant, stable circuit operation is always performed regardless of fluctuations in the Ns lightning voltage.

The comparison output of the comparator COM P 3 becomes the output of the AND gate 10 and the NOR gate 11, and the comparison output of the comparator COM P 4 becomes the output of the AND gate 10 and the NOR gate 11.

As a result, first and second pulse signals corresponding to the driving direction of the motor M are derived from each output terminal of the AND gate 10 and the NOR gate 11.

The drive signal mentioned above is sent to the comparator C via the resistor R+s.
It also serves as a non-inverting input for OMPs. Comparator C
The OMP s constitutes a polarity determining means that determines the polarity of the drive signal with respect to the signal reference level by using 1/2 V ref as an inverted input.

The discrimination output of the comparator COMPs becomes the data (D>input) of the D-FF12.The D-FF12 uses the Q output of R8-FF4 in the triangular wave generation circuit 8 as a trigger (T) input, and its Q and Φ outputs are the AND gate 13. .14 each - human power.AND gate 13.14 is AND gate 10
and the outputs of the NOR gate 11, that is, the first and second pulse signals, are respectively inputted, and the Q of the D-FF 12.

A gate means is configured to output only one of the first and second pulse signals based on the d output.

Each output pulse of the AND gate 13.14 is supplied to a compensation circuit 15.16 that compensates for energy loss due to back electromotive force of back electromotive force absorbing diodes D+ and D2 in a motor drive circuit 18, which will be described later. Compensation circuit 15
, the output pulse of the AND gate 13 is connected to the resistor R17.
It becomes the base input of the transistor Q7 via the capacitor C2, and this transistor Q7 is connected in parallel with the capacitor C2. Both ends of the capacitor C2 are short-circuited when the transistor Q7 is turned on, and the charge is discharged to vtrR, and charging is started by the constant current source Ia when the transistor Q7 is turned off, that is, when the output pulse of the AND gate 13 disappears. be done. The voltage across the capacitor c2 becomes the inverting input of the comparator COMPs. Comparator COMP
s uses the reference voltage EO as a non-inverting input, and generates a high-level pulse signal when the voltage across the capacitor c2 is lower than the reference voltage Eo. As a result, the compensation circuit 15 becomes AND
A pulse signal obtained by adding a pulse having an approximately constant pulse width to the output pulse of the gate 13 is output.

Similar to the compensation circuit 15, the compensation circuit 16 also includes a resistor RI8, a transistor Qs, a capacitor (/3), a constant current source rb, and a comparator COMP7, and its operation is exactly the same as that of the compensation circuit 15.

Each output pulse of the compensation circuit 15 , 16 is supplied via a predrive circuit 17 to a motor drive circuit 18 .

In the motor drive circuit 18, the motor M is PNPN.
Upper transistor Q9 and NPN transistor Q +o and PNP transistor QII and NPN transistor Q
Each of the 12 collectors is connected between the common connection points. Transistors Q9, QIa, Q++, and Q12 are power transistors. Transistor Q9. Ql+
Each emitter is connected directly to the power source V, and each base is connected to a respective resistor RI9. It is connected to the power supply Vcc via R2G. On the other hand, the emitters of transistors QIQ and Q12 are both grounded, and the bases of each transistor are connected to resistors R2+ and R, respectively.
22 and a Zener diode ZD.
+ and connected to each collector via ZD2. Both ends of the motor M are diodes D+ and D2 for absorbing back electromotive force.
It is connected to the power supply Vcc via.

In the pre-drive circuit 17, the pulse signal supplied from the compensation circuit 15 drives the power transistor Q9 through a pre-drive stage consisting of resistors R23, R24 and a transistor Q13, and is inverted by an inverter 19 and then connected to a resistor. R25 to R27 and transistor Q1
The power transistor Q12 is driven through a predrive stage consisting of four. As a result, a current flows through the motor M in the direction of the arrow shown by the solid line in the figure, and the motor M is driven to rotate in the forward direction. Further, the pulse signal from the compensation circuit 15 is passed through the inverter 20 to the transistor Q +s
is also supplied to turn on the transistor Q+s when the motor M stops driving in the forward direction. As a result, the base and emitter of the power transistor Q12 are short-circuited by the transistor Q+s, so that the power transistor Q12 is instantly turned off. The reason for providing this transistor Q +s will be explained in detail later. The base of transistor Q+s is connected to power supply Vcc via resistor R28.

On the other hand, the pulse signal supplied from the compensation circuit 16 is
2B, R3] and the transistor Q16 through a predrive stage, and after being inverted by the inverter 21, the resistors R31 to R3 are inverted.
The power transistor Q 10 is driven through a predrive stage consisting of the transistor Q 33 and the transistor Q 17. As a result, a current flows through the motor M in the direction of the arrow shown by the broken line in the figure, and the motor M is driven to rotate in the opposite direction.

Further, the constant current source from the compensation circuit 16 is also supplied to the transistor Q +s via the inverter 22, and turns on the transistor Q +s when the reverse drive of the motor M is stopped. As a result, the base and emitter of the power transistor 010 are short-circuited by the transistor Q+a, so that the power transistor Q+o is instantly turned off. The base of transistor QCs is connected to power supply Vcc via resistor R34.

Next, the circuit operation of the PWM drive circuit according to the present invention will be explained.

First, the circuit operation of the triangular wave generation circuit 8 will be explained with reference to the waveform diagram of FIG. In the triangular wave generation circuit 8, the second
When the constant current 82 of the first constant current source 1 is in an inactive state, that is, when the transistor Q6 is turned on and the transistors Q3 and Q4 are turned off, the capacitor C1 As shown in the figure (a), it is charged with a certain slope angle. When the voltage across the capacitor CI reaches the upper limit reference level Vu of the comparator circuit 3, the comparator COM P + outputs a low level pulse (b)
is generated, and in response to this pulse (b), the Φ output (d) of R8-FF4 transitions to a low level.

This turns transistor Q6 off, so
The second constant current source 2 is in an activated state, that is, the transistor Q3
, Q4 are turned on, and a current twice the constant current of the first constant current source 1 is sucked.

As a result, the capacitor CI, which had been in the charging state, shifts to the discharging state, and as shown in FIG. 2(a), the capacitor CI is discharged with the same angle of inclination as during charging. Subsequently, the voltage across the capacitor C1 is set to the lower limit reference level V of the comparator circuit 3.
When the current level is reached, comparator COMP 2 generates a low level pulse (C), and in response to this pulse (C), R
d output (d) of 8-FF4 transitions to high level. As a result, the transistor Q6 is turned on and the second constant current source 2 is deactivated, so that the capacitor C is turned on again.
1 is charged at a constant angle of inclination by a constant current supplied from the first constant current source 1.

In this way, by repeating the charging and discharging operation of the capacitor C1 with the constant current from the first and second constant current sources 1.2, the voltage across the capacitor C1 is as shown by the solid line in FIG. 2(a). The signal changes into a triangular waveform as shown in FIG.
) is output as a second phase triangular wave signal φb having the same peak value as the first phase triangular wave signal φa and having an opposite phase. This two-phase triangular wave signal φa.

φb becomes a reference input of the comparator circuit 9.

A drive signal for the motor M having a signal reference level of 1/2 Vref is supplied as a comparison input of the comparison circuit 9.

Here, if the motor M is, for example, a spindle motor that rotationally drives a compact disc, the error signal obtained by comparing the reproduction synchronization signal from the disc with the reference synchronization signal becomes the drive signal, and based on this error signal, The drive control of the spindle motor is then performed. This is the so-called spindle servo.

In Fig. 3, the cross point of the two-phase triangular wave signals φa and φb is at the 1/2 Vrer level, and this 1/2
The PWM operation when the signal level of the drive signal is high and low with respect to the 2 V ref level will be described below.

In the comparator circuit 9, first, when the signal level of the drive signal is higher than <1/2Vref level as shown by the dashed line in FIG. Time t when the signal level of the one-phase triangular wave signal φa becomes low! The triangular wave signal φa transitions from a low level to a high level at , and remains at a high level until time t4 when the signal level of the triangular wave signal φa exceeds the signal level of the drive signal.

Furthermore, the output (C) of the comparator COMP4 transitions from high level to low level at time t2 when the signal level of the second phase triangular wave signal φb exceeds the signal level of the drive signal, At time t3 when it becomes low, it changes to high level again.

On the other hand, if the signal level of the drive signal is lower than <1/2Vref level as shown by the two-dot chain line in Figure (a) and has the same absolute value level as in the above case, the output (d) of the comparator COMP3 is the first phase triangular wave signal φa
Time t2 when the signal level of exceeds the signal level of the drive signal
The triangular wave signal φa transitions from a low level to a high level at , and remains at a high level until time t3 when the signal level of the triangular wave signal φa exceeds the signal level of the drive signal. Further, the output (e) of the comparator COMP4 transitions from high level to low level at time t1 when the signal level of the second phase triangular wave signal φb exceeds the signal level of the drive signal, and becomes lower than the signal level of the drive signal. At time t4, the level changes to high level again.

Each output of comparator COMP3 and COMP4 is AN
The D gate 10 and the NOR gate 11 are powered by two people, and the AND gate 10 is operated by two people when both of them are at a high level.
That is, when the signal level of the drive signal is higher than the 1/2 V ref level, a high level pulse (f) is output, and the N
The OR gate 11 outputs a high level pulse (q) when both of the two input signals are at a low level, that is, when the signal level of the drive signal is lower than the 1/2 V ref level. Therefore, the AND gate 10 and the NOR gate 11 output pulse signals @(f) and (Q) corresponding to the driving direction of the motor M. Note that here we have explained the case where the signal level of the drive signal is constant, so the pulse signal (f),
(Although the pulse width of l is constant, it is easy to understand that this pulse width changes depending on the signal level of the drive signal.

In this way, by generating two-phase triangular wave signals φa and φb with equal peak values and mutually opposite phases, and performing PWM operation using the linear portions of these two-phase triangular wave signals φa and φb, even if the triangular wave Even if ringing or so-called rounding occurs at the tip, there is no deterioration in linearity when the signal level of the drive signal is small.

Here, if the reference power supply voltage V ref fluctuates, PW
The pulse width of the pulse signal generated by M changes,
The driving power generated by this pulse signal changes in response to fluctuations in the power supply voltage.

That is, as shown in FIG. 4 (A>), if the pulse width of the pulse signal when the drive signal is at a certain signal level is To, the drive power due to this pulse signal is equal to the pulse width T.
o and the drive voltage Vo (JJ quasi-power supply voltage Vref), so if the drive voltage Vo becomes, for example, 1/2 due to fluctuations in the power supply voltage, the drive power will also be reduced to 1/2 as shown by the diagonal line. It will become.

However, in the triangular wave generation circuit 8, the first and second
The comparison reference level of the current value setting circuit 6 that sets the constant current values of the constant current sources 1 and 2 is set by dividing the reference power supply voltage Vref by resistors R11 and R12, and the reference level is also subject to fluctuations in the power supply voltage. Therefore, the current value setting circuit 6 changes the first value according to the fluctuation of the power supply voltage.
And the constant current value of the second constant current source 1.2 can be controlled.

As a result, the inclination angle of the triangular wave changes as shown in FIG. 4(B). On the other hand, the upper and lower comparison reference levels VLJ and VL of the comparison circuit 3 are also based on the resistances R5 to R8. Since it is set by dividing the power supply voltage Vre'f, if the reference voltage &'Z voltage yrer becomes 1/2, the comparison reference levels VLI and VL of the upper and lower limits also become 1/2.
2, and as a result, the peak value Vp of the triangular wave is shown in Figure 4 (B
), it becomes 1/2 of what it was before the power supply fluctuation. Therefore, by setting the inclination angle of the triangular wave so that the repetition period of the triangular wave is the same before and after the power fluctuation, a pulse signal with twice (2To) the pulse width before the fluctuation will be generated. Therefore, even if the drive voltage VD becomes 1/2, the drive power generated by the pulse signal remains the same as before the power supply fluctuation.

That is, in the triangular wave generation circuit 8, by controlling the peak value and slope angle of the triangular wave according to fluctuations in the electric voltage, the driving power generated by the pulse signal is adjusted to the reference power supply voltage Vr.
This means that it can always be kept constant regardless of fluctuations in ef. In addition,
The slope angle of the triangular wave is determined by the constant current values of the first and second constant current sources 1 and 2 and the capacitance of the capacitor C1.

In FIG. 1 again, the signal level of the drive signal is now at the fifth level.
If the change occurs as shown by the dashed line in Figure (a), two pulse signals (b) and (c) with pulse widths corresponding to the polarity and signal level of the drive signal will
are output from OR gate 11, and are output from AND gate 1, respectively.
3. Each of 14 - becomes human power. The drive signal is comparator C
It also serves as a comparison input for OMPs, and the signal reference level is 1/2.
The polarity with respect to Vref is determined. D-F which uses the comparison output (d) of this comparator COMP5 as data input.
F12 uses the output (e) of R8-FF4 in the triangular wave generation circuit 8 as a trigger input, and the output (e)
Q output (f>, (Q)) is generated at the falling edge of Q.

The 0 output (f), l) is supplied as a gate control signal to an AND gate 13.14.

In the above embodiment, the mouth output (e) of R8-FF4 was directly used as the trigger input of D-FF12, but the mouth output (e)
It is also possible to use a trigger input of the D-FF 12 via a pulse generator that generates pulses at the rising and falling timings of e). According to this, the period of polarity determination becomes 1/2, and the resolution can be doubled.

D-FF12 Q, CI ratio output f), (g> is motor M
For example, when the signal level of the drive signal is small and its polarity changes from positive to negative, the NOR gate 11 generates a reverse drive that occurs instantaneously as shown in FIG. 5(C). As for the pulse signal (first pulse), since the output (Q) is at a low level at the time of generation, the AND gate 14 operates to inhibit its output. The reason for this prohibition will be explained below.

Now, let us consider the case where a reverse drive pulse signal is instantaneously generated from the NOR gate 11 at a timing when the signal level of the drive signal is small and its polarity changes from positive to negative, as shown in FIG. 5(C). , in the motor drive circuit 18, the transistor Q is activated in response to the pulse signal shown in FIG. 5(b).
9. Q10 is turned on and drives the motor M in the forward direction, but as shown in FIG.
12 is in the off state, and transistors Q++, Q+.

turns on and attempts to drive motor M in the opposite direction.

Here, as shown in FIG. 6, a transistor generally has a capacitance CO between the base and emitter, so that the transistor that is turned on in response to the drive pulse (a) can be turned on from the time when the pulse (a) disappears. It has a characteristic that it requires a delay of one hour to FF before it shifts to the off state.Therefore, as described above, by generating the reverse drive pulse signal shown in FIG. 5(C), the transistor Qs .

Q12 is turned off and transistors Q11. QI
However, due to the one-time delay tOFF mentioned above, transistor QI2 cannot be turned off instantaneously, and there will be a period in which it is temporarily turned on at the same time as transistor Q. A large current may flow through Qll and Q12, leading to destruction of the transistors.

However, in this PWM drive circuit, the AND gate 13.
14, and these gates 13 and 14 are controlled based on the polarity determination result with respect to the signal reference level of the drive signal, so in the above example, the reverse direction drive shown in FIG. Since the output of the pulse signal can be inhibited by the AND gate 14 in response to the d output (0) of the D-FF 12, the transistor Q 12 will not be turned on at the same time as the transistor Q u.

In addition, in order to reduce the delay time topF of the power transistor Q12IQIO, the predrive circuit 17
are provided with transistors Q +s and Q +s. These transistors Q+s and Q+a instantaneously turn on in response to the disappearance of the drive pulses of power transistors Q+p and Q+e, and these transistors QI2.0I
By short-circuiting the base and emitter of O, the delay time tOFF can be shortened. The delay time tOFF of a transistor is generally about 1 to 2 μsec, but by providing the transistors Q+s and Q+s, it can be shortened to about 1/10, that is, about 100 nSeC.

Another embodiment for preventing the above-mentioned power transistors from turning on simultaneously is shown in FIG. In this figure, as described above, the first and second pulse signals (a) corresponding to the driving direction of the motor M are output from the AND gate 10 and the NOR gate 11, and these pulse signals are sent to the delay circuit 23, respectively.
．． 24, it is delayed by a predetermined time τ0. These delayed outputs (b) are supplied to three-state buffers 25 and 26, respectively. The first and second pulse signals (a) are also supplied to one-shot multivibrators 27 and 28, respectively. One shot multi vibrator 27.28
is at a low level for a certain period of time from the time of generation of the first and second pulse signals to their extinction, preferably until a time (2τ○) twice the delay time τ0 of the delay circuits 23 and 24 has elapsed. An output (C) is generated and supplied to the buffer 26.25 to inhibit the second and first pulse signals outputted from the delay circuit 24.23 from being supplied to the next stage.

FIG. 8 is an operating waveform diagram of the circuit in FIG. 7, and (a)
-(C) show the waveforms of the signals (a) to (C) in FIG. 7, respectively.

Referring to this waveform diagram, the circuit operation in FIG.
To explain the NO gate 11, a pulse signal (a
) is delayed by a time τ0 in the delay circuit 23 and becomes the drive pulse (b) for the motor M. At this time, in response to the low level inhibition signal (C) output from the one-shot multivibrator 27, the buffer 26 cuts off the output line of the other drive pulse. As a result, a certain period (time τ0
), the output of the local drive pulse is prohibited, so the time τ0 is the power transistor QI2 mentioned above.
．． By setting the delay time toFF of 0IO longer than the delay time toFF, power transistors Q9 and QIO (or Q
u and Q1? ) are never in the on state at the same time.

As mentioned earlier, the delay time t of the transistor
Since oFF is generally about 1 to 2 μsec, the time τ0
It is desirable to set it to about 5 μSeC.

In FIG. 1, first and second pulse signals corresponding to the driving direction of the motor M output from the AND gate 13.14 are respectively supplied to a compensation circuit 15.16. These compensation circuits 15 and 16 are for compensating for energy loss in the back electromotive force absorbing diodes D+ and D2 in the motor drive circuit 18. The energy loss in the back electromotive force absorption diodes D+ and D2 is almost constant and can be ignored when the pulse width of the pulse signal is large, but when the pulse width is small, the loss ratio increases. come. Therefore, as shown by the broken line in Fig. 9, the gain decreases in the region where the pulse width of the pulse signal is small, so when the pulse width is small, energy loss occurs in the back electromotive force absorbing diodes DI and D2. It would be better to compensate them for that.

Here, i! Iti(8) To explain the circuit operation of the circuit 15 with reference to the waveform diagram in FIG. When the transistor Q7 turns on, the charge in the capacitor C2 is instantly discharged, and from the time when the input pulse (a) disappears, the capacitor C2 is charged again with a constant current. Therefore, the voltage across the capacitor C2 is The voltage changes as shown in Fig. 10(b).The voltage (b) across the comparator
is compared with the reference voltage E○, and as a result, the comparator CO
At the output end of the M P 7, a pulse signal (C) is obtained having a pulse width corresponding to the period from the generation of the input pulse (a) to the elapse of a predetermined time Ta after the input pulse (a) disappears.

In other words, a constant pulse width T with respect to the input pulse (a)
a has been added, and this added pulse width T
The energy loss in the back electromotive force absorbing diodes D+ and D2 can be compensated for by the energy corresponding to the amount a.

FIG. 11 shows the input/output characteristics of the compensation circuits 15 and 16, that is, the relationship between the pulse width of the input pulse and the added pulse width. In the pulse width region (■) of the input pulse where the input pulse cannot drop to the level where it cannot be lowered, no pulse width is added, but in the region (■) where the input pulse reaches zero level below the reference voltage Eo, the additional pulse width changes proportionally and reaches the zero level. In the subsequent region ■, the pulse width added is a fixed width. In other words, region ■ where the pulse width of the input pulse is extremely small.

In case (2), there is no addition of pulse width or the additional pulse width changes proportionally, but this is due to the fact that the rise and fall of the input pulse are not steep but actually gentle; In the region (2), the gain can be improved as shown by the solid line in FIG.

The compensation circuits 15 and 16 are not limited to the configurations of the above embodiments, but may include, for example, as shown in FIG.
Constant pulse width T in response to the rising edge of the input pulse
The pulse generating circuit 29 may be configured to include a pulse generating circuit 29 that generates a pulse signal having a pulse signal having a value of b, and an OR gate 30 that calculates the logical sum of the output pulse of the pulse generating circuit 29 and the input pulse. In this configuration, when the pulse width of the input pulse is smaller than the pulse width Tb, a pulse signal having the pulse width Tb is always output from the OR gate 30, so that the pulse width of the input pulse is the opposite of that when the pulse width is small. The energy loss in the electromotive force absorbing diodes D+ and D2 is compensated for, and when the pulse width of the input pulse is greater than the pulse width Tb, the pulse width of the input pulse is not changed.

In the above embodiment, a case has been described in which the application is applied to a drive circuit of a spindle motor that rotationally drives a compact disc, but the application is not limited to this, but is applicable to a carriage motor that drives a pickup, a focus of information reading light in a pickup, etc. It can also be applied to drive circuits for focus actuators and tracking actuators that control tracking, and can be widely applied not only to compact disc players but also to drive circuits for various loads in various devices.

As explained above, according to the triangular wave generation circuit according to the present invention, a first constant current source and a second constant current source having a constant current value twice that of the first constant current source are provided. The structure is such that a triangular wave signal is generated by charging and discharging a capacitor (power storage means) with a constant current by on/off control of this second constant current source, and one end of the capacitor is connected to a reference potential point. Since it is a circuit configuration that can be easily configured by
It is possible to reduce the number of terminal bins when

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
Figure 3 is a waveform diagram of each part to explain the circuit operation of the triangular wave generation circuit in the figure. Figure 3 is a waveform diagram of each part to explain the operation of generating two pulse signals corresponding to the drive direction of the load by PWM operation. (A>, (B) are waveform diagrams to explain the operation of changing the slope angle and peak value of the triangular wave in response to fluctuations in the power supply voltage. Figure 5 is a waveform diagram for explaining the operation of changing the slope angle and peak value of the triangular wave in response to fluctuations in the power supply voltage. Figure 6 is a diagram for explaining the circuit operation of the simultaneous ON prevention circuit for power transistors, Figure 6 is a diagram for explaining the toFF delay time of the transistor, Figure 7 is another embodiment of the simultaneous ON prevention circuit. Fig. 8 is a waveform diagram of each part to explain the circuit operation of Fig. 7, and Fig. 9 shows the change in gain due to energy loss due to back electromotive force in the back electromotive force absorption diode. Figure 10 is a waveform diagram for explaining the circuit operation of a compensation circuit that compensates for energy loss due to back electromotive force in a back electromotive force absorption diode, and Figure 11 shows the input/output characteristics of such a compensation circuit. figure,
FIG. 12 is a block diagram showing another embodiment of such a compensation circuit, FIG. 13 is a diagram for explaining the operation of a conventional PWM, and FIG. 14 is a circuit diagram showing a conventional example of a triangular wave generating circuit. Explanation of symbols of main parts 1...First constant current source 2...Second constant current source 3.9...Comparison circuit 8... Triangular wave generation circuit

Claims (1)

[Claims] a first constant current source; a second constant current source that is connected in series with the first constant current source and sinks twice as much current as the first constant current source; and the first and second constant current sources. a power storage means connected between a common connection point of the current source and a reference potential point; a comparison circuit for monitoring the output level of the power storage means; and a power storage means for controlling the second constant current source based on the output of the comparison circuit. A triangular wave generation circuit, comprising: a control means for activating the power storage means, and outputs an output signal of the power storage means as a triangular wave signal.