JPS6264272A - Controller for pwm inverter - Google Patents

Controller for pwm inverter

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Publication number
JPS6264272A
JPS6264272A JP60200536A JP20053685A JPS6264272A JP S6264272 A JPS6264272 A JP S6264272A JP 60200536 A JP60200536 A JP 60200536A JP 20053685 A JP20053685 A JP 20053685A JP S6264272 A JPS6264272 A JP S6264272A
Authority
JP
Japan
Prior art keywords
voltage
input
inverter
frequency
reference signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60200536A
Other languages
Japanese (ja)
Inventor
Hidehiko Kikuchi
秀彦 菊池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60200536A priority Critical patent/JPS6264272A/en
Publication of JPS6264272A publication Critical patent/JPS6264272A/en
Pending legal-status Critical Current

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  • Control Of Ac Motors In General (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To hold an AC output voltage constant irrespective of the variation in an input voltage by controlling the frequency and the pulse width of an inverter by a reference frequency and a corrected voltage reference signal. CONSTITUTION:An input DC voltage V is detected by a voltage detector 11, amplified by an amplifier 6e, a reference voltage (v) generated from a V/F characteristic generator 2 is then divided by a divider 12, amplified by an amplifier 6e, a voltage reference signal is calculated, and input to D/A converters 5a, 5b. A reference frequency is also input from a microprocessor 4 to the converters 5a, 5b. The outputs of the converters 5a, 5b are applied through amplifiers 6a-6c to comparators 9a-9c. The comparators 9a-9c output drive signals for turning ON or OFF switching elements of phases of an inverter.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は直流電源を用いたpuM(パルス幅変調)イン
バータの制御装置にかかり、特にV/F (出方電圧と
出力周波数の比)一定制御における直流電源電圧変動の
補正回路に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a control device for a PUM (Pulse Width Modulation) inverter using a DC power supply, and particularly to a control device for a PUM (pulse width modulation) inverter using a DC power supply, and in particular a constant V/F (ratio of output voltage to output frequency) control. This invention relates to a correction circuit for DC power supply voltage fluctuations.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

V/F一定#御をする内Sインバータの従来の一例を第
4図に示す。
An example of a conventional internal S inverter that controls V/F at a constant level is shown in FIG.

第4図において、出力指令設定器1で設定された出力指
令信号はV/F特性発生器2に入力され、その出力はV
F変換器3を介して周波数基準f*のパルス列に変換さ
れてマイクロプロセッサ4のクロックに入力され、内部
で処理されてU相およびW相用正弦波基準パルスfU、
fすが出力され、それぞれ乗算形OA変換器5a、 5
bに入力される。
In FIG. 4, the output command signal set by the output command setting device 1 is input to the V/F characteristic generator 2, and its output is V
It is converted into a pulse train of frequency reference f* via the F converter 3, inputted to the clock of the microprocessor 4, and processed internally to produce a sine wave reference pulse fU for the U phase and W phase,
f is output, and multiplier type OA converters 5a, 5 respectively.
b.

一方上記乗算形DA変換器5a、5bには上記V/F特
性発生器2からの電圧基準信号v*(第6図に示すよう
にV町よf*に比例する。)も入力されて乗算され、ア
ナログ値に変換された後さらに増幅器6a。
On the other hand, the voltage reference signal v* from the V/F characteristic generator 2 (as shown in FIG. After being converted into an analog value, it is further passed through an amplifier 6a.

6cで増幅されてそれぞれU相およびW相の正弦波制御
信号Sυ、S讐となる。
6c and become U-phase and W-phase sine wave control signals Sυ and Sυ, respectively.

上記正弦波制御信号SU+ SWはさらに抵抗7a、 
7bおよび増幅器6bを介してV相の正弦波制御信号S
νに変換され、発振器8で発生された三角波搬送波Tと
それぞれの比較器9a、 9b、 9 cで比較されて
インバータのU相、■相、W相の各スイッチング素子を
オンオフさせるドライブ信号を出力し、これによって3
相の正弦波インバータ出力を得ている。
The sine wave control signal SU+SW is further connected to a resistor 7a,
V-phase sine wave control signal S via 7b and amplifier 6b.
It is converted into ν and compared with the triangular carrier wave T generated by the oscillator 8 by the respective comparators 9a, 9b, and 9c, and outputs a drive signal that turns on and off each switching element of the U phase, ■ phase, and W phase of the inverter. and this results in 3
You are getting a phase sine wave inverter output.

第7図は上記各部信号波形を示すもので、(A)−は1
京、(B)はfu、(C)はTy SLJw sv、(
D)はU相ドライブ信号、(E)はV相ドライブ信号を
示している。
Figure 7 shows the signal waveforms of each part mentioned above, (A) - is 1
Kyo, (B) is fu, (C) is Ty SLJw sv, (
D) shows a U-phase drive signal, and (E) shows a V-phase drive signal.

上記第4図の回路では周波数基準f*とドライブ信号と
が一対一で対応するので、インバータ出力電圧は主回路
入力直流電圧Vに比例し、従って入力直流電圧Vが上昇
するとV/F比が増大し、■が低下するとV/F比が減
少するという問題が生じ、特に交流電動機駆動に用いる
場合に問題となる。
In the circuit shown in Figure 4 above, there is a one-to-one correspondence between the frequency reference f* and the drive signal, so the inverter output voltage is proportional to the main circuit input DC voltage V, and therefore when the input DC voltage V increases, the V/F ratio increases. When the ratio increases and the value of (2) decreases, a problem arises in that the V/F ratio decreases, which is particularly a problem when used to drive an AC motor.

インバータ出力電圧が入力電圧変動の影響を受けなくす
るには、第5図に示すように出力電圧を整流器10で整
流し、フィードバック信号として偏差検出器13で電圧
基準Vと比較し、その偏差を電圧基準Vに加算し、増幅
器6dで増幅して実際の電圧基準信号−として用いる方
法があるが、このようなフィードバック制御では入力電
圧変動が太きいとき出力電圧の不安定を招くという問題
がある。
In order to prevent the inverter output voltage from being affected by input voltage fluctuations, the output voltage is rectified by a rectifier 10 as shown in FIG. 5, and the deviation is compared with the voltage reference V by a deviation detector 13 as a feedback signal. There is a method of adding it to the voltage reference V, amplifying it with an amplifier 6d, and using it as an actual voltage reference signal, but such feedback control has the problem of causing instability of the output voltage when input voltage fluctuations are large. .

入力電圧の影響を防ぐ他の方法として、入力電圧Vを−
たんチョッパ回路に通して一定の直流電圧に変換し、こ
れを入1カ直流電圧として用いる方法があるが、この場
合は装置全体が大きくなって、寸法およびコストの面で
問題となる。
Another way to prevent input voltage effects is to set the input voltage V to -
There is a method of passing the voltage through a chopper circuit to convert it into a constant DC voltage and using this as the input DC voltage, but in this case, the entire device becomes large, which poses problems in terms of size and cost.

〔発明の目的〕[Purpose of the invention]

本発明は、入力電圧の変動にかかわらず交流出力電圧を
一定に保持するV/F制御PlIMインバータの制御装
置を提供することを目的としている。
An object of the present invention is to provide a control device for a V/F-controlled PlIM inverter that maintains an AC output voltage constant regardless of input voltage fluctuations.

〔発明の概要〕[Summary of the invention]

本発明は、設定された基準周波数に対応してV/F一定
制御する直流電圧入力PWMインバータの制御装置にお
いて、上記基準周波数に比例する電圧基準を実際の直流
入力電圧と標準直流入力電圧との比で除算して実際の電
圧基準信号とする電圧補正回路を備え、上記基準周波数
と補正された電圧基準信号とを用いてインバータの周波
数およびパルス幅を制御し、これによって直流入力電圧
の変動にかかわらずV/F比を一定に保持できるように
したものである。
The present invention provides a control device for a DC voltage input PWM inverter that performs constant V/F control in accordance with a set reference frequency. It is equipped with a voltage correction circuit that divides by the ratio to obtain an actual voltage reference signal, and uses the above reference frequency and the corrected voltage reference signal to control the frequency and pulse width of the inverter, thereby adjusting to fluctuations in the DC input voltage. This allows the V/F ratio to be kept constant regardless of the situation.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例を第1図に示す。 An embodiment of the present invention is shown in FIG.

第1図は従来の第4図に比べて、電圧基準信号−を主回
路入力直流電圧Vに応じて補正する電圧補正回路が設け
られており、他は従来の第4図と同じである。
Compared to the conventional circuit shown in FIG. 4, FIG. 1 is provided with a voltage correction circuit that corrects the voltage reference signal - according to the main circuit input DC voltage V, and other aspects are the same as the conventional circuit shown in FIG. 4.

すなわち入力直流電圧Vは電圧検出器11で検出され、
増幅器6eで増幅された後1割算器12でV/F特性発
生器2の発生する基準電圧Vを割算し、さらに増幅器6
dで増幅して最終的に電圧基準信号−として、 オ − vo。
That is, the input DC voltage V is detected by the voltage detector 11,
After being amplified by the amplifier 6e, the reference voltage V generated by the V/F characteristic generator 2 is divided by the divider 12, and then the reference voltage V generated by the V/F characteristic generator 2 is divided by the divider 12.
d and finally as a voltage reference signal.

■ を算出してDA変換器5a、5bに入力する。ここで■
(2) is calculated and input to the DA converters 5a and 5b. Here■
.

は入力直流電圧Vの標準値(すなわちVがそのまま−と
して使用できる入力直流電圧)である。
is the standard value of the input DC voltage V (that is, the input DC voltage where V can be used as is as -).

第2図はV>Voの場合のVとV*の関係を示している
FIG. 2 shows the relationship between V and V* when V>Vo.

このように人力直流電圧Vに応じて電圧基準信号V*を
補正すると、入力直流電圧Vが標準値v0より高いとき
はそれに反比例して電圧基準信号V木が低下し、各正弦
波制御信号Sυ? SV* SVの波高値も小さくなり
、各相のドライブ信号のオン期間が入力直流電圧Vに反
比例して小さくなり、結局インバータの出力電圧は入力
直流電圧Vの変動にかかわらず周波数基準fxに比例し
て一定に保持され、V/F一定制御が安定に行われる。
When the voltage reference signal V* is corrected according to the human-powered DC voltage V in this way, when the input DC voltage V is higher than the standard value v0, the voltage reference signal V tree decreases in inverse proportion to it, and each sine wave control signal Sυ ? SV* The peak value of SV also becomes smaller, and the on-period of the drive signal of each phase becomes smaller in inverse proportion to the input DC voltage V. Eventually, the output voltage of the inverter becomes proportional to the frequency reference fx regardless of fluctuations in the input DC voltage V. V/F constant control is performed stably.

第3図は本発明の他の実施例を示すもので、この場合は
インバータの出力電圧を整流器10を通してフィードバ
ックし、電圧基準Vとの偏差を偏差検出@13で取出し
て割算器12の出力に加算しており、これによって直流
入力電圧変動以外の要因によるインバータ出力電圧の変
動も抑制し、さらに安定した出力電圧が得られるように
している。
FIG. 3 shows another embodiment of the present invention. In this case, the output voltage of the inverter is fed back through the rectifier 10, the deviation from the voltage reference V is detected by the deviation detection @ 13, and the output voltage of the divider 12 is output. This suppresses fluctuations in the inverter output voltage due to factors other than DC input voltage fluctuations, thereby making it possible to obtain a more stable output voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、直流入力電圧の変
動に応じて同じ周波数基準に対応する電圧基準信号を補
正してPWHにおけるパルス幅を変える簡単な補正回路
を追加するだけで、直流入ヵ電圧の変動にかかわらずV
/F比を一定に保持できる合理的なPli1Mインバー
タの制御装置が実現できる。
As explained above, according to the present invention, by simply adding a simple correction circuit that corrects the voltage reference signal corresponding to the same frequency reference according to fluctuations in the DC input voltage and changes the pulse width in the PWH, the DC input voltage can be changed. V regardless of voltage fluctuations
A rational Pli1M inverter control device that can maintain the /F ratio constant can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図、第2図は
第1図における電圧基準補正回路の動作を示す特性図、
第3図は本発明の他の実施例を示すブロック図、第4図
および第5図はそれぞれ従来の制御装置の一例を示すブ
ロック図、第6図は第4図における周波数基準信号と電
圧基準信号との関係を示す特性図、第7図はPvM制御
における各部波形図である。 1     出力指令設定器 2      V/F特性発生器 3      VF変換器 4     マイクロプロセッサ 5a、5b    乗算形DA変換器 68〜6e    増幅器 8     発振器 9a、 9b、 9c  比較器 10      整流器 11      電圧検出器 12      割算器 13      偏差検出器 (8733)代理人 弁理士  猪 股 祥 晃(ほか
1名)第 2 図 茅3図 茅6図 第 7 区
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a characteristic diagram showing the operation of the voltage reference correction circuit in FIG. 1,
FIG. 3 is a block diagram showing another embodiment of the present invention, FIGS. 4 and 5 are block diagrams each showing an example of a conventional control device, and FIG. 6 is a frequency reference signal and voltage reference in FIG. 4. A characteristic diagram showing the relationship with the signal, and FIG. 7 is a waveform diagram of each part in PvM control. 1 Output command setter 2 V/F characteristic generator 3 VF converter 4 Microprocessor 5a, 5b Multiplying type DA converter 68-6e Amplifier 8 Oscillator 9a, 9b, 9c Comparator 10 Rectifier 11 Voltage detector 12 Divider 13 Deviation Detector (8733) Agent Patent Attorney Yoshiaki Inomata (and 1 other person) Section 2, Figure 3, Figure 6, Section 7

Claims (1)

【特許請求の範囲】[Claims] 設定された基準周波数に対応してV/F一定制御する直
流電圧入力PWMインバータの制御装置において、上記
基準周波数に比例する電圧基準を実際の直流入力電圧と
標準直流入力電圧との比で除算して実際の電圧基準信号
とする電圧補正回路を備え、上記基準周波数と補正され
た電圧基準信号とを用いてインバータの周波数およびパ
ルス幅を制御することを特徴とするPWMインバータの
制御装置。
In a control device for a DC voltage input PWM inverter that performs constant V/F control in accordance with a set reference frequency, the voltage reference proportional to the reference frequency is divided by the ratio of the actual DC input voltage and the standard DC input voltage. 1. A control device for a PWM inverter, comprising a voltage correction circuit that uses the reference frequency as an actual voltage reference signal, and controls the frequency and pulse width of an inverter using the reference frequency and the corrected voltage reference signal.
JP60200536A 1985-09-12 1985-09-12 Controller for pwm inverter Pending JPS6264272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60200536A JPS6264272A (en) 1985-09-12 1985-09-12 Controller for pwm inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60200536A JPS6264272A (en) 1985-09-12 1985-09-12 Controller for pwm inverter

Publications (1)

Publication Number Publication Date
JPS6264272A true JPS6264272A (en) 1987-03-23

Family

ID=16425937

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60200536A Pending JPS6264272A (en) 1985-09-12 1985-09-12 Controller for pwm inverter

Country Status (1)

Country Link
JP (1) JPS6264272A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01174275A (en) * 1987-12-28 1989-07-10 Toshiba Corp Controlling method of power converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01174275A (en) * 1987-12-28 1989-07-10 Toshiba Corp Controlling method of power converter

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